VMWARE, INC.

Patent Trials and Appeals Board

Jan 7, 2022

2020006086 (P.T.A.B. Jan. 7, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/751,194 06/26/2015 Jinto ANTONY C329 (VMW-1190) 4654 152666 7590 01/07/2022 LOZA & LOZA, LLP/VMware 305 N. Second Ave., #127 Upland, CA 91786 EXAMINER KABIR, MOHAMMAD H ART UNIT PAPER NUMBER 2199 NOTIFICATION DATE DELIVERY MODE 01/07/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ipadmin@vmware.com tomh-pto@lozaip.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte JINTO ANTONY, SUDHISH P.T., and MADHUSUDHANAN GANGADHARAN ____________ Appeal 2020-006086 Application 14/751,1941 Technology Center 2100 _______________ Before JAMES B. ARPIN, HUNG H. BUI, and AMBER L. HAGY, Administrative Patent Judges. BUI, Administrative Patent Judge. DECISION ON APPEAL Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s final rejection of claims 1-7, 9-14, 16-19, and 21. Appeal Br. 10-14 (Claims App.). We have jurisdiction under 35 U.S.C. § 6(b). We reverse.2 1 “Appellant” refers to “applicant(s)” as defined in 37 C.F.R. § 1.42 (2012). VMware, Inc. is identified as the real party in interest. Appeal Br. 1. 2 We refer to Appellant’s Appeal Brief filed April 17, 2020 (“Appeal Br.”); Reply Brief filed August 28, 2020 (“Reply Br.”); Examiner’s Answer mailed June 22, 2020 (“Ans.”); Final Office Action mailed August 22, 2019 (“Final Act.”); and Specification filed June 26, 2015 (“Spec.”). Appeal 2020-006086 Application 14/751,194 2 STATEMENT OF THE CASE Appellant’s claimed invention relates to “a system [shown in Figure 1] for facilitating parallelized configuration of multiple virtual machines [VMs].” Spec. ¶ 13. Figure 1 depicting virtual machine (VM) system, is reproduced below with our annotations emphasizing elements 101, 108, 116, and 124(1): Figure 1 depicts virtual machine (VM) system 100 including central VM console management module (“central manager”) 102 providing an interface for an administrator to input, via input device 107, and configure multiple VMs 126 in a parallel manner, via configuration manager 108. Spec. ¶ 15. According to Appellant, Configuration manager 108 controls the configuration of VMs 126 based on administrator input via input device 107, based on Appeal 2020-006086 Application 14/751,194 3 scripts 112, and based on display data received from each VM 126 (via I/O multiplexer 118) and analyzed by image processor 110 . . . An administrator may “attach” any number of VMs 126 to the input/output multiplexer 118 in order to replicate commands for those VMs 126. In various embodiments, I/O multiplexer 118 replicates commands only for virtual machines 126 that are attached and, similarly, combines display only from virtual machines 126 that are attached. Spec. ¶ 16 (emphasis added). Claims 1, 10, and 17 are independent. Claim 1 is representative, as reproduced below with disputed limitations emphasized and bracketed numerals added for clarity: 1. A method for parallelizing execution of configuration operations for a plurality of virtual machines, the method comprising: identifying a first command for the plurality of virtual machines; determining that the first command comprises a command from an input device for execution by each virtual machine in the plurality of virtual machines; replicating the first command for each of the virtual machines in the plurality of virtual machines to generate first replicated commands; [1] controlling each virtual machine of the plurality of virtual machines according to the first replicated commands via an input/output multiplexer, wherein the configuration of the virtual machines is modified from a first common state to a second common state; and [2] tracking one or more display data frames received from the plurality of virtual machines by the input/output multiplexer, wherein the input/output multiplexer waits for all of the plurality of virtual machines to advance to a next display data frame. Appeal Br. 14 (Claims App.). Appeal 2020-006086 Application 14/751,194 4 REJECTION3 AND REFERENCES Claims 1-7, 9-14, 16-19, and 21 stand rejected under 35 U.S.C. § 103 as obvious over the combined teachings of Talagala et al. (US 2013/0097369 A1; published Apr. 18, 2013; “Talagala”) and Hakura et al. (US 2014/0118362 A1; published May 1, 2014). Final Act. 4-28. ANALYSIS Claim 1 In support of the obviousness rejection of claim 1, the Examiner finds the combination of Talagala and Hakura teaches all of the limitations of Appellant’s claimed “method for parallelizing execution of configuration operations for a plurality of virtual machines,” including the disputed limitations: [1] controlling each virtual machine of the plurality of virtual machines according to the first replicated commands via an input/output multiplexer, wherein the configuration of the virtual machines is modified from a first common state to a second common state [Hakura ¶¶ 10, 97]; and [2] tracking one or more display data frames received from the plurality of virtual machines by the input/output multiplexer, wherein the input/output multiplexer waits for all of the plurality of virtual machines to advance to a next display data frame [Talagala ¶¶ 6, 361]. Final Act. 4-9 (citing Talagala ¶¶ 6, 361; Hakura ¶¶ 10, 97). Based on the teachings of Talagala and Hakura, the Examiner finds, [i]t would have been obvious . . . to apply the known technique 3 The Examiner withdraws the rejection of claims 8 and 15 under 35 U.S.C. § 103 as obvious over the combined teachings of Talagala, Hakura, and Kannan et al. (US 20014/0196029 A1; published July 10, 2014). Ans. 3. As such, we do not consider here the patentability of claims 8 and 15. Appeal 2020-006086 Application 14/751,194 5 of Hakura in the same way to the system of Talagala to enhance barrier mechanism, monitoring, displaying data frame and modified from a first common state to a second common state of Talagala in the same manner as that of Hakura. Id. at 9 (citing Hakura ¶¶ 9, 10, 32, 97, Figures 2, 3B-6). Appellant disputes: (1) the Examiner’s findings regarding the teachings of Talagala and Hakura, as well as (2) the Examiner’s stated reason to combine the teachings of Talagala and Hakura. First, Appellant contends neither Talagala nor Hakura, alone or in combination, teaches or suggests, [1] controlling each virtual machine of the plurality of virtual machines according to the first replicated commands via an input/output multiplexer, wherein the configuration of the virtual machines is modified from a first common state to a second common state, as recited in claim 1. Appeal Br. 3-5; Reply Br. 2-3 (emphasis added). In particular, Appellant argues the cited portions of Hakura merely describe: (1) “a graphics subsystem” [implementing a tiling architecture, shown in Figure 6, that includes multiple processing entities (e.g., first and second processing entities) that process work related to the different tiles in parallel (e.g., first and second batches of primitives and a barrier command in between the first and second batches of primitives); and (2) the use of “a barrier command 504” in the context of non-tiled barrier functionality, shown in Figure 5, to reset and cause “both [the] first [pre-raster operations (PROP)] unit 525(0) and second PROP unit 525(1) to begin processing work received after the barrier command 504.” Appeal Br. 4 (citing Hakura ¶¶ 10, 97). According to Hakura, the PROP unit is configured to perform, among other things, early z-testing, optimizations for color blending, and address translation. Hakura ¶ 83. Appeal 2020-006086 Application 14/751,194 6 Appellant argues Hakura does not teach or suggest any “virtual machine as claimed” or any modification of configurations of the “virtual machines” from “a first common state to a second common state.” Appeal Br. 4-5; Reply Br. 2. The Examiner does not respond to Appellant’s arguments sufficiently. Instead, the Examiner takes a new position that (1) Talagala teaches “virtual machines and how virtual machines are reconfigured into different states/configurations,” (2) Hakura teaches “how well know concept of ‘barrier’ command modified from a first command state to a second common state based on setting a flag,” and, as such, (3) “applying . . . Hakura to the environment of Talagala discloses a plurality of virtual machines are configured into different states/configurations based on settings of flags to process barrier based work.” Ans. 3-7 (citing Talagala ¶¶ 296, 362, 429; Hakura ¶¶ 81, 94, 102). Second, Appellant contends neither Talagala nor Hakura, alone or in combination, teaches or suggests, [2] tracking one or more display data frames received from the plurality of virtual machines by the input/output multiplexer, wherein the input/output multiplexer waits for all of the plurality of virtual machines to advance to a next display data frame, as recited in claim 1. Appeal Br. 5-7 (citing Talagala ¶¶ 6, 361); Reply Br. 3-4. Appellant argues the cited portions of Talagala only describe (1) the use of a barrier completion module as part of storage controller 104 within storage device 102, shown in Figure 1, to determine completion of a serializing instruction flushing data from a processor cache to an auto- commit buffer’ and (2) the use of a storage management layer (SML) 1050 to (i) provide user access to auto-commit memory (ACM) 1011, (ii) allocate, Appeal 2020-006086 Application 14/751,194 7 map or unmap ACM buffers, shown in Figure 10, and in some embodiments, (iii) “maintain metadata tracking the associations between logical identifiers and/or address ranges in the memory system 1018 and auto-commit buffers 1013.” Appeal Br. 6-7 (citing Talagala ¶¶ 6, 361). The Examiner also does not respond to Appellant’s arguments sufficiently. Instead, the Examiner takes a new position that (1) paragraph 32 of Hakura “teaches that the barrier processing leads to displaying of data frames resulting from the barrier processing”; (2) paragraph 32, Figures 3B-6 of Talagala teach “the input/output multiplexer waits for all of the plurality of virtual machines to advance in barrier processing” and, without any explanation, (3) “the combination of Talagala and Hakura teaches ‘the input/output multiplexer waits for all the plurality of virtual machines to advance to barrier processing.” Ans. 8-9 (citing Talagala ¶ 6; Hakura ¶ 32, Figs. 3B-6). We do not agree with the Examiner’s new positions. Obviousness is a question of law based on underlying factual findings, In re Baxter, 678 F.3d 1357, 1361 (Fed. Cir. 2012), including what a reference teaches, In re Beattie, 974 F.2d 1309, 1311 (Fed. Cir. 1992), and the existence of a reason to combine references, In re Hyon, 679 F.3d 1363, 1365-66 (Fed. Cir. 2012). At the outset, we note that neither Talagala nor Hakura, alone or in combination, teaches or suggests Appellant’s claimed “method for parallelizing execution of configuration operations for a plurality of virtual machines,” including the disputed limitations recited in Appellant’s claim 1. For example, Talagala teaches “an apparatus, system, and method [] for auto-commit memory [ACM] management” and “auto-commit memory synchronization operations” in the context of a host processor relative to a non-volatile storage device, shown, for example, in Figures 1, 10-11. The Appeal 2020-006086 Application 14/751,194 8 purpose of Talagala is to flush data from a processor cache to an auto- commit memory (ACM), even “if a host device experiences a power failure or other restart event.” Talagala ¶¶ 2-7; Abstract. Talagala’s Figure 1 is reproduced below: Figure 1 depicts the relationship between host processor 114 and storage device 102 to improve data management in the event of a power failure. Talagala ¶¶ 44, 51. Talagala’s Figure 11 depicting the more detailed relationship between host processor 1014 and storage device 1102 is reproduced below with our annotations emphasizing elements 1111 and 1016 and noting that ACM is an abbreviation for “auto-commit memory”: Appeal 2020-006086 Application 14/751,194 9 Figure 11 depicts the relationship between host processor 1014 and storage device 1102 including ACM 1111 (1011, shown in Figure 10) and ACM buffer 1013. Talagala ¶¶ 267, 273. According to Talagala, ACM buffer 1013 is configured to receive data destaged (or flushed) from a cache of processor 1024 to ACM buffer 1013 in response to a serializing instruction. Talagala ¶ 6. Paragraph 170 of Talagala describes storage controller 104, shown in Figure 1, as including “a MUX 350 that comprises an array of multiplexers 350a-n where each multiplexer is dedicated to a row in the solid-state Appeal 2020-006086 Application 14/751,194 10 storage array 110.” However, using Talagala’s MUX to access to storage array 110 is not the same as Appellant’s claimed “input/out multiplexer” used in the context of “controlling each virtual machine of the plurality of virtual machines according to the first replicated commands . . ., wherein the configuration of the virtual machines is modified from a first common state to a second common state” as recited in claim 1 (emphasis added). Likewise, paragraph 296 of Talagala describes the auto-commit memory (ACM) 1010, shown in Figure 10, as “communicatively coupled to a host 1014” and like the host 114, “may comprise operating systems, virtual machines, applications [and] processor complex 1012” and, as such, “an ACM user may refer to an operating system, a virtual machine operating system (e.g., hypervisor) . . . or other program process.” However, using Talagala’s ACM to refer to VM operating system is not the same as Appellant’s claimed “controlling each virtual machine of the plurality of virtual machines according to the first replicated commands . . ., wherein the configuration of the virtual machines is modified from a first common state to a second common state” as recited in claim 1. As a secondary reference, Hakura does not remedy the noted deficiencies of Talagala to achieve Appellant’s claimed method because Hakura only teaches “a graphics subsystem” [implementing a tiling architecture, shown in Figure 6, that includes multiple processing entities (e.g., first and second processing entities) that process work related to the different tiles in parallel (e.g., first and second batches of primitives and a barrier command in between the first and second batches of primitives). Hakura ¶¶ 10, 97). Like Talagala, Hakura does not teach or suggest any of Appellant’s claimed “virtual machine” or “parallelizing execution of configuration Appeal 2020-006086 Application 14/751,194 11 operations for a plurality of virtual machines” and, more importantly, the claimed “controlling each virtual machine of the plurality of virtual machines according to the first replicated commands via an input/output multiplexer, wherein the configuration of the virtual machines is modified from a first common state to a second common state” as recited in claim 1 (emphasis added). Therefore, we are persuaded by Appellant’s arguments that neither Talagala nor Hakura, teaches or suggests any modification of configurations of the “virtual machines” from “a first common state to a second common state” including the disputed limitations of Appellant’s claim 1. Lastly, we note the Examiner’s rationale to incorporate the teachings of Hakura into Talagala is insufficient to support the combination as required by KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007); and In re Kahn, 441 F.3d 977, 988 (Fed Cir. 2006) (“[R]ejections on obviousness grounds cannot be sustained by mere conclusory statements; instead, there must be some articulated reasoning with some rational underpinning to support the legal conclusion of obviousness.”). For example, the Examiner reasons [i]t would have been obvious . . . to apply the known technique of Hakura in the same way to the system of Talagala to enhance barrier mechanism, monitoring, displaying data frame and modified from a first common state to a second common state of Talagala in the same manner as that of Hakura. Final Act. 9. However, “enhancing barrier mechanism, monitoring, displaying data frame [] from a first common state to a second common state,” as suggested by the Examiner, do not facilitate parallelized configuration of multiple virtual machines in the manner recited in Appellant’s claim 1. Appeal 2020-006086 Application 14/751,194 12 For these reasons, we do not sustain the Examiner’s obviousness rejection of claim 1 and of its dependent claims 2-7, 9, and 21, which are not argued separately. Claims 10 and 17 Claim 10 is narrower in scope relative to claim 1, and further requires the disputed limitations: (1) “in response to receiving a command for mapping one or more virtual machines to an input/output multiplexer, mapping the one or more virtual machines to an input/output multiplexer” and (2) “combining, via the input/output multiplexer, display data that are output from virtual machines mapped to the input/output multiplexer to generate combined display data; [and] displaying the combined display data from the plurality of virtual machines on a virtual machine console display.” Claim 17 recites similar limitations. In support of the obviousness rejection of claims 10 and 17, the Examiner finds the combination of Talagala and Hakura teaches all of the limitations of Appellant’s claimed “method for parallelizing execution of operations for a plurality of virtual machines,” including the disputed limitations. Final Act. 16-19 (citing Talagala ¶¶ 89, 171, 227; Hakura ¶¶ 32, 97, 99). We disagree with (1) the Examiner’s findings regarding the teachings of Talagala and Hakura as well as (2) the Examiner’s stated reason to combine the teachings of Talagala and Hakura for the same reasons discussed relative to Appellant’s claim 1. In particular, we agree with Appellant’s arguments that neither Talagala nor Hakura, alone or in combination, teaches or suggests any “mapping one or more virtual machines to an input/output multiplexer” or “combining, via the input/output Appeal 2020-006086 Application 14/751,194 13 multiplexer, display data that are output from virtual machines mapped to the input/output multiplexer to generate combined display data; [and] displaying the combined display data from the plurality of virtual machines on a virtual machine console display,” recited in claims 10 and 17. For these reasons, we do not sustain the Examiner’s obviousness rejection of claims 10 and 17 and of their respective dependent claims 11- 14, 16, 18, and 19, which are not argued separately. CONCLUSION4 On this record, Appellant persuades us the Examiner errs in rejecting claims 1-7, 9-14, 16-19, and 21 as obvious over the combined teachings of Talagala and Hakura. DECISION SUMMARY In Summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1-7, 9-14, 16-19, 21 103 Talagala, Hakura 1-7, 9-14, 16-19, 21 REVERSED 4 As noted above, the Examiner withdraws the obviousness rejection of claims 8 and 15 based on the combined teachings of Talagala, Hakura, and Kannan was withdrawn by the Examiner. See supra note 3. However, when prosecution resumes, the Examiner may consider whether Kannan teaches configurations of virtual machines (VMs) 112, 114, 116, via VM management center 130 using command requests having scripts to invoke execution of the scripts on one or more target VM(s), as shown in Kannan’s Figure 1.