Tommi M. Jokinen et al.Download PDFPatent Trials and Appeals BoardNov 1, 201914223252 - (D) (P.T.A.B. Nov. 1, 2019) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/223,252 03/24/2014 Tommi M. Jokinen DN30852NH 8638 53364 7590 11/01/2019 TERRILE, CANNATTI & CHAMBERS, LLP NXP 6501 William Cannon Drive West AUSTIN, TX 78735 EXAMINER MACASIANO, JOANNE GONZALES ART UNIT PAPER NUMBER 2194 NOTIFICATION DATE DELIVERY MODE 11/01/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ip.department.us@nxp.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte TOMMI M. JOKINEN, ZHENG XU, and KUN XU Appeal 2019-000587 Application 14/223,252 Technology Center 2100 ____________ Before JOHN A. EVANS, JOHN P. PINKERTON, and MICHAEL M. BARRY, Administrative Patent Judges. BARRY, Administrative Patent Judge. DECISION ON APPEAL Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1–15, which are all of the claims pending in this application. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies the real party in interest as NXP USA, Inc. Appeal Br. 1. Appeal 2019-000587 Application 14/223,252 2 STATEMENT OF THE CASE Introduction Appellant’s disclosure and claimed invention relate to low latency data delivery within a multi-core, data processing system. Spec. ¶¶ 1, 23. In the interest of performing tasks more quickly (reduced latency) with fewer resources (increased performance), data processing systems may have certain tasks performed by a resource other than a core processor, such as by a hardware accelerator, during which time the core can be used to perform other tasks. Id. ¶¶ 2, 3. When a task is to be performed by such a resource, input data may be read from the core’s memory. See id. ¶¶ 3, 22, 23. After the resource has completed the task, output data may be written back to the core’s memory—an event about which the core often needs to be notified. See id. ¶¶ 3, 23. Appellant identifies a need to improve existing core notification techniques—including those that provide a separate notification interface, side band signals for snooping by the core, or an additional status transaction—because “these techniques can add additional routing and area to the processing system.” Spec. ¶ 3. Thus, in a disclosed embodiment of Appellant’s invention, the core awaiting the output data may snoop its memory and determine that the job is complete based upon status information corresponding to a zero byte data-beat, i.e., a combination of a data byte of the output data and a corresponding write strobe set to inactive (e.g., low). Id. ¶¶ 20–21, 23. Such an embodiment yields a data processing system with reduced latency and increased performance because it “provid[es] . . . a near instantaneous notification of task completion” to the snooping core and “uses an existing capability of certain interconnect protocols (albeit in a new capacity) without Appeal 2019-000587 Application 14/223,252 3 adding additional area to indicate when an accelerator completes a task.” See id. ¶ 21. Claims 1, 6, and 11 are independent claims. Claim 1 is illustrative of the claims on appeal: 1. A method comprising: assigning a task to a processing core; identifying a job within the task to be performed via an accelerator; performing and completing the job via the accelerator; generating output data including associated status information via the accelerator, the status information including an associated inactive write strobe that indicates whether the task has completed, the associated inactive write strobe identifying the status information within the output data, a combination of the output data and the associated inactive write strobe corresponding to a zero-byte data beat; snooping the status information to determine when the job being performed by the accelerator is completed, the snooping comprising snooping the status information, the snooping determining when the job being performed by the accelerator is completed based upon the status information corresponding to the zero byte data-beat; and continuing executing the task using the output data associated with the status information. Appeal Br. 7 (Claims App’x). Rejections and References The Examiner rejected claims 1, 2, 6, 7, 11, and 12 under 35 U.S.C. § 103 as being unpatentable over MacInnis et al. (US 2003/0185306 A1; pub. Oct. 2, 2003) (“MacInnis”), Slocum et al. (US 6,816,262 B1; iss. Nov. 9. 2004) (“Slocum”), and Solomon (US 5,943,483; iss. Aug. 24, 1999). Final 2–15. Appeal 2019-000587 Application 14/223,252 4 The Examiner rejected claims 3, 8, and 13 under 35 U.S.C. § 103 as being unpatentable over MacInnis, Slocum, Solomon, and Kuo (US 6,085,272; iss. July 4, 2000). Id. at 15–18. The Examiner rejected claims 4, 5, 9, 10, 14, and 15 under 35 U.S.C. § 103 as being unpatentable over MacInnis, Slocum, Solomon, and Moran et al. (US 2008/0282007 A1; pub. Nov. 13, 2008) (“Moran”). Id. at 18–22. ANALYSIS Claims 1–3, 6–8, and 11–13 Appellant argues Examiner error in the § 103 rejections of claims 1–3, 6–8, and 11–13 based solely on independent claims 1, 6, and 11, which Appellant argues together. See Appeal Br. 3–5. We select claim 1 as representative for the § 103 rejections of claims 1–3, 6–8, and 11–13. 37 C.F.R. § 41.37(c)(1)(iv). In rejecting claim 1, the Examiner finds, among other things, that MacInnis in view of Slocum teaches “generating output data including associated status information via the accelerator, the status information including an associated inactive write strobe that indicates whether the task has completed, the associated inactive write strobe identifying the status information within the output data,” as recited. Final 3–5 (citing MacInnis ¶¶ 31, 80; Slocum 8:24–28, 9:36–37). Appellant contends the Examiner errs in this finding because Slocum does not disclose or suggest that its accumulate mode is performed using a hardware accelerator. Appeal Br. 3–4. The Examiner responds that “the [field programmable gate array] FPGA hardware carrying out accumulate operations as disclosed in Slocum is equivalent to the accelerator recited in Appeal 2019-000587 Application 14/223,252 5 the claim limitations, as well as the accelerators disclosed in the MacInnis reference.” Ans. 4, see also id. at 3–4 (citing, e.g., Slocum 7:40–44, 59–60, 8:10–13; MacInnis Fig. 5, ¶¶ 28, 31, 79). Appellant does not persuade us of reversible error. The cited references must be considered for the entirety of what they teach and suggest to one skilled in the art. See, e.g., In re Hedges, 783 F.2d 1038, 1039 (Fed. Cir. 1986) (citing In re Wesslau, 353 F.2d 238, 241 (CCPA 1965)). Further, each reference cited by the Examiner must be read, not in isolation, but for what it fairly teaches in combination with the prior art as a whole. See In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986). The relevant inquiry is “what the combined teachings of th[os]e references would have suggested to those of ordinary skill in the art.” In re Keller, 642 F.2d 413, 425 (CCPA 1981) (emphasis added). Here, MacInnis, as cited by the Examiner, teaches the recited hardware accelerator, including a status register that indicates whether the module has completed its assigned tasks. Final 3–4 (citing MacInnis ¶¶ 31, 75, 77, 80). We agree with the Examiner that ordinarily skilled artisans would have understood this disclosure teaches “generating output data including associated status information via the accelerator, the status information . . . indicat[ing] whether the task has completed” as recited. Because the Examiner has shown that MacInnis teaches the recited “accelerator,” we do not need to analyze whether Slocum also teaches the same element. Appellant further contends that Slocum does not disclose or suggest “the status information including an associated inactive write strobe that indicates whether the task has completed . . . [and] identif[ies] the status Appeal 2019-000587 Application 14/223,252 6 information within the output data,” as recited. Appeal Br. 4. This argument is unpersuasive because it is conclusory—it does not substantively address a deficiency in the Examiner’s proposed combination and does not effectively explain how or why the Examiner erred. See 37 C.F.R. § 41.37(c)(1)(iv); In re Lovin, 652 F.3d 1349, 1357 (Fed. Cir. 2011) (explaining an appellant must advance substantive arguments beyond mere recitation of the claim elements and naked assertions that the corresponding elements were not found in the prior art). Moreover, the Examiner’s findings and explanations are reasonable. In particular, we agree with the Examiner that Slocum’s disclosure of a strobe going low, indicating that an accumulate mode of a field programmable gate array (FPGA) has completed its tasks, teaches “an associated inactive write strobe that indicates whether the task has completed.” Final Act. 4–5 (citing Slocum 8:24–28). As the Examiner explains, the strobe in Slocum (1) is “inactive” because it is set low; (2) is a “write” strobe because it is used by the microcontroller and FPGA during the write mode to signal write data on the bus; and (3) “indicates” that the task (i.e., accumulate operations) has been completed. See Ans. 4–5. We also agree with the Examiner that ordinarily skilled artisans would have understood that combining MacInnis’s hardware accelerator system (including its status register) with the low strobe functionality of Slocum teaches or at least suggests “status information including an associated inactive write strobe that indicates whether the task has completed . . . [and] identif[ies] the status information within the output data.” Id. As the Examiner explains, “it would have been obvious to one of common knowledge in the art that the associated status information disclosed by Appeal 2019-000587 Application 14/223,252 7 MacInnis, Paragraphs [0031] and [0080], would have been read when Strobe signal disclosed in Slocum ‘goes low’.” Ans. 5. Accordingly, we discern no error in the Examiner’s determination that combining the teachings of MacInnis and Slocum to arrive at the disputed limitation would have been obvious. See Final 5 (citing Slocum 9:36–37). Appellant also contends that MacInnis does not teach or suggest “snooping the status information to determine when the job being performed by the accelerator is completed,” as recited. Appeal Br. 4. Appellant’s contention is not persuasive because the Examiner relies on a combination of MacInnis, Slocum, and Solomon, not MacInnis alone, for teaching the disputed limitation. See Final 5–6 (citing Solomon 4:57–60); see also id. at 2–5 (laying out the respective teachings of MacInnis and Slocum); Ans. 5–6; Merck, 800 F.2d at 1097; Keller, 642 F.2d at 425. As the Examiner explains, it is Solomon’s disclosure of a process that “‘snoops’ the bus until the transfer of data is completed,” such that “the state of the bus upon completion indicates whether the data was successfully transferred” (Final Act. 5 (quoting Solomon 4:57–60)) that “show[s] . . . ‘snooping’ of status information would have been obvious.” Ans. 6. With respect to “the snooping determining when the job being performed by the accelerator is completed based upon the status information corresponding to the zero byte data-beat,” the Examiner cites Solomon’s snooping process as discussed above and explains that “the ‘zero-byte data beat’ limitation merely recites a descriptive grouping of data and further wherein such completion snooping would snoop the ‘inactive write strobe’ signal, as taught above by Slocum, which certainly corresponds to the recited grouping of data.” Final 5–6 (citing Solomon 4:57–60). Appeal 2019-000587 Application 14/223,252 8 Appellant disagrees, contending that “determining when the [job being performed by the] accelerator is completed based upon the status corresponding to the zero-byte data-beat should be provided patentable weight.” Appeal Br. 5. Accordingly, Appellant contends that none of the cited prior art references disclose or suggest “a combination of the output data and the associated inactive write strobe corresponding to a zero-byte data beat, much less . . . the snooping determining when the job being performed by the accelerator is completed based upon the status information corresponding to the zero byte data-beat.” Id. The Examiner responds by explaining that the recited phrase “zero– byte data beat” has been “reasonably interpreted . . . as . . . defining the logical combination of ‘output data’ and an ‘inactive write strobe’, as the term ‘zero-byte data beat’ did not appear to be a term of the art requiring any well-known meaning.” Ans. 6. Thus, “the Examiner maintains that since Slocum teaches that the completion of an ‘Accumulate Mode’ is signaled by a strobe going low, followed by the transmission of the data collected during the accumulate mode, then this makes obvious the portion of the [disputed] limitation regarding the ‘zero-byte data beat’, i.e. the combination of ‘output data’ and an ‘inactive write strobe’.” Id. The Examiner further explains that “since Solomon teaches that the state of the bus is snooped, i.e. monitored, to determine when the data has been successfully transferred, i.e. snooping the status of by detecting the ‘inactive write strobe’ as part of the ‘zero-byte data beat’ disclosed by Slocum . . . the combination of Slocum in view of Solomon” renders obvious the disputed limitation. Id. at 6–7. Appellant does not persuade us of reversible error. As an initial matter, we agree with the Examiner’s interpretation of “zero-byte data beat” Appeal 2019-000587 Application 14/223,252 9 as encompassing “the logical combination of ‘output data’ and an ‘inactive write strobe’,” which is consistent with a plain and ordinary reading of the claim language, in view of Appellant’s Specification. Ans. 6; see Spec. ¶¶ 20, 21 (providing that “the combination of [a byte of output data] and the data byte write strobe may be considered at [sic] data ‘beat’” and that “[t]he byte of status information 240” included in data information 212 of output data 200 and “identified by setting a corresponding data byte write strobe inactive (e.g., by setting the data byte strobe low) . . . may be considered a ‘zero-byte’ data beat.”). Applying this interpretation, Slocum’s strobe going low once the data collection during the accumulate mode has completed teaches a “zero-byte data beat,” as recited, because it is a logical combination of the data collected in accumulation mode (“output data”) and the strobe going low (“an associated inactive write strobe”). Accordingly, the combined teachings of MacInnis and Slocum would have taught or suggested to one of ordinary skill in the art that a job being performed by the accelerator may be determined as completed based upon status information corresponding to the data having been collected by the accelerator and the strobe having gone low, i.e., “the zero-byte data beat.” See, e.g., MacInnis ¶¶ 31, 80; Slocum 8:24–28. Therefore, we agree with the Examiner that applying Solomon’s known technique—snooping a bus to determine when data has been successfully transferred—to the combined teachings of MacInnis and Slocum would have suggested “the snooping determining when the job being performed by the accelerator is completed based upon the status information corresponding to the zero byte data-beat” as recited. We note Appellant proffers no rebuttal to the foregoing findings and explanations by the Examiner. Appeal 2019-000587 Application 14/223,252 10 Furthermore, to the extent Appellant’s contentions assert that the cited prior art teachings are not properly combinable, Appellant has not presented any persuasive evidence that the proposed combination would have been unpredictable, “uniquely challenging or difficult for one of ordinary skill in the art,” or would have “represented an unobvious step over the prior art.” Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418–19 (2007)); KSR, 550 U.S. at 416 (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”). For the foregoing reasons, we sustain the Examiner’s § 103 rejections of claims 1–3, 6–8, and 11–13. In doing so, as consistent with the foregoing, we adopt the findings and reasoning for the rejection of claim 1 as set forth by the Examiner in the Final Rejection and in the Answer. Claims 4, 9, and 14 With respect to claims 4,2 9, and 14, Appellant submits that “snooping when a job being performed by an accelerator is completed based upon the status corresponding to the zero byte data-beat in the context of an accelerator which is included within an interconnect which comprises an Advanced Microcontroller Bus Architecture (AMBA) interconnect should be provided patentable weight.” Appeal Br. 5. Accordingly, Appellant contends none of the cited prior art discloses or suggests 2 Appellant states that its contention applies to claim 3, but the disputed limitation is recited in claim 4, not claim 3. Therefore, we treat this contention as applying to claim 4, not claim 3. Appeal 2019-000587 Application 14/223,252 11 a combination of an accelerator which includes an interconnect which comprises an AMBA interconnect where the output data and the associated inactive write strobe correspond to a zero-byte data beat, the snooping determining when the job being performed by the accelerator is completed based upon the status information corresponding to the zero byte data-beat. Id. This contention is unpersuasive because it does not substantively address a deficiency in the Examiner’s proposed combination and does not effectively explain how or why the Examiner erred. See 37 C.F.R. § 41.37(c)(1)(iv); Lovin, 652 F.3d at 1357; accord Ans. 7. To the extent Appellant is reiterating arguments advanced for independent claims 1, 6, or 11, these arguments are unpersuasive for the reasons discussed above. Moreover, the Examiner’s findings and explanations that Moran teaches or suggests “the interconnect circuit comprises an [AMBA] interconnect” are reasonable. Final Act. 18–19 (citing Moran ¶ 16); Ans. 7–8. As the Examiner explains, “the claim language regarding the ‘AMBA interconnect’ has been given patentable weight and . . . Moran . . . show[s] . . . it was well-known in the art to utilize an AMBA interconnect since such interconnect technology is well-known in the art to advantageously support high performance and low power on-chip communication.” Ans. 7–8. Appellant offers no rebuttal to this explanation. For the foregoing reasons, we sustain the Examiner’s § 103 rejections of claims 4, 9, and 14. Appeal 2019-000587 Application 14/223,252 12 Claims 5, 10, and 15 With respect to claims 5, 10, and 15,3 Appellant submits that “snooping when a job being performed by an accelerator is completed based upon the status corresponding to the zero byte data-beat in the context of an accelerator which is included within an interconnect where the Advanced Microcontroller Bus Architecture (AMBA) interconnect comprises an Advanced eXtensible Interface (AXI) interconnect should be provided patentable weight.” Appeal Br. 6. Accordingly, Appellant contends none of the cited prior art discloses or suggests a combination of an accelerator which includes an interconnect which comprises an AMBA interconnect which comprises an AXI interconnect where the output data and the associated inactive write strobe correspond to a zero-byte data beat, the snooping determining when the job being performed by the accelerator is completed based upon the status information corresponding to the zero byte data-beat. Id. This contention is unpersuasive because it does not substantively address a deficiency in the Examiner’s proposed combination and does not effectively explain how or why the Examiner erred. See 37 C.F.R. § 41.37(c)(1)(iv); Lovin, 652 F.3d at 1357; accord Ans. 8. To the extent Appellant is reiterating arguments advanced for independent claims 1, 6, or 11, these arguments are unpersuasive for the reasons discussed above. Moreover, the Examiner’s findings and explanations that Moran teaches or suggests “the [AMBA] interconnect 3 Appellant states that its contention applies to claim 14, but the disputed limitation is recited in claim 15, not claim 14. Therefore, we treat this contention as applying to claim 15, not claim 14. Appeal 2019-000587 Application 14/223,252 13 further comprises an [AXI] interconnect” are reasonable. Final Act. 19 (citing Moran ¶ 16); Ans. 8–9. As the Examiner explains, “the claim language regarding the ‘AMBA interconnect’ and ‘AXI interconnect’ have been given patentable weight and . . . Moran . . . show[s] . . . it was well- known in the art to utilize [such] an AMBA interconnect since such interconnect technology is well-known in the art to advantageously support high performance and low power on-chip communication.” Ans. 8–9. For the foregoing reasons, we sustain the Examiner’s § 103 rejections of claims 5, 10, and 15. CONCLUSION We affirm the Examiner’s rejection of claims 1–15 under 35 U.S.C. § 103. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37 C.F.R. § 41.50(f). Appeal 2019-000587 Application 14/223,252 14 In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1, 2, 6, 7, 11, 12 103 MacInnis, Slocum, Solomon 1, 2, 6, 7, 11, 12 3, 8, 13 103 MacInnis, Slocum, Solomon, Kuo 3, 8, 13 4, 5, 9, 10, 14, 15 103 MacInnis, Slocum, Solomon, Moran 4, 5, 9, 10, 14, 15 Overall Outcome 1–15 AFFIRMED Copy with citationCopy as parenthetical citation