Texas Instruments Incorporated

Patent Trials and Appeals Board

May 4, 2021

2020003513 (P.T.A.B. May. 4, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/784,066 10/13/2017 Casey Thomas Morrison TI-78589 1081
23494 7590 05/04/2021
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, MS 3999
DALLAS, TX 75265
EXAMINER
TYNES JR., LAWRENCE C
ART UNIT PAPER NUMBER
2816
NOTIFICATION DATE DELIVERY MODE
05/04/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CASEY THOMAS MORRISON and LEE MARTIN SLEDJESKI

Appeal 2020-003513
Application 15/784,066
Technology Center 2800
Before MICHAEL P. COLAIANNI, MONTÉ T. SQUIRE, and
BRIAN D. RANGE, Administrative Patent Judges.
RANGE, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–4, 6–10, 12, 21, and 22. We have
jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies the real party in interest as Texas Instruments Incorporated.
Appeal Br. 3.
Appeal 2020-003513
Application 15/784,066

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CLAIMED SUBJECT MATTER2
Appellant describes the invention as relating to semiconductor devices
in ball grid array (BGA) packages. Spec. ¶ 2. The Specification explains the
need for an improved semiconductor package that allows increased channel
density (i.e., more communication signals routed away from the BGA device
in less area). Id. ¶ 3. In particular, Appellant explains that if terminals are
arranged in a linear fashion parallel to a substrate’s edge, the length of the
semiconductor passage increases as terminals are added. Id. ¶¶ 36–40; Figs.
6–7. If the terminals are arranged in a pattern where terminals are arranged
at an angle to the substrate’s edge such as in a zig zag or herringbone
pattern, density per unit length of signal channels may be increased. Id.
¶¶ 41–48; Figs. 8–9. Figure 8 illustrates such a pattern, and we reproduce
Figure 8 below.

2 In this Decision, we refer to the Final Office Action dated March 4, 2019
(“Final Act.”), the Appeal Brief filed August 7, 2019 (“Appeal Br.”), the
Examiner’s Advisory Action dated May 24, 2019 (“Advisory Action”), the
Examiner’s Answer dated February 6, 2020 (“Ans.”), and the Reply Brief
filed April 6, 2020 (“Reply Br.”).
Appeal 2020-003513
Application 15/784,066

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Figure 8 is a plan view of a portion of terminals for a semiconductor
package. Spec. ¶ 12. Figure 8 illustrates how ground and signal terminals
may be arranged in a repeating pattern illustrated by first, second, and third
terminal groups 811, 813, and 815. Id. ¶¶ 41–42.
Claim 1 is the only independent claim on appeal and is illustrative:
1. An apparatus, comprising:
a substrate having a first surface configured to include at
least one integrated circuit, and having a second surface
opposite the first surface,
the second surface having a plurality of terminals,
the substrate having a a first, second, third, and fourth
sides forming a periphery of the substrate; and
at least a first set of the plurality of terminals disposed
adjacent the first side of the substrate and forming a periphery
of the plurality of terminals adjacent to the first side of the
substrate,
the first set of the plurality of terminals arranged in
a pattern, the pattern comprising
a first group of consecutive ones of the
terminals extending in a first direction at a first
angle to a longitudinal line parallel to the first side
and directed towards an interior of the substrate,
a second group of consecutive terminals
extending in a second direction at a second angle
with respect to the first direction and extending
towards the periphery of the substrate, and
a third group of consecutive ones of the of
the terminals extending from the second group and
extending in the first direction at a third angle to
the second direction and away from the periphery
of the substrate,
wherein the plurality of terminals is electrically
connected to the integrated circuit.
Appeal 2020-003513
Application 15/784,066

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Appeal Br. 10 (Claims App.) (formatting modified for readability).
REFERENCES
The Examiner relies upon the prior art below in rejecting the claims
on appeal:
Name Reference Date
Massingill US 5,420,460 May 30, 1995
Mehta et al. US 2005/0215085 A1 Sept. 29, 2005
Shimanuki US 2006/0145344 A1 July 6, 2006
Siddiquie et al. US 2012/0032684 A1 Feb. 9, 2012
Matsumoto et al. US 2016/0172016 A1 June 16, 2016

REJECTIONS
The Examiner maintains the following rejections on appeal:
A. Claims 1–4, 6, 7, 21, and 22 under 35 U.S.C. § 102(a)(1) as
anticipated by Shimanuki. Ans. 3.
B. Claims 8 and 9 under 35 U.S.C. § 103 as obvious over Shimanuki in
view of Massingill. Id. at 6.
C. Claim 10 under 35 U.S.C. § 103 as obvious over Shimanuki in view
of Massingill and Matsumoto with reference to Mehta. Id. at 7.
D. Claim 12 under 35 U.S.C. § 103 as obvious over Shimanuki in view
of Siddiquie. Id. at 8.

OPINION
To resolve the issues before us on appeal, we focus on the Examiner’s
findings and determinations that relate to the error Appellant identifies.
Because we decide this appeal based on a recitation recited by independent
claim 1, we focus our analysis on claim 1.
Appeal 2020-003513
Application 15/784,066

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The Examiner finds that Shimanuki discloses a plurality of terminals
that meet the recitations of claim 1. Advisory Action 2–3. In particular, the
Examiner finds that Shimanuki terminals can be selected to form groups in a
zigzag pattern. Id. The Examiner illustrates this position by annotating
Shimanuki Figure 30. Id. at 3; see also id. at 4 (annotating Shimanuki Figure
1). We reproduce the Examiner’s annotated version of Shimanuki Figure 30
below.

Shimanuki Figure 30 is a plan view showing an example of a semiconductor
pattern on the main surface side of a wiring substrate according to an
embodiment of Shimanuki. Shimanuki ¶ 52. The Examiner annotates Figure
30 by drawing a line that connects certain terminals among the top two rows
of Shimanuki terminals in a zigzag pattern. Advisory Action 3.
Appellant argues that the Examiner’s line added to Shimanuki’s
Figure 30 does not identify a pattern of terminals that corresponds with the
recitations of claim 1. Appeal Br. 6–8; Reply Br. 1–3. We agree. Claim 1
requires a “first set of the plurality of terminals . . . forming a periphery of
the plurality of terminals adjacent to the first side of the substrate.” Appeal
Br. 10 (Claims App.) (emphasis added). As Appellant and the Examiner
Appeal 2020-003513
Application 15/784,066

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argue, “periphery” in this context refers to external or outermost. Id. at 6–7;
Ans. 10.
The Examiner contends that the identified terminals of Figure 30 are
“in a periphery” because they are in “the area outside of device 1.” Ans. 10.
Claim 1, however, does not recite that the first set of the plurality of
terminals is located in a periphery. Instead, the first set must form “a
periphery of the plurality of terminals adjacent to the first side of the
substrate.” This same first set must be “arranged in a pattern” as claim 1
recites. Some of Shimanuki’s periphery of terminals are not part of the “first
set” (i.e., lines of the zigzag) the Examiner identifies. Thus, what the
Examiner identifies as claim 1’s “first set of the plurality of terminals” does
not form “a periphery of the plurality of terminals” as claim 1 requires.
Because the Examiner does not adequately establish that Shimanuki
teaches the terminal geometry that claim 1 recites, we do not sustain the
Examiner’s rejection of claim 1. Because the Examiner’s treatment of
dependent claims does not cure this error, we also do not sustain rejection of
those claims.
DECISION SUMMARY
In summary:
Claim(s)
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–4, 6, 7,
21, 22
102(a)(1) Shimanuki 1–4, 6, 7,
21, 22
8, 9 103 Shimanuki, Massingill 8, 9
10 103 Shimanuki, Massingill,
Matsumoto, Mehta
10
12 103 Shimanuki, Siddiquie 12
Overall
Outcome
1–4, 6–10,
12, 21, 22
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Application 15/784,066

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REVERSED