Taiwan Semiconductor Manufacturing Company, Ltd.

Patent Trials and Appeals Board

Oct 26, 2020

2019005580 (P.T.A.B. Oct. 26, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/162,115 05/23/2016 Ji-Soo Park TSMP2100387US03 9705
43859 7590 10/26/2020
SLATER MATSIL, LLP/TSMC
17950 PRESTON ROAD, SUITE 1000
DALLAS, TX 75252
EXAMINER
TRAN, TONY
ART UNIT PAPER NUMBER
2894
NOTIFICATION DATE DELIVERY MODE
10/26/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@slatermatsil.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________
Ex parte JI-SOO PARK
____________
Appeal 2019-005580
Application 15/162,115
Technology Center 2800
____________
Before JAMES C. HOUSEL, BRIAN D. RANGE, and
DEBRA L. DENNETT, Administrative Patent Judges.
DENNETT, Administrative Patent Judge.
DECISION ON APPEAL1
Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the
Examiner’s decision to reject claims 1–20 of Application 15/162,115, which
constitute all the claims pending in this application. We have jurisdiction
under 35 U.S.C. § 6(b).

1 In our Decision, we refer to the Specification (“Spec.”) of Application
No. 15/162,115 filed May 23, 2016; the Final Office Action dated Jan. 19,
2018 (“Final Act.”); the Advisory Action dated Apr. 6, 2018 (“Adv. Act.”);
the Appeal Brief filed Aug. 24, 2018 (“Appeal Br.”); the Examiner’s
Answer dated May 13, 2019 (“Ans.”); and the Reply Brief filed July 15,
2019 (“Reply Br.”).
2 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies the real party in interest as TAIWAN
SEMICONDUCTOR MANUFACTURING COMPANY, LTD. Appeal Br.
2.
Appeal 2019-005580
Application 15/162,115
2
For the reasons set forth below, we AFFIRM IN PART.
STATEMENT OF THE CASE
The ’115 Application relates to epitaxial growth of a crystalline
material. Spec. ¶ 2. The Inventor indicates that dislocation density of
epitaxially grown material can be unacceptably high for many applications.
Id. ¶ 4. According to the Inventor, Aspect Ratio Trapping (ART) is a defect
reduction technique that mitigates defects, causing defects to terminate at
non-crystalline, e.g., dielectric sidewalls. Id. ¶ 5. The Inventor states that
ART uses high aspect ratio openings such as trenches or holes to trap
dislocations, preventing defects from reaching the epitaxial film surface. Id.
Figure 7A, reproduced below from the ’115 Application, shows a cross
section of an epitaxially grown crystalline material using ART. Id.

In Figure 7A crystalline material 140 is epitaxially grown on substrate
100. Id. By confining the crystalline growth within an opening (e.g.,
trench) with a sufficiently high aspect ratio (e.g., 1 or greater), defects 150
formed while epitaxially growing the crystalline material 140 travel to and
end at the insulator sidewalls 130, and crystalline material 140 continues to
grow without the continued growth of defects 150. Id.
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The Inventor indicates that it is desirable to obtain a smooth crystal
surface within opening to avoid interface variances between layers that
affect the functionality of an interface from one device to another device on
the same substrate. Id. ¶ 7. Thus, according to the Inventor, there is a need
to reduce the surface roughness of crystalline materials grown in an ART
opening. Id. ¶ 10.
Claims 1, 12, and 19 reproduced below from the Claims Appendix of
the Appeal Brief illustrate the claimed subject matter:
1. A semiconductor structure comprising:
a trench having at least two sidewalls, an insulating layer
formed on said at least two sidewalls, the trench having a
bottom formed of a crystalline substrate; and
an epitaxial crystalline material within the trench, the
epitaxial crystalline material being lattice-mismatched with the
crystalline substrate, the epitaxial crystalline material having a
top surface, wherein the top surface of the epitaxial crystalline
material:
is below an uppermost surface of the insulating
layer;
has a root mean square surface roughness of 5 nm
or less;
is a distinct surface from sidewalls of the epitaxial
crystalline material; and
comprises at least two facets.
12. A structure comprising:
an insulator having an opening to a crystalline substrate,
the opening being defined by a pair of non-crystalline
sidewalls, the pair of non-crystalline sidewalls including a first
noncrystalline sidewall and a second non-crystalline sidewall;
and
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Application 15/162,115
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an epitaxial crystalline material within the opening of the
insulator, the epitaxial crystalline material being lattice-
mismatched with the crystalline substrate, the epitaxial
crystalline material having at least one top surface with a root
mean square surface roughness of 5 nm or less, the at least one
top surface of the epitaxial crystalline material extending from
the first non-crystalline sidewall to the second non-crystalline
sidewall, the at least one top surface being below an uppermost
surface of the insulator.
19. A structure comprising:
a confined area on a substrate, the confined area defined
by a pair of laterally opposed portions of oxide material
disposed over the substrate; and
a first epitaxial material on the confined area of the
substrate between the pair of laterally opposed portions of oxide
material, the first epitaxial material having a top surface with a
root mean square surface roughness of 5 nm or less, the top
surface extending from a first sidewall of one of the pair of
laterally opposed portions of oxide material to a second
sidewall of another of the pair of laterally opposed portions of
oxide material.
REFERENCES
The Examiner relies on the following references in rejecting the
claims:
Name Reference Date
Pan et al. (“Pan”) US 2007/0025670 A1 Feb. 1, 2007
Currie et al.
(“Currie ’465”)3
US 2007/0054465 A1 Mar. 8, 2007
Currie et al.
(“Currie ’467”)
US 2007/0054467 A1 Mar. 8, 2007
Kim et al. (“Kim”) US 2008/0163814 A1 July 10, 2008

3 Currie ’465 and Currie ’467 have the same filing date, publication
date, figures, and appear to have identical disclosures. Compare Currie ’465
Appeal 2019-005580
Application 15/162,115
5
REJECTIONS
The Examiner rejects claims under 35 U.S.C. § 1034 as follows: (1)
claims 19 and 20 over Pan in view of Kim; and (2) claims 1–18 over Pan in
view of Kim, and further in view of Currie. Final Act. 2–8.
DISCUSSION
Rejection of claims 19 and 20 over Pan in view of Kim5
Claim 19 is independent and claim 20 depends from it. Appeal Br.
20. The Examiner finds claims 19 and 20 obvious over Pan in view of Kim.
Final Act. 24. Appellant does not address the rejection of these claims in the
Appeal Brief. See generally Appeal Br.
We summarily sustain the rejection of claims 19 and 20 as obvious
over the combination of Pan and Kim.
Rejection of claims 1–18 over Pan in view of Kim and Currie6

with Currie ’467. The Examiner cites Currie ’465, paragraph 41, against
claims 1–5, 7–15, and 18, and Currie ’467, paragraph 27, against claims 6,
16, and 17. Compare Final Act. 4 with id. at 8. Appellant does not identify
which published application is cited. See, e.g., Appeal Br. 10. We cite to
“Currie” generically, as there is no difference between the applications in
terms of the figures and text cited.
4 Because this application was filed after the March 16, 2013, effective
date of the America Invents Act, we refer to the AIA version of the statute.
5 The Examiner did not enter Appellant’s proposed amendments to
claims 19 and 20. Adv. Act. 1.
6 In the Final Office Action, the Examiner rejects claims 1–5, 7–15, and
18 over Pan in view of Kim and further in view of Currie ’465. Final Act. 4.
The Examiner mentions Kerber in discussing the rejection of claim 11. Id.
at 7. The Examiner rejects claims 6, 16, and 17 over “Pan/Kerber as applied
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Application 15/162,115
6
We review the appealed rejections for error based upon the issues
identified by Appellant and in light of the arguments and evidence produced
thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential),
(cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011))
(“[I]t has long been the Board’s practice to require an applicant to identify
the alleged error in the [E]xaminer’s rejections.”). After considering the
evidence presented in this Appeal and each of Appellant’s arguments, we are
persuaded that Appellant identifies reversible error in the Examiner’s
rejection of claims 1–18.
Appellant argues claims 1–4, 6–8, 12, and 14–18 as a group. Appeal
Br. 7–12. We select claim 1 as representative of the group. 37 C.F.R.
§ 42.37(c)(1)(iv). To the extent necessary, we address claims 5, 9–11, and
13 separately below.
Claims 1 and 12 are independent and contain similar limitations. See
Appeal Br. 18, 19. The limitations that are at issue first in this appeal
regarding this group of claims are (1) claim 1’s recitation “the top surface of
the epitaxial crystalline material: is below an uppermost surface of the
insulating layer; has a root mean square surface roughness of 5 nm or less”;
and (2) claim 12’s recitation “the epitaxial crystalline material having at

to claim 1 and 12 above, and further in view of Currie.” Id. at 8. Kerber is
not otherwise identified in the Final Office Action. See generally id.
In the Remarks accompanying Appellant’s Nov. 21, 2017 Amendment
After Final, Appellant states that the Examiner acknowledged in an Oct. 23,
2017 interview that references to “Kerber” appearing in the Aug. 21, 2017
Non-Final Office Action were typographical errors and should be replaced
with “Kim.”
The prosecution history is consistent with the Examiner intending to
replace “Kerber” with “Kim.”
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Application 15/162,115
7
least one top surface with a root mean square surface roughness of 5 nm or
less . . . the at least one top surface [of the epitaxial crystalline material]
being below an uppermost surface of the insulator.” Id. at 7.
With regard to claim 1, the Examiner finds that Pan teaches a
semiconductor structure comprising a trench having at least two sidewalls,
an insulating layer formed on said at least two sidewalls, the trench having a
bottom formed of a crystalline substrate, and an epitaxial crystalline material
within the trench, the epitaxial crystalline material being lattice-mismatched
with the crystalline substrate, the epitaxial crystalline material having a top
surface which is a distinct surface from sidewalls of the epitaxial crystalline
material, and comprises at least two facets. Final Act. 4 (citing Pan FIGS.
4A-4B, ¶¶ 20–21).
The Examiner acknowledges that Pan does not teach the epitaxial
crystalline material has a top surface with a root mean square surface
roughness of 5 nm or less, but relies on Kim for this teaching. Id. at 5
(citing Kim ¶ 80). The Examiner determines that it would have been
obvious for one of ordinary skill in the art as of the effective filing date of
the invention to combine the teachings of Pan and Kim for the purpose of
reducing defects, as taught by Kim. Id.
The Examiner finds that the combination of Pan and Kim fails to
teach the top surface of the epitaxial crystalline material is below an
uppermost surface of the insulating later. Id. The Examiner finds that
Currie ’465 teaches this limitation. Id. (citing Currie ’465 FIG. 5B, ¶ 41).
The Examiner determines that it would have been obvious to one of ordinary
skill in the art to incorporate this teaching into Pan’s modified
semiconductor device for the purpose of enhanced mobility, as taught by
Currie. Id.
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Appellant argues that none of the cited references teaches or suggests
a structure that can achieve the claimed roughness for a top surface of an
epitaxial crystalline material below an uppermost surface of the insulating
layer or insulator. Appeal Br. 7. More specifically, Appellant argues that
the Examiner’s rejection requires taking the surface roughness of the top
surface of Kim’s layer 112 that is achieved only above the top surface of
Kim’s dielectric mask 106, and applying it to the top surfaces of layers 540A
and 540B of Currie, which are below the top surface of Currie’s insulator
layer 510. Id. at 7–8. Appellant illustrates the point with an annotated
figure combining Kim’s Fig. 1(f) and Currie’s Fig. 5A, reproduced below.
Id. at 8.

The portion of Kim’s Fig. 1 included in Appellant’s combined
illustration shows a schematic of final SLEO (sidewall lateral epitaxial
overgrowth) regrowth with window regions 108 and sidewalls 110 made by
etching. Kim ¶¶ 53, 71. Layer 112, which is typically non-polar m-plane
GaN material, is grown in window regions 108 and on sidewalls 110. Id.
¶ 72. As layer 112 starts to grow above the top surface 114 of dielectric
mask 106, layer 112 starts growing laterally along top surface 114 until one
Appeal 2019-005580
Application 15/162,115
9
lateral growth 116 meets up with another lateral growth 118 as a given
intersection 120. Id. At that point, layer 112 starts growing vertically. Id.
Currie’s Fig. 5A as included in Appellant’s combined figure depicts a
schematic cross-sectional side view illustrating formation of semiconductor
structures. Currie ¶ 24. Fig. 5A shows “epitaxially deposited active area
material(s) only partially fill openings 520A and 520B defined in an
insulator layer 510 and extending to the substrate 500. Thus, top surfaces of
active-area regions 540A and 540B do not reach to the top surface 560 of the
insulator layer.” Id. ¶ 41.
According to Appellant, one of ordinary skill in the art would not
have had a reasonable expectation of success in combining the three
references, and the combination fails to provide an enabling disclosure to
achieve the challenged features of claim 1. Appeal Br. 8. Appellant argues
that the top surface of layer 112 in Kim’s Fig. 1(f) is not below an
uppermost surface of an insulating layer. Id. at 9. Appellant quotes Kim as
teaching “[a]s layer 112 starts to grow above the top surface 114 of
dielectric mask 106, layer 112 starts growing laterally along top surface 114,
until one lateral growth 116 meets up with another lateral grown 118 at a
given intersection 120.” Id. (quoting Kim ¶ 72). Appellant argues that “it is
only the coalescing of lateral growth fronts 116 and 118 at intersections 120
. . . over a top surface of dielectric mask 106 to achieve the asserted surface
roughness at ‘the top of layer 112 . . . .’” Id. Appellant argues that Kim
discloses the surface roughness is a result of growing layer 112 above the
uppermost surface of the insulating layer. Id. at 10.
Appellant contends that Currie provides no teaching regarding
roughness of the top surfaces of the layers 540A and 540B. Id. Appellant
argues that Currie’s disclosure of achieving low root mean square surface
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roughness values for wafer bonding surfaces in other embodiments does not
apply to layers 540A and 540B because they are not wafer bonding surfaces.
Id. at 10–11.
Appellant also contends that the rejection of claim 1 is based on
impermissible hindsight, as none of the cited references teaches or suggests
a structure with a top surface of an epitaxial crystalline material having the
claimed roughness and being below an uppermost surface of the insulating
layer or insulator. Id. at 11.
In response to Appellant’s arguments, the Examiner finds that Pan,
Kim, and Currie teach the same inventive concept wherein the epitaxial
crystalline material grows in the trench formed in the insulating layer. Ans.
4 (“Since, all three Pan, Kim and Currie teach the same inventive concept
wherein the epitaxial crystalline material grow in the trench form between
the insulating layer 18 and 2 of Pan, FIGS. 4B and 2C; SiO2 masking
materials 106 of Kim, FIG. 1 (d); and 510 of Currie, FIG. 5A.”). The
Examiner also cites Currie as teaching “a root mean square surface
roughness of the surface 280 does not exceed about 1 nm,” and finds that
Currie can achieve the claimed roughness for a top surface of an epitaxial
crystalline material below the upper surface, making it reasonable to
combine the three references to yield a predictable result. Id. (citing Currie
¶ 34).
Appellant persuades us of reversible error in the Examiner’s rejection
of claim 1. We agree with Appellant’s position that the combined references
do not teach a structure with the claimed roughness for a top surface of an
epitaxial crystalline material below an uppermost surface of the insulating
layer. See Appeal Br. 7.
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Kim teaches defect reduction of non-polar m-plane with sidewall
lateral epitaxial overgrowth. Kim ¶ 39. The purpose of Kim is to minimize
defect densities in nitride materials by employing lateral overgrowth from
sidewalls of etched nitride material through a dielectric mask. Id. ¶ 47. As
Kim describes:
The method includes depositing a patterned mask on non-polar
or semi-polar III-Nitride template, etching the template material
down to various depths through openings in the mask, and
regrowing the non-polar or semi-polar epitaxial film by
coalescing laterally from the tops of the sidewalls before the
vertically growing material from the trench bottoms reaches the
surface. The coalesced features grow through the openings of the
mask, and grow laterally over the dielectric mask until a fully
coalesced continuous film is achieved.
Id. (emphasis added). Therefore, achieving the root mean square surface
roughness of the upper surface (the top of layer 112 in step (f) of FIG. 1) that
the Examiner relies on requires lateral overgrowth of the epitaxial layer over
the dielectric mask. Kim does not teach that the root mean square roughness
of 5 nm or less can be achieved “wherein the top surface of the epitaxial
crystalline material is below an uppermost surface of the insulating layer,”
as required by claim 1.
Currie teaches achieving low root mean square surface roughness
values for wafer bonding surfaces by performing chemical mechanical
polishing. Currie ¶ 32. Currie discloses the difficulty of stopping selective
epitaxy precisely at the point that the openings are filled with active-area
materials, and explains that portions extending above the top surface of the
insulator layer may be removed by planarization so that the surface of the
active-area regions is substantially coplanar with the top surface of the
insulator layer. Id. ¶ 30. Currie discloses an implementation of
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embodiments in which epitaxially deposited active area material(s) only
partially fill the openings defined in the insulator, and the top surfaces of
active-area regions 540A and 540B do not reach to the top surface of the
insulator layer. Id. ¶ 41. However, Currie’s disclosure of achieving low
root mean square surface roughness values for wafer bonding surfaces by
performing chemical mechanical polishing does not apply to the surfaces of
these partially filled openings. See id. ¶¶ 32, 41. Curries teaches that the
partially filled openings can be left empty or filled with a dielectric material
forming buffer regions over the active-area regions. Id. ¶ 41. If the
dielectric material is deposited over the entire surface of the active-area
regions and top surface of the insulator layer, the structure may then be
planarized such that any dielectric material formed over top surface of the
insulator layer is removed, and the dielectric material remains only over
active-area regions. Id. Under such circumstances (where the windows or
trenches shown in FIG. 5A are filled to the top with dielectric), the surface
may be planarized. Id. Thus, Currie indicates that the windows or trenches
must be filled to the top in order to achieve a smooth, planarized surface.
Whether or not a person of ordinary skill in the art would have had a
reasonable expectation that a particular combination of references would
work is a pure question of fact. Alza Corp. v. Mylan Labs., Inc., 464 F.3d
1286, 1289 (Fed. Cir. 2006). A reasonable expectation of success must be
founded in the prior art to show obviousness. In re Vaeck, 947 F.2d 488,
493 (Fed. Cir. 1991). Given the teachings of Kim and Currie discussed
above, we determine that the Examiner has not adequately established that
one of ordinary skill in the art as of the effective filing date of the invention
would have had a reasonable expectation of success in achieving the
structure claimed in claim 1.
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We do not sustain the rejection of claim 1 as obvious over Pan in view
of Kim and Currie. Because claims 2–18 include the same limitation found
lacking in the cited art, we also do not sustain the rejection of these claims as
obvious over the same references.
DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1–5, 7–15,
18 103
Pan, Kim, Currie 1–5, 7–15, 18
6, 16, 17 103 Pan, Kim, Currie 6, 16, 17
19, 20 103 Pan, Kim 19, 20
Overall
Outcome
19, 20 1–18
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED IN PART