Subbayya Chowdary. Yanamadala et al.

Patent Trials and Appeals Board

Oct 17, 2019

13280205 - (D) (P.T.A.B. Oct. 17, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/280,205 10/24/2011 Subbayya Chowdary Yanamadala 20057-1613 3443
69569 7590 10/17/2019
NORTH WEBER & BAUGH LLP
3260 Hillview Avenue, 1st Floor
PALO ALTO, CA 94304
EXAMINER
POPHAM, JEFFREY D
ART UNIT PAPER NUMBER
2432
NOTIFICATION DATE DELIVERY MODE
10/17/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docket1@northweber.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SUBBAYYA CHOWDARY YANAMADALA and
ANISH DHANEKULA
Appeal 2018-009151
Application 13/280,205
Technology Center 2400
Before ROBERT E. NAPPI, NORMAN H. BEAMER, and
MICHAEL T. CYGAN, Administrative Patent Judges.

CYGAN, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1, 3–5, 9, 11–13, 23–37, and 31. We
have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies the real party in interest as Maxim
Integrated Products. Appeal Br. 3.
Appeal 2018-009151
Application 13/280,205

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CLAIMED SUBJECT MATTER
The claims are directed to a detection of tampering in a secure
application specific integrated circuit (ASIC). Appeal Br. 6. Claims 1 and 9
are illustrative, with the portions disputed upon appeal emphasized by
italicization:
1. A method of detecting a tampering attempt in a secure
application specific integrated circuit (ASIC), comprising steps
of:
generating a plurality of random numbers that varies with
time;
using a mesh driver that determines a driving pattern and
a mesh configuration to drive an active mesh according to the
plurality of random numbers, the active mesh comprising
sensing nodes;
monitoring sensing nodes with respect to the plurality of
random numbers by comparing outputs at the sensing nodes
with the random numbers to detect an inconsistency, the
sensing nodes being coupled to one or more analog switches;
and
generating a flag signal that indicates the tampering
attempt, wherein the active mesh is made from at least one
metal layer above a substrate of the secure ASIC and is routed
to the substrate via intermediate metal and polysilicon layers.
9. A tamper detection system that protects a sensitive
area in a secure application specific integrated circuit (ASIC),
comprising:
an active mesh that comprises a plurality of conductive
metal wires, the active mesh covering the sensitive area;
a random number generator (RNG) that generates at least
one random number, the at least one random number
comprising a plurality of bits and varying with time;
a mesh driver, coupled between the active mesh and the
RNG, the mesh driver determines a driving pattern and a mesh
configuration to drive the active mesh with a time-varying
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driving pattern according to the at least one random number, a
first end node of each conductive metal wire in the plurality of
conductive metal wires being driven at a logic level determined
by a bit in the plurality of bits and being routed to a doped
ASIC substrate via routing paths formed by layers of metal and
polysilicon; and
a tamper sensing unit, coupled to both the active mesh
and the RNG, the tamper sensing unit monitoring a voltage at a
second end node of at least one conductive metal wire selected
from the plurality of metal wires that are coupled to one or
more analog switches, verifying the voltage with respect to a
corresponding bit in the plurality of bits, and generating a flag
signal.
Dependent claims 3–5, 11–13, 23–27, and 31 each incorporate the
limitations of their respective independent claims. Claims 2, 6, 10, and 14–
22 have been cancelled, and claims 7, 8, and 28–30 have been withdrawn
from consideration, and are not under appeal. Appeal Br. 5.
REJECTIONS
Claims 1, 3–5, 9, 11–13, 23–27, and 31 are rejected under 35 U.S.C.
§112(a) as lacking written description. The Examiner has determined that
claim 1 lacks written description because the limitation “the sensing nodes
being coupled to one or more analog switches” is not supported by the
Specification as originally filed. Final Act. 9. The Examiner has further
determined that claim 9 lacks written description because the limitation “and
being routed to a doped ASIC substrate via routing paths formed by layers of
metal and polysilicon” is not supported by the Specification as originally
filed. Id. Both limitations were not present in the originally filed claims,
and were added during prosecution through amendment of the claims. Spec.
19–21. Appellant contends that both limitations were supported by the
originally filed Specification. Appeal Br. 10–16.
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A. “the sensing nodes being coupled to one or more analog switches”
The Examiner has determined that this limitation is not supported by
the Specification because the originally-filed Specification describes the
sensing node as including one or more analog switches, but not coupled to
one or more analog switches. Final Act. 9. The Examiner has further
determined that this language does not appear, ipsis verbis, in the
Specification. Ans. 14–16. The Examiner has further determined that the
claim requires the sensing nodes and switches to be directly coupled. Id. at
17. The Examiner has further determined that the claim requires the nodes
to perform sensing and not that the node itself be sensed. Id.
Appellant first argues that support for this limitation is found through
the description of “wire[s] being sensed;’ ‘driving a . . . node of each
conductive metal wire;’ and ‘a plurality of analog switches that are
controlled to couple the plurality of conductive metal wires to the RNG, the
mesh driver and the tamper sensing unit.’” Appeal Br. 13 (citing Spec. ¶ 46,
claims 4, 14). We are persuaded by this argument. The cited portion of the
Specification describes that sensing of tampering occurs when one particular
sensing node is shorted to a nearby conducted wire; i.e., the nodes sense
tampering. Spec. ¶ 46. The Specification further describes that the sensing
nodes are selected for monitoring by the tamper sensing unit. Id. Originally
filed claim 14 further describes the tamper sensing system comprising a
plurality of analog switches that are controlled to couple the plurality of the
conductive metal wires to the RNG [random number generator], the mesh
driver, and the tamper sensing unit. The Examiner has not explained why
one having ordinary skill in the art would not understand the originally-filed
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Specification to describe the sensing nodes on the conductive metal wires as
coupled to the analog switches.
We further agree with Appellant argument that under 35 U.S.C.
§112(a), claim language need not be reproduced ipsis verbis in the
Specification. Id.; Reply Br. 8. Our reviewing court has clearly stated that
§112(a) does not require the exact wording of a claim to be found in the
originally-filed Specification. See, e.g., Vas-Cath, Inc. v. Mahurkar, 935
F.2d 1555, 1563 (Fed. Cir. 1991); Martin v. Johnson, 454 F.2d 746, 751
(CCPA 1972).
Appellant next argues that the claims make no distinction between
“indirect coupling” and “direct coupling,” and that the Specification
supports analog switches being coupled to metal wires, and supports metal
wires having nodes being sensed. Appeal Br. 13; Reply Br. 9. As to this
argument, we agree. Claim 1 simply recites “being coupled.” The Examiner
has not explained why the two electronic components “being coupled” in
claim 1 would not include being coupled via an electrically conductive wire.
Consequently, we are persuaded by Appellant that the Specification, as a
whole, describes “sensing nodes being coupled to one or more analog
switches,” as set forth in claim 1.
Accordingly, we are persuaded of error in the Examiner’s rejection of
claim 1. Since the rejection of claims 3–5 and 23–26 is predicated on the
same rationale, we reverse the Examiner’s rejection of claims 1, 3–5, and
23–26.
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B. “and being routed to a doped ASIC substrate via routing paths
formed by layers of metal and polysilicon”
The Examiner has determined that this limitation is not supported by
the Specification because the originally-filed Specification does not describe
a doped ASIC substrate or the routing of anything thereto via such routing
paths. Final Act. 9. The Examiner has further determined that the
Specification as originally filed does not describe that an end node is routed
to a doped ASIC substrate. Ans. 22–25.
Appellant argues that Figure 1B of the originally-filed Specification
shows a “p-substrate (ASIC [Application Specific Integrated Circuit]
substrate),” having substrate zones denoted as “p+” and “n+” that would be
understood in the art as describing routing paths in a doped ASIC substrate.
Appeal Br. 14. The Examiner does not appear to contest this interpretation
of Figure 1B. To the extent that the Examiner points to Appellant’s
statements that particular prior art references do not contain a doped ASIC
(Ans. 18–20), we do not agree that this undermines the Appellant’s
contention that Figure 1B shows a doped ASIC. To the extent that the
Examiner finds the Specification to lack the word “doped,” such an ipsis
verbis test is not determinative where the Specification “describe[s] an
invention understandable to th[e] skilled artisan and show[s] that the
inventor actually invented the invention claimed.” Ariad Pharms., Inc. v. Eli
Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (en banc). We are
therefore persuaded by Appellant that the originally-filed Specification
describes a doped ASIC substrate.
Appellant further argues that the end node is routed to the ASIC
substrate because the end node, which is the sensing node of the conductive
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metal wire, is coupled to the analog switches that are located in an ASIC
substrate. Reply Br. 12 (citing the Specification and current claim 25).
With respect to the reliance on current claim 25, that claim was added during
prosecution, and therefore does not demonstrate possession upon filing, as
required by 35 U.S.C. § 112(a). However, the Specification as originally
filed states that “[c]onductive wires and the capacitors in the active mesh
502 are coupled to the underlying integrated circuit via analog switches that
are also included in the ASIC substrate.” Spec. ¶ 50. Further, the
Specification describes the coupling of the active mesh to the integrated
circuit by “routing paths formed using the intermediate metal and
polysilicon layers.” Id. ¶ 49. We are therefore persuaded that Appellant’s
Specification demonstrates possession of a doped ASIC substrate that is
coupled to the sensing nodes in the active mesh by routing paths formed by
layers of metal and polysilicon.
The Examiner states that Appellant has not described what is being
routed in claim 9. Ans. 22. However, we determine that (1) the
Specification describes the time-varying driving pattern as being coupled via
the analog switch (Spec. ¶ 49), (2) the claim is in the form of an apparatus
rather than a method, and therefore its scope is determined by what it is
rather than what it does (Hewlett-Packard Co. v. Bausch & Lomb, Inc., 909
F.2d 1464, 1468 (Fed. Cir. 1990) (“[A]pparatus claims cover what a device
is, not what a device does”)), and (3) the rejection is styled as a lack of
written description, not that the claims fail to “particularly point[] out and
distinctly claim[] the subject matter,” which is a requirement of 35 U.S.C.
§112(b), not § 112(a).
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DECISION
For the above-described reasons, we reverse the Examiner’s rejection
of claims 1, 3–5, 9, 11–13, 23–27, and 31 as lacking written description
under 35 U.S.C. §112(a).
CONCLUSION
In summary:
Claims
Rejected
35 U.S.C. § Basis Affirmed Reversed
1, 3–5, 9,
11–13, 23–
27, 31
112(a) Written
Description
1, 3–5, 9,
11–13, 23–
27, 31

REVERSED