SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Patent Trials and Appeals BoardMay 14, 2021

2020001231 (P.T.A.B. May. 14, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/591,047 01/07/2015 Keisuke Miyagawa 12732-0259002 8824 26171 7590 05/14/2021 FISH & RICHARDSON P.C. (DC) P.O. BOX 1022 MINNEAPOLIS, MN 55440-1022 EXAMINER MANDEVILLE, JASON M ART UNIT PAPER NUMBER 2622 NOTIFICATION DATE DELIVERY MODE 05/14/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): PATDOCTC@fr.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte KEISUKE MIYAGAWA Appeal 2020-001231 Application 14/591,047 Technology Center 2600 Before JEREMY J. CURCURI, ADAM J. PYONIN, and PHILLIP A. BENNETT, Administrative Patent Judges. BENNETT, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 2, 3, 5–7, 9–12, and 14, which are all of the pending claims. Claims 1, 3, 8, and 13 are cancelled. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Semiconductor Energy Laboratory Co., Ltd. Appeal Br. 1. Appeal 2020-001231 Application 14/591,047 2 CLAIMED SUBJECT MATTER The claims are directed to a light emitting device. Claim 2, reproduced below with key limitations in italics, is illustrative of the claimed subject matter: 2. A light emitting device comprising: a shift register; an inverter; a scan line; a first signal line; a second signal line; a power supply line; a first transistor; a second transistor; a third transistor; a fourth transistor; a first capacitor; a second capacitor; a first light emitting element; and a second light emitting element, wherein a gate of the first transistor is connected to the scan line, wherein one of a source and a drain of the first transistor is connected to the first signal line, wherein the other of the source and the drain of the first transistor is directly connected to a gate of the second transistor, wherein one of a source and a drain of the second transistor is connected to the first light emitting element, wherein the other of the source and the drain of the second transistor is directly connected to the power supply line, Appeal 2020-001231 Application 14/591,047 3 wherein a first electrode of the first capacitor is connected to the gate of the second transistor, wherein a second electrode of the first capacitor is connected to the one of the source and the drain of the second transistor, wherein a gate of the third transistor is connected to the scan line, wherein one of a source and a drain of the third transistor is connected to the second signal line, wherein the other of the source and the drain of the third transistor is directly connected to a gate of the fourth transistor, wherein one of a source and a drain of the fourth transistor is connected to the second light emitting element, wherein the other of the source and the drain of the fourth transistor is directly connected to the power supply line, wherein an output terminal of the shift register is electrically connected to an input terminal of the inverter, wherein an output terminal of the inverter is directly connected to the power supply line, wherein a first electrode of the second capacitor is connected to the gate of the fourth transistor, and wherein a second electrode of the second capacitor is connected to the one of the source and the drain of the fourth transistor. Corrected Appeal Br. 2–3 (Claims Appendix). REFERENCES2 The references relied upon by the Examiner as prior art are: Name Reference Date Li US 2004/0012545 A1 Jan. 22, 2004 2 All citations to the references are to the first named inventor/author only. Appeal 2020-001231 Application 14/591,047 4 Matsumoto3 JP 2003-216103 July 30, 2003 REJECTIONS Claims 2, 3, 5–7, 9–12, and 14 are rejected under pre–AIA 35 U.S.C. § 103(a) as being unpatentable over Li and Matsumoto. Final Act. 2. ISSUE Has the Examiner erred in finding Matsumoto’s transistor Tr10 teaches or suggests “an inverter” as recited in claim 2? ANALYSIS The Examiner rejects claim 2 as obvious over Li and Matsumoto. The Examiner relies primary on Li, but found that Li does not teach, inter alia, “wherein an output terminal of the inverter is directly connected to the power supply line.” Final Act. 5 (“Li does not explicitly disclose an inverter wherein an output terminal of the inverter is directly connected to the power supply line, and an output terminal of the shift register is electrically connected to an input terminal of the inverter.”). To address this deficiency, the Examiner introduces Matsumoto, finding that transistors Tr10 and Tr20 depicted in Matsumoto’s Figure 2 function as inverters that are both directly connected to the power supply lines PVdd11 and PVdd12, respectively, and they also receive input from shift register 100. Final Act. 6 (citing Matsumoto Figure 2). The Examiner explains that Matsumoto’s transistors Tr10 and Tr20 perform an inverting function because: 3 Matsumoto is a Japanese language reference. The Examiner provides a machine translation. Herein all references to Matsumoto are to the Examiner’s machine translation. Appeal 2020-001231 Application 14/591,047 5 [T]he light emitting pixel elements of the matrix display panel (see (OLED10), for example) can only be turned “on” and “off” according to the output of the PMOS transistors (see (Tr10), for example) and only in accordance with the voltage levels that will provide the “on” and “off” functions of the light emitting elements. Ans. 24. Appellant argues the Examiner has erred. Specifically, Appellant contends: [T]he transistors Tr10 and Tr20 can only control whether or not a voltage from PVdd10 is supplied to PVdd11 (through transistor Tr10) and whether or not a voltage from PVdd10 is supplied to PVdd12 (through transistor Tr20). That is, when transistor Tr10 is turned off, PVdd11 would be in a floating state if a voltage is not supplied by another route, and when Tr20 is turned off, PVdd12 would be in a floating state if a voltage is not supplied by another route. Thus, transistors Tr10 and Tr20 themselves do not output a “low signal” and do not function as inverter circuits. App. Br. 6. We begin by construing the disputed limitation. In finding Matsumoto teaches an inverter, the Examiner interprets “inverter” to mean “any circuit structure that” inverts the input—changing a high input to a low output, and a low input to a high output. Ans. 22. We discern no error in this interpretation.4 As the Examiner correctly explains, the Specification does not limit claimed inverter to any specific type of inverter or any specific configuration. Final Act. 18. Applying this interpretation, we agree with the Examiner that Matsumoto’s switching transistors Tr10 and Tr11, which are depicted and 4 Appellant does not challenge this interpretation or offer a competing proposal. Appeal 2020-001231 Application 14/591,047 6 discussed with reference to Figures 1 and 2, are inverters within the meaning of Appellant’s claims. Matsumoto teaches that the “power supply line PVdd10 supplies electric power to a plurality of pixel circuits containing pixel circuit Pix10.” Matsumoto at ¶ 14. Matsumoto describes that power is delivered to the pixel circuit Pix10 on power supply line PVdd11, on which a transistor Tr10 acts as a switch element. Id. The pixel circuit Pix10, together with transistor Tr10, are depicted in Matsumoto’s Figure 1 and are further illustrated in Figure 2 as part of a four pixel OLED. As shown, the transistor Tr10 receives signal input via its gate electrode connected to reset line RS10, which in turn connects to the output terminal of shift register 100. Matsumoto teaches that “reset line RS10 passes the reset signal which controls turning on and off of first transistor Tr10.” Matsumoto ¶ 15. The source electrode is connected to power supply line PVdd10, while the drain electrode connects to pixel circuit Pix10, which is supplied electric power by supply line PVdd11 and “is wired in parallel with selection line SL10.” Matsumoto ¶ 14–15. In operation, when “the reset signal of reset line RS10 becomes high, a first transistor Tr10 is turned OFF, and the electric power supply of pixel circuit Pix10 is intercepted.” Matsumoto ¶ 18. Matsumoto explains: As a result, OLED10 is separated from first power supply line PVdd10, and it goes out. Putting out lights is maintained until the reset signal of reset line RS10 becomes a low again and the selection signal of selection line SL 10 becomes a high. Thereby, the electric charge remainder to an optical element can be eliminated, and a residual image phenomenon can be improved. Matsumoto ¶ 18. Thus, Matsumoto teaches that when the reset line RS10 is high, the Tr10 is turned off such that current does not flow from supply line PVdd10 through the transistor to supply line PVdd11 in pixel circuit Pix10 Appeal 2020-001231 Application 14/591,047 7 and the OLED is not illuminated. And, when the reset line RS10 goes low, the current flows through the transistor to PVdd11, which causes the OLED to illuminate. Appellant argues that “the transistor ITSELF does NOT function as an inverter” because “the transistor Tr10 . . . can only control whether or not a voltage from PVdd10 is supplied to PVdd11.” Reply Br. 1. As such, Appellant asserts that when Tr10 is shut off, “PVdd11 would be in a floating state without another circuit element supplying voltage by another route.” Reply Br. 1. We do not find this argument persuasive for two reasons. First, Appellant’s argument is inconsistent with Matsumoto’s disclosure. Matsumoto teaches that “[w]hen the signal of a reset line RS10 becomes high, the first transistor TR10 is turned off and the OLED10 is cut from a first power source supplying line PVdd10 and then the OLED10 turns off the light.” Matsumoto Abstract (emphasis added). Thus, according to Matsumoto, when the input signal goes high, the output results in the OLED receiving no power and turning off. Appellant does not persuasively explain why this scenario does not constitute a low output from transistor Tr10. Instead, Appellant asserts that in certain situations, such as when Tr12 is in an off-state, PVdd11 would not be driven low. However, Appellant does not explain why Tr10 does not function as in inverter in those instances Tr12 is in an on-state and PVdd11 is driven low. Thus, even crediting Appellant’s argument, Matusmoto’s transistor Tr10 functions as an inverter in at least some situations. As noted above, we also do not find Appellant’s argument persuasive for a second reason. Appellant argues “PVdd11 would be in a floating state without another circuit element supplying voltage by another route,” but Appeal 2020-001231 Application 14/591,047 8 Matsumoto never states that PVdd11 would be in a floating state. Matsumoto’s only reference to any floated charge is made with reference to luminance data held between the drain of Tr11 and the gate of Tr12. See Matsumoto ¶ 17 (“Since the luminance data is held by floating between the drain electrode (or source electrode) of second transistor Tr11, and the gate electrode of 3rd transistor Tr12, luminescence of OLED10 according to the luminance data is maintained.”). In sum, we agree with the Examiner’s characterization of the operation of Matsumoto’s pixel circuit. We determine a skilled artisan would have understood Matsumoto as suggesting that PVdd11 would not be in a floating state in at least one possible implementation. As such, we are not persuaded the Examiner has erred in rejecting the claims under 35 U.S.C. § 103. Remaining Claims Appellant presents no separate arguments for patentability of any other claims. Accordingly, we sustain the Examiner’s rejections of these claims for the reasons stated with respect to the independent claims from which they depend. See 37 C.F.R. § 41.37(c)(1)(iv). CONCLUSION We affirm the Examiner’s decision to reject the claims. DECISION SUMMARY Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 2, 3, 5–7, 9– 12, 14 103(a) Li, Matsumoto 2, 3, 5–7, 9– 12, 14 Appeal 2020-001231 Application 14/591,047 9 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED