Semiconductor Energy Laboratory Co., Ltd.

Patent Trials and Appeals BoardOct 5, 2021

2021002680 (P.T.A.B. Oct. 5, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 16/233,358 12/27/2018 Shunpei YAMAZAKI 0756-11701 1457 31780 7590 10/05/2021 Robinson Intellectual Property Law Office, P.C. 3975 Fair Ridge Drive Suite 20 North Fairfax, VA 22033 EXAMINER KING, SUN MI KIM ART UNIT PAPER NUMBER 2813 NOTIFICATION DATE DELIVERY MODE 10/05/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ptomail@riplo.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte SHUNPEI YAMAZAKI, HIDEKAZU MIYAIRI, AKIHARU MIYANAGA, KENGO AKIMOTO, and KOJIRO SHIRAISHI Appeal 2021-002680 Application 16/233,358 Technology Center 2800 Before ROBERT E. NAPPI, CAROLYN D. THOMAS, and ERIC S. FRAHM, Administrative Patent Judges.1 NAPPI, Administrative Patent Judge. DECISION ON APPEAL Appellant2 appeals under 35 U.S.C. § 134(a) from the Examiner’s decision to reject claims 2–10. Claim 1 is canceled. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 Oral arguments were heard on August 17, 2021 before Judges Nappi, Thomas, and Bain, subsequent to the hearing the Judge Frahm was substituted for Judge Bain. 2 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Semiconductor Energy Laboratory Co., Ltd. Appeal Br. 3. Appeal 2021-002680 Application 16/233,358 2 BACKGROUND The Claimed Invention The invention relates to a semiconductor device, and specifically, to a “semiconductor device which has a circuit including a thin film transistor (hereinafter, referred to as a TFT) in which a channel formation region is formed using an oxide semiconductor film.” Spec. 1:7–9. Claims 2, 4, and 6 are independent. Claim 2 is illustrative of the invention and the subject matter in dispute, and is reproduced below: 2. A semiconductor device comprising: a gate electrode layer; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a first layer over the oxide semiconductor layer; a second layer over the oxide semiconductor layer; a source electrode layer electrically connected to the oxide semiconductor layer through the first layer; and a drain electrode layer electrically connected to the oxide semiconductor layer through the second layer, wherein each of the source electrode layer and the drain electrode layer includes a stacked structure of a first conductive layer and a second conductive layer, wherein one of the first conductive layer and the second conductive layer includes copper, wherein, in plan view: the oxide semiconductor layer includes a first region projected beyond a periphery of the first layer, Appeal 2021-002680 Application 16/233,358 3 the first layer includes a region projected beyond a periphery of the source electrode layer, the oxide semiconductor layer includes a second region projected beyond a periphery of the second layer, and the second layer includes a region projected beyond a periphery of the drain electrode layer, and wherein, in the oxide semiconductor layer: a thickness of the first region is smaller than a thickness of a region overlapping with the first layer, and a thickness of the second region is smaller than a thickness of a region overlapping with the second layer. Appeal Br. 19–20 (Claims App.). References The references relied upon by the Examiner are: Name Reference Date Kang US 6,900,872 B2 May 31, 2005 Ono et al. (“Ono”) US 2004/0232421 A1 Nov. 25, 2004 Yamazaki US 2005/0012097 A1 Jan. 20, 2005 Park et al. (“Park”) US 2008/0258141 A1 Oct. 23, 2008 The Rejection on Appeal Claims 2, 4, 6, and 8–10 stand rejected under pre-AIA 35 U.S.C. § 103(a) as being unpatentable over Ono, Yamazaki, and Park. Final Act. 2. Claims 3, 5, and 7 stand rejected under pre-AIA 35 U.S.C. § 103(a) as being unpatentable over Ono, Yamazaki, Park, and Kang. Final Act. 9. DISCUSSION We have reviewed the Examiner’s rejection in light of Appellant’s arguments presented in this appeal. Arguments that Appellant could have made but did not make in the Briefs are deemed to be waived. See 37 C.F.R. Appeal 2021-002680 Application 16/233,358 4 § 41.37(c)(1)(iv). For the reasons discussed below, Appellant has persuaded us of error. Appellant identifies that each of independent claims 2, 4, and 6 recite “in plan view: the oxide semiconductor layer includes a first region projected beyond a periphery of the first layer” and “the second layer includes a region projected beyond a periphery of the drain electrode layer” and that the thickness of each the first and second region is smaller than a thickness of a region overlapping this first and second layer. Appeal Br. 4– 7. Appellant argues the Examiner erred in finding the prior art teaches or suggests this thinned region. Appeal Br. 8–16, Reply Br, 5–11. Appellant argues the Examiner relies on Ono for the claimed layer structures, and contends that the cited portion of Ono “fails to show a plan view” and fails to show any region projected beyond a periphery of the first layer and drain electrode layer. Reply Br. 6 (citing Ono, Fig. 11). Similarly, Appellant argues the other figures in Ono fail to illustrate the claimed layers. Id. (citing Ono, Figs. 7B, 7C, 7D, 10). We agree. On this record, neither the Final Action nor the Answer sufficiently identify the Examiner’s finding or reasoning as to the limitation “in plan view: the oxide semiconductor layer includes a first region projected beyond a periphery of the first layer.” Appeal Br. 19 (emphasis added). The Examiner finds that “Ono teaches a thinned semiconductor layer, where modifying the thinned semiconductor layer to be of an oxide semiconductor material would provide a thinned oxide semiconductor layer.” Ans. 5. The Examiner further finds that “[o]ne having ordinary skill in the art would recognize that an oxide semiconductor material would work in the channel of Ono because Park shows that oxide semiconductor (GIZO) is a well- Appeal 2021-002680 Application 16/233,358 5 known channel material for a thin film transistor.” Id. at 6–7. These findings address the rationale to combine, but not the disputed limitation itself. In the Final Office Action, the Examiner simply cites “Figure 11” (of Ono), but as discussed above, Figure 11 is not in “plan view” as recited in claim 2. The Examiner need not solely rely on Ono, as the rejection is obviousness based on a combination of references, but, on this record, we discern no finding as to how the combination teaches the disputed element. Accordingly, Appellant persuades us of error regarding the obviousness rejection of claim 2. We are persuaded of error regarding the obviousness rejections of the remaining claims (which include a limitation commensurate in scope with the disputed limitation of claim 2) for the same reason. We, therefore, do not sustain the obviousness rejections of claims 2– 10. CONCLUSION For the foregoing reasons, we reverse the Examiner’s decision rejecting claims 2–10. DECISION SUMMARY In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 2, 4, 6, 8–10 103(a) Ono, Yamazaki, Park 2, 4, 6, 8– 10 3, 5, 7 103(a) Ono, Yamazaki, Park, Kang 3, 5, 7 Appeal 2021-002680 Application 16/233,358 6 Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed Overall Outcome 2–10 REVERSED