SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Patent Trials and Appeals BoardMar 12, 2021

2020002331 (P.T.A.B. Mar. 12, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/954,353 04/16/2018 Jinchang ZHOU ONS02238C02US 2040 132194 7590 03/12/2021 SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (AS) 5005 E. McDowell Road Maildrop A700 Phoenix, AZ 85008 EXAMINER YEUNG LOPEZ, FEIFEI ART UNIT PAPER NUMBER 2899 NOTIFICATION DATE DELIVERY MODE 03/12/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ipdocket@iptech.law patents@onsemi.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte JINCHANG ZHOU, YUSHENG LIN, and MINGJIAO LIU Appeal 2020-002331 Application 15/954,353 Technology Center 2800 Before GEORGE C. BEST, BRIAN D. RANGE, and LILAN REN, Administrative Patent Judges. RANGE, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1–20. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. 1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies the real party in interest as Semiconductor Components Industries, LLC. Appeal Br. 3. Appeal 2020-002331 Application 15/954,353 2 CLAIMED SUBJECT MATTER2 Appellant describes the invention as relating to a semiconductor device and method of integrating a power module with an internal interposer and opposing substrates. Spec. ¶ 2. Claim 1 is illustrative: 1. A semiconductor device, comprising: a substrate; a plurality of first interconnect pads formed over a surface of the substrate; and a plurality of second interconnect pads formed over the surface of the substrate, wherein the second interconnect pads have an area different from an area of the first interconnect pads, and the first interconnect pads and second interconnect pads are electrically common and arranged in an identifiable pattern for alignment. REJECTION AND REFERENCES On appeal, the Examiner maintains the following rejections: Rejection 1: Claims 1, 6, 7, 13, 14, and 20 under 35 U.S.C. § 102(a)(1) as anticipated by Rowe et al., US 4,739,448, Apr. 19, 1988 (“Rowe”), and Rejection 2: Claims 1–5, 7–12, and 14–19 under 35 U.S.C. § 103 as obvious over Ishii et al., US 2015/0115269 A1, Apr. 30, 2015 (“Ishii”). OPINION We review the appealed rejections for error based upon the issues identified by Appellant and in light of the arguments and evidence produced 2 In this Decision, we refer to the Final Office Action dated July 30, 2019 (“Final Act.”), the Appeal Brief filed September 25, 2019 (“Appeal Br.”), the Examiner’s Answer dated December 2, 2019 (“Ans.”), and the Reply Brief filed February 3, 2020 (“Reply Br.”). Appeal 2020-002331 Application 15/954,353 3 thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential), (cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) (“[I]t has long been the Board’s practice to require an applicant to identify the alleged error in the examiner’s rejections.”)). After considering the evidence presented in this Appeal and each of Appellant’s arguments, we are not persuaded that Appellant identifies reversible error. Thus, we affirm the Examiner’s rejections for the reasons expressed in the Final Office Action and the Answer. We add the following primarily for emphasis. Appellant argues all claims as a group. See Appeal Br. 11–19. Therefore, consistent with the provisions of 37 C.F.R. § 41.37(c)(1)(iv) (2013), we limit our discussion to claim 1, and all other claims on appeal stand or fall together with claim 1. Rejection 1. The Examiner rejects claims 1, 6, 7, 13, 14, and 20 as anticipated by Rowe. Final Act. 2. The Examiner finds that Rowe teaches the structure of claim 1. Id. The Examiner finds, for example, that Rowe teaches interconnect pads (150 and 154 as depicted in Figure 14) of different areas that are electrically common and arranged in an identifiable pattern for alignment. Id. Appellant argues that Rowe Figure 3 teaches pads 74, 76, 78, and 80 and that Rowe teaches that all pads in layer 42 have a similar geometry. Appeal Br. 11–13; Reply Br. 4–6. Appellant’s argument does not identify error because the Examiner relies on the structure of Rowe at 150 and 154 as corresponding to the pads of claim 1. Ans. 3–4. Rowe does not refer to structures 150 and 154 as pads; rather, Rowe refers to structure 150 as a ground line and refers to structure 154 as a ground portion. Rowe 6:14–40. The Examiner, however, finds that structures 150 and 154 provide surfaces Appeal 2020-002331 Application 15/954,353 4 for electrical bumps. Ans. 3–4. The Examiner’s finding is supported by Rowe. See Rowe Fig. 3 (depicting bump 146 on structure 148 which is the end of ground line 150 and depicting bump 152 on ground portion 154). The Examiner thus determines that structures 150 and 154 are pads with the scope of claim 1. Ans. 3–4. Rowe also establishes that structures 150 and 154 have different areas. Rowe Fig. 14. Appellant does not persuasively refute the Examiner’s position. Also, because Rowe does not refer to structures 150 and 154 as being pads, a person of skill in the art would not read Rowe’s statement that “all pads 128 in layer 42 have a similar geometry” as teaching that structures 150 and 154 must have the same area. Rowe. 6:55–60. To the contrary, Rowe Figure 14 suggests that the geometry and areas of structures 150 and 154 are different. Appellant also argues that Rowe structures 150 and 154 cannot be used for alignment because they are symmetric and do not allow a determination of whether a wafer has been inserted into a sawing tool correctly. Appeal Br. 12–13. Appellant’s argument is unpersuasive because it argues limitations that claim 1 does not recite. Claim 1 requires that the first and second interconnect pads be “arranged in an identifiable pattern for alignment.” Rowe structures 150 and 154 are arranged in an identifiable pattern. Ans. 4–5; Rowe Fig. 14. The Rowe pattern permits alignment to Rowe’s bumps. Ans. 4–5. Claim 1 does not require asymmetry as Appellant argues. Because Appellant’s arguments do not identify error, we sustain this rejection. Appeal 2020-002331 Application 15/954,353 5 Rejection 2. The Examiner rejects claims 1–5, 7–12, and 14–19 under 35 U.S.C. § 103 as obvious over Ishii et al., US 2015/0115269 A1, Apr. 30, 2015 (“Ishii”).3 The Examiner finds that the structure of Ishii Figure 28 depicts, for example, pluralities of interconnect pads having different areas. Final Act. 7. The Examiner finds that Figure 28 teaches first and second interconnect pads being electrically common through wires WR1. Id. The Examiner determines that Ishii “does not teach plural first interconnect pads to be electrically common (at the same electrical potential).” Id. The Examiner finds that Fig. 29 teaches plural first interconnect pads to be electrically common “through wires WR4” and determines that it would have been obvious to make the first interconnect and second interconnect pads to be electrically common “for the benefit of enhancing current supplying performance.” Id. Appellant argues that Ishii does not teach making “the entirety of the pads electrically common.” Appeal Br. 18; see also Reply Br. 8–9. Appellant’s argument is unpersuasive because claim 1 does not require that all pads on the substrate be electrically common. Rather, claim 1 only requires at least two pads of a first area and at least two pads of a second area be electrically common. Appellant admits Ishii teaches “a first grouping of electrode pads (PD1a) electrically coupling to another group of electrode 3 In the Final Office Action, the Examiner separately articulated two rejections based on Ishii: (1) a rejection of claims as anticipated by Ishii or, in the alternative, as obvious over Ishii and (2) a rejection of claims as obvious over Ishii. Final Act. 3, 7. In the Answer, the Examiner withdrew the first of these rejections but maintained the second. Ans. 3; see also Reply Br. 2 (assuming that the rejection over Ishii under Section 103 is maintained). Appeal 2020-002331 Application 15/954,353 6 pads (PD2)” (Appeal Br. 18), and this admitted structure is sufficient to satisfy claim 1’s “electrically common” requirement. Moreover, Appellant does not persuasively refute the Examiner’s findings regarding Ishii’s pads being interconnected by wires and does not persuasively dispute the Examiner’s stated rationale for modifying the teachings of Ishii’s Figure 28. Appellant also argues that laim 1’s “electrically common” recitation requires elements “couple to the same electrical source” rather than merely having “the same electrical potential.” Appeal Br. 19. As explained above, however, the Examiner’s rejection is based upon a person of skill in the art connecting various pads via wires. Final Act. 7; Ans. 5–6. Thus, even if Appellant’s claim construction were accepted, claim 1’s “electrically common” recitation does not distinguish claim 1 from the Examiner’s articulation of modified Ishii. Because Appellant does not identify error, we sustain the rejection. DECISION SUMMARY In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1, 6, 7, 13, 14, 20 102(a)(1) Rowe 1, 6, 7, 13, 14, 20 1–5, 7–12, 14–19 103 Ishii 1–5, 7–12, 14–19 Overall Outcome 1–20 Appeal 2020-002331 Application 15/954,353 7 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED