Ren Wang et al.

Patent Trials and Appeals BoardFeb 21, 2020

14583389 - (D) (P.T.A.B. Feb. 21, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/583,389 12/26/2014 Ren Wang P71780 1071 96162 7590 02/21/2020 Law Office of R. Alan Burnett, PS c/o CPA Global 900 Second Avenue South, Suite 600 Minneapolis, MN 55402 EXAMINER VERDERAMO III, RALPH A ART UNIT PAPER NUMBER 2136 NOTIFICATION DATE DELIVERY MODE 02/21/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): alan@patentlylegal.com docketing@cpaglobal.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte REN WANG, ANDREW J. HERDRICH, YEN-CHENG LIU, HERBERT H. HUM, JONG SOO PARK, CHRISTOPHER J. HUGHES, NAMAKKAL N. VENKATESAN, ADRIAN C. MOGA, AAMER JALEEL, ZESHAN A. CHISHTI, MESUT A. ERGIN, JR-SHIAN TSAI, ALEXANDER W. MIN, TSUNG-YUAN C. TAI, CHRISTIAN MACIOCCO, and RAJESH SANKARAN Appeal 2019-000076 Application 14/583,389 Technology Center 2100 Before MAHSHID D. SAADAT, ALLEN R. MacDONALD, and NABEEL U. KHAN, Administrative Patent Judges. MacDONALD, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant0F1 appeals from the Examiner’s decision to reject claims 1–10 and 18–25. Claims 11–17 were withdrawn from consideration. We have jurisdiction under 35 U.S.C. § 6(b). We affirm in part. 1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Intel Corporation. Appeal Br. 4. Appeal 2019-000076 Application 14/583,389 2 CLAIMED SUBJECT MATTER Claims 1 and 6 are illustrative of the claimed subject matter (emphasis, formatting, and bracketed material added): 1. A processor, configured to be implemented in a computer system, comprising: [A.] a plurality of cores, each having at least one associated cache occupying a respective level in a cache hierarchy; [B.] a last level cache (LLC), communicatively coupled to the plurality of cores; and [C.] a memory controller, communicatively coupled to the plurality of cores, configured to support access to external system memory when the processor is installed in the computer system; [D.] wherein each of the caches associated with a core, and the LLC include a plurality of cacheline slots for storing cacheline data, and wherein the processor is further is configured to support a machine instruction that when executed by a core causes the processor to demote a cacheline from a lower- level cache to a higher-level cache. 6. The processor of claim 1, wherein the computer system is a multi- socketed computer system employing a Non-Uniform Memory Access (NUMA) architecture in which multiple instances of the processor are to be installed, each socket including a processor and local system memory, and the processor further includes a socket-to-socket interconnect interface configured to facilitate communication between processors installed in different sockets, and wherein execution of the machine instruction causes a processor operating as a local socket to: [E.] demote a cacheline to the LLC cache on the local socket; and [F.] push a copy of the cacheline to an LLC of a processor installed in a remote socket, wherein the cacheline is pushed via the socket-to-socket interconnect interface. Appeal 2019-000076 Application 14/583,389 3 REFERENCES The prior art relied upon by the Examiner is: Name Reference Date Arimilli US 6,330,643 B1 Dec. 11, 2001 Gaither US 2008/0229009 A1 Sept. 18, 2008 REJECTIONS A. The Examiner rejects claims 1–5 and 18–21 under 35 U.S.C. § 102(a)(1) as being anticipated by Gaither. Final Act. 2–7. Appellant separately argues claim 1. Appellant does not present separate arguments for claims 2–5 and 18–21. Thus, the rejection of these claims turn on our decision as to claim 1. Except for our ultimate decision, we do not discuss the § 102(a)(1) rejection of claims 2–5 and 18–21. B. The Examiner rejects claims 6–10 and 22–25 under 35 U.S.C. § 103 as being unpatentable over the combination of Gaither and Arimilli. Final Act. 8–20. Appellant separately argues claim 6. Appellant does not present separate arguments for claims 7–10 and 22–25. Thus, the rejection of these claims turn on our decision as to claim 6. Except for our ultimate decision, we do not discuss the § 103 rejection of claims 7–10 and 22–25. OPINION We have reviewed the Examiner’s rejections in light of Appellant’s arguments that the Examiner has erred. Appeal 2019-000076 Application 14/583,389 4 A. Appellant raises the following argument in contending that the Examiner erred in rejecting claim 1 under 35 U.S.C. § 102(a)(1). As clearly shown in FIG. 3, a cell 302 is not a processor as would be recognized by a person having ordinary skill in the art (PHOSITA) at the time of the invention and in view of the application specification and drawings. Among other indicators, it is well-known that system memory comprising RAM is not implemented on a processor. In addition, processor cores 308 are also referred to as processors 308 and illustrated as processors (e.g., Proc. 1, Proc. 2, etc.). By comparison, a non- limiting examples of processor having the claimed configuration are shown in Figures 5 (see above), 1, 8, 8a, and 8b of the present application. As illustrated in Figure 5, memory 113 is a separate component from the processor that is external to the processor (the processor includes a processor core portion 500 that includes the processor cores and the LI and L2 caches and an “uncore” portion 502 that includes the L3 cache (the LLC) and the memory controller). As would be recognized by a PHOSITA, the processors in the present application employ a System on a Chip (SoC) architecture that includes the core portion and the uncore portion (see Figures 8, 8a, and 8b), wherein memory is external to the processor. . . . . . . . . The Examiner has not presented any evidence that one of ordinary skill in the art, in view of the specification and drawings of the present application, would construe “external system memory” to be part of the claimed processor of claim 1. The Examiner’s interpretation of this claim element is overly broad and is not supported by any factual evidence. . . . . Under the Examiner’s interpretation of claim 1, the claim element “configured to support access to external system memory when the processor is installed in the computer system” is given no meaning. If the external system memory is construed to be part of the processor, as asserted by the examiner, then the claim terms “when the processor is installed in the computer system” have no meaning and would render these Appeal 2019-000076 Application 14/583,389 5 claim terms as superfluous. In addition, the Examiner’s interpretation has rendered the claim term “external” to have [no] meaning. Under the Examiner’s argument, “system memory 324 is external to the processor cores 308.” This would imply that there are processors that would be known to those of ordinary skill in the art that have system memory in the processor cores. This would also require the memory controller to be in the processor cores, or otherwise if the memory controller was external to the processor cores the memory controller would need to access system memory in the processor cores. The Examiner has not identified such a processor, and Applicant respectfully asserts that such a processor does not exist. Appeal Br. 18–20 (Appellant’s emphasis omitted; panel’s emphasis added); see also Reply Br. 5–14. We are not persuaded the Examiner erred. Instead, we agree with the Examiner that Gaither’s cell discloses the claimed “processor.” See Final Act. 2; see also Ans. 3. More specifically, claim 1 recites that the “processor” comprises “a plurality of cores,” “a last level cache (LLC),” and “a memory controller.” Similar to the “processor” of claim 1, Gaither discloses that cell 302 includes a plurality of processor cores 308, an L4 cache 318, and memory controller 320. See Gaither ¶¶ 21, 22. Thus, notwithstanding the fact that Gaither uses different terminology to identify the disclosed structure (i.e., cell rather than processor), Appellant has not persuasively shown that the Examiner erred in finding Gaither’s cell discloses the claimed “processor.” Further, we do not agree with Appellant that Gaither’s system memory fails to disclose the claimed “external system memory” because Gaither discloses that system memory 324 is part of cell 302. Instead, we agree with the Examiner that claim 1 does not recite what the system memory is external from. See Ans. 4. Rather, claim 1 merely recites “a Appeal 2019-000076 Application 14/583,389 6 memory controller . . . configured to support access to external memory.” Gaither discloses this element, as Gaither discloses a memory controller 320 that processes data transfers to and from a system memory 324, where system memory 324 is external from memory controller 320. See Gaither ¶ 22. Appellant further raises the following argument in contending that the Examiner erred in rejecting claim 1 under 35 U.S.C. § 102(a)(1). A process running on a processor core does not equate to a processor core. A machine instruction, as is well-known in the art, is an instruction that is executed by a machine (i.e., a processor or processor core) as part of the processor’s instruction set – the set of machine instructions that comprises a computer’s machine language. The claimed “machine instruction” is ‘a’ machine instruction – it is singular. It is not possible to have a process running on a core comprise a single machine instruction. Appeal Br. 21 (emphasis added); see also Reply Br. 15–16. We are not persuaded by this argument. As a threshold matter, the Examiner found that Gaither’s processor cores 308, as opposed to push engine 326 (which Gaither discloses is implemented on one of processor cores 308), teaches or suggests the claimed “plurality of cores.” See Final Act. 2; see also Gaither ¶ 23. But even further, claim 1 recites “wherein the processor is further . . . configured to support a machine instruction . . . executed by a core.” The aforementioned element only requires that a processor core execute a machine instruction, not that the processor core is required to only execute a single machine instruction. Thus, we agree with the Examiner that Gaither’s disclosure of push engine 326 implementing a push instruction discloses the aforementioned element, notwithstanding that push engine 326 may implement other instructions. See Ans. 4–5. Appeal 2019-000076 Application 14/583,389 7 Appellant additionally raises the following argument in contending that the Examiner erred in rejecting claim 1 under 35 U.S.C. § 102(a)(1). [Gaither’s] scheme is not commensurate with how a processor core executes machine instructions. The machine instructions, also referred to as machine code, is generated by compiling source code to opcode (operation code), which is then linked (using various opcode libraries) to generate the machine code that is executed on a processor or processor core. There is no mechanism to dynamically inject a single machine code instruction into a sequence of existing machine code – that is not feasibly possible, and Gaither provides no disclosure on how this might be done (nor would a PHOSITA have any reason to attempt to do so). Rather, a PHOSITA skilled in the computer and processor arts would recognize the Gaither push engine scheme is implemented at the software level using multiple processes executing on the processor core(s) under which data is exchanged between the processes (enabling the processes to interact with one another). As is well known, processes are implemented as threads of machine instructions that are executed on physical machines, such as a processor core. . . . . . . . In [Gaither], the information provided by the push engine is included with the push instruction, which again is sent from the push engine to the source node. In summary, it is clear that the “push instruction” is not a machine instruction that is executed on a processor core. Appeal Br. 22–23, 27 (emphasis added). This argument is not persuasive either. Gaither discloses push engine 326 implements a push instruction to push block data to at least one target memory. See Gaither ¶ 27. Gaither further describes that push engine 326 can be implemented as operation code (i.e., opcode), and that a push instruction includes an opcode and operand that identifies a block of data on which the corresponding line of opcode operates on. See Gaither ¶¶ 23, 36. Appeal 2019-000076 Application 14/583,389 8 As a person of ordinary skill in the art would understand that an opcode is a part of a machine instruction, we agree with the Examiner that Gaither’s push instructions discloses the claimed “machine instruction” of claim 1. See Final Act. 3–4; see also Ans. 5. Appellant further raises the following argument in contending that the Examiner erred in rejecting claim 1 under 35 U.S.C. § 102(a)(1). There is no discussion in Gaither of demoting a cacheline via the push instruction. As clearly stated, the push instruction causes the source processor to push a coherent copy of the block data to the at least one target memory. It does not push the block data to the at least one target memory (removing the block from its current location) but rather pushes a copy of the data, which means it leaves a copy of the data in wherever it is pushed from. This does not equate to demoting a cacheline, as described in the present application. Under the present application, demoting a cacheline results in the cacheline being evicted from the cache. This is not in accordance with conventional cache behavior under which a cache eviction algorithm is used to determine which cacheline would be evicted. Appeal Br. 27 (Appellant’s emphasis omitted; panel’s emphasis added); see also Reply Br. 16. We are not persuaded by this argument either. Contrary to Appellant’s argument, Gaither’s disclosure of the push instruction is not limited to the scenario of pushing a copy of the data to a target location and leaving a copy of the data in a source location. Instead, Gaither explicitly discloses that the push instruction encompasses “any transfer of a block of data to one or more potential consumer nodes that occurs in the absence of detecting a request . . . from the potential consumer for such block of data.” Gaither ¶ 10 (emphasis added). Gaither goes on to disclose the ownership of the block of data can be transferred from the source location to the target location. See Gaither ¶¶ 18, 32. Thus, we agree with the Examiner that Appeal 2019-000076 Application 14/583,389 9 Gaither’s disclosure of the push operation does encompass removing the block of data from the source location, and, thus, Gaither does disclose the claimed “demot[ing] a cacheline from a lower-level cache to a higher-level cache.” See Final Act. 3–4; see also Ans. 5–6. B. Appellant raises the following argument in contending that the Examiner erred in rejecting claim 6 under 35 U.S.C. § 103. A PHOSITA at the time of the invention and in view of the application specification and drawings would not consider system interconnect 306 to be a socket-to-socket interconnect interface, as required by claim 6. However, even if it was construed as such, there is no disclosure in Gaither teaching or suggesting demot[ing] a cacheline to the LLC cache on the local socket and push[ing] a copy of the cacheline to an LLC of a processor installed in a remote socket, wherein the cacheline is pushed via the socket-to-socket interconnect interface. Under claim 6, the cacheline is demoted to the LLC, which is the LLC on the local socket, and a copy of that cacheline is pushed to the LLC on another processor (installed in the remote socket). Under Gaither there is at most a single copy of a cacheline that would be pushed to a single LLC. A shared cache memory that is accessible to multiple processors would constitute a single LLC, not a local LLC and a remote LLC. . . . . With further respect to the rejection of claim 6, the Examiner has failed to indicate how Gaither would be combined with Arimilli, why a PHOSITA would be motivated to do so, nor provide any evidence to why a PHOSITA would have a reasonable expectation of success in implemented the combination. . . . . . . . [The Examiner fails to provide] evidence to how Gaither would be modified by Arimilli. In addition, the Examiner’s Appeal 2019-000076 Application 14/583,389 10 presumed motivation to combine, “This essentially would allow different sized and speed memories instead of having everything stored in the same large and slow location to make everything uniform” is unrelated to the invention of claim 6, and doesn’t even correspond to the purpose of NUMA architectures in the first place, which is to enable processors/cores on different sockets to remotely access memory on other sockets. The non- uniform memory access that results is not something intended as a benefit, but rather is inherent to the NUMA design. Appeal Br. 38–39, 41 (Appellant’s emphasis omitted; panel’s emphasis added); see also Reply Br. 18–20. We are persuaded the Examiner erred in finding the combination of Gaither and Arimilli teaches or suggests “push a copy of the cacheline to an LLC of a processor installed in a remote socket, wherein the cacheline is pushed via the socket-to-socket interconnect interface,” as recited in claim 6.1F2 While we agree with the Examiner that Gaither’s system interconnect teaches or suggests the claimed “socket-to-socket interconnect interface” (see Final Act. 8–9 (citing Gaither, Fig. 3); see also Gaither ¶ 20), we agree with Appellant that Gaither does not teach or suggest the push engine pushing a block of data from a low-level cache of a cell to a target memory located within another cell via the system interconnect. See Appeal Br. 38; see also Gaither ¶¶ 23–25. CONCLUSION The Examiner has not erred in rejecting claims 1–5 and 18–21 as being anticipated under 35 U.S.C. § 102(a)(1). 2 We do not reach Appellant’s additional arguments regarding the rejection of claim 6, as the identified issue is dispositive. Appeal 2019-000076 Application 14/583,389 11 The Examiner erred in rejecting claims 6–10 and 22–25 as being unpatentable under 35 U.S.C. § 103. The Examiner’s rejection of claims 1–5 and 18–21 as being anticipated under 35 U.S.C. § 102(a)(1) is affirmed. The Examiner’s rejection of claims 6–10 and 22–25 as being unpatentable under 35 U.S.C. § 103 is reversed. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1–5, 18–21 102(a)(1) Gaither 1–5, 18–21 6–10, 22– 25 103 Gaither, Arimilli 6–10, 22– 25 Overall Outcome 1–5, 18–21 6–10, 22– 25 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv) (2017). AFFIRMED IN PART