Realtek Semiconductor Corp.

Patent Trials and Appeals BoardJul 31, 2020

15677240 - (D) (P.T.A.B. Jul. 31, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/677,240 08/15/2017 Chia-Liang (Leon) Lin 251812-7090 8235 109673 7590 07/31/2020 McClure, Qualey & Rodack, LLP 280 Interstate North Circle SE Suite 550 Atlanta, GA 30339 EXAMINER BAHR, KURTIS R. ART UNIT PAPER NUMBER 2844 NOTIFICATION DATE DELIVERY MODE 07/31/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): dan.mcclure@mqrlaw.com terri.logan@mqrlaw.com uspatents@mqrlaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte CHIA-LIANG (LEON) LIN Appeal 2019-005122 Application 15/677,240 Technology Center 2800 BEFORE JEFFREY B. ROBERTSON, DONNA M. PRAISS, and MERRELL C. CASHION, JR., Administrative Patent Judges. ROBERTSON, Administrative Patent Judge. DECISION ON APPEAL1 STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the Examiner’s decision to reject claims 1–8. See Appeal Br. 4, 8. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. 1 This Decision includes citations to the following documents: Specification filed August 15, 2017 (“Spec.”); Non-Final Office Action mailed January 18, 2019 (“Non-Final Act.”); Appeal Brief filed April 8, 2019 (“Appeal Br.”); Examiner’s Answer mailed May 9, 2019 (“Ans.”); and Reply Brief filed June 19, 2019 (“Reply Br.”). 2 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Realtek Semiconductor Corp. See generally Appeal Br. Appeal 2019-005122 Application 15/677,240 2 CLAIMED SUBJECT MATTER Appellant states the invention relates to clock buffer circuits having improved noise immunity. Spec. ¶ 1. Claim 1, reproduced below, is illustrative of the claimed subject matter (Appeal Br., Claims Appendix A-1): 1. A clock buffer circuit comprising: a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, a power pin, and a ground pin of the first inverter directly connect to the first clock signal, a first source node, and a second source node, respectively, and wherein an output pin of the first inverter generates the second clock signal; a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, a power pin, and a ground pin of the second inverter directly connect to the second clock signal, the first source node, and the second source node, respectively, and wherein an output pin of the second inverter generates the third clock signal; a first resistor directly connected between a first DC (direct- current) voltage and the first source node; and a second resistor directly connected between a second DC voltage and the second source node, wherein the first source node is connected to the first DC voltage only through the first resistor, and the second source node is connected to the second DC voltage only through the second resistor, thereby configuring the circuit to have improved noise immunity. Claim 5 is also independent and recites a method for improving noise immunity in a clock buffer circuit, where the clock buffer circuit has similar limitations as recited in claim 1. Id. at A-2. Appeal 2019-005122 Application 15/677,240 3 REFERENCES The prior art relied upon by the Examiner is: Name Reference Date Hirano et al. (hereinafter “Hirano”) US 5,179,298 January 12, 1993 Chakraborty US 9,647,669 B1 May 9, 2017 Oh et al. (hereinafter “Oh”) US 9,866,332 B2 January 9, 2018 REJECTIONS 1. The Examiner rejected claims 1–8 under 35 U.S.C. § 103 as unpatentable over Chakraborty and Hirano. Non-Final Act. 3–12. 2. The Examiner rejected claims 1 and 5 under 35 U.S.C. § 103 as unpatentable over Chakraborty and Oh. Non-Final Act. 12–17. OPINION Rejection 1 We limit our discussion to claim 1, which is sufficient to resolve the issues associated with this rejection. The Examiner’s Rejection In rejecting claim 1 as obvious over the combination of Chakraborty and Hirano, the Examiner found Chakraborty discloses a clock buffer circuit including the arrangement of inverters as recited in claim 1, but does not teach the recited first and second resistors. Non-Final Act. 3–4. The Examiner found Hirano discloses a first resistor directly connected between a first DC voltage and a source node and a second resistor directly connected between a second DC voltage and a second source node, which configures the circuit to have improved noise immunity. Id. at 4–5. The Examiner Appeal 2019-005122 Application 15/677,240 4 determined it would have been obvious to have combined the inverters for Chakraborty’s clock signals with Hirano’s resistors “to suppress noise that would cause voltage fluctuations of Hirano to suppress fluctuations in the power and ground to avoid[] errors in the desired output signal to improve circuit performance.” Id. at 5, citing Hirano, col. 3, ll. 31–42. Appellant’s contentions Appellant argues, inter alia, that Hirano does not disclose resistors for noise immunity, but, rather, Hirano discloses resistors to adjust or shift switching levels of an input signal. Appeal Br. 7. Appellant argues one of ordinary skill in the art would not have been motivated to have combined Hirano with Chakraborty because Chakraborty does not identify any switching level issues, in part, because Hirano is directed to an input buffer circuit and Chakraborty is directed to a high-frequency divider. Id. Appellant contends the problem addressed in Hirano is not present in the system of Chakraborty. Id. Issue Has Appellant demonstrated reversible error in the Examiner’s position that it would have been obvious to have combined Chakraborty and Hirano to arrive at the clock buffer circuit of claim 1? Discussion We are persuaded by Appellant’s arguments. The Examiner’s position is that (1) small parasitic resistances exist in all connections that influence the DC and ground levels creating variations in voltage levels or noise while operating due to the wires, connections, or traces on the voltage Appeal 2019-005122 Application 15/677,240 5 lines to the transistors and (2) Hirano adjusts the resistance to decrease current and avoid malfunctions related to parasitic resistance. Ans. 19; Non- Final Act. 3–4; Hirano col. 3, ll. 31–42. However, as pointed out by Appellant, Chakraborty does not identify or provide any evidence of a switching level issue. The primary object of Hirano’s invention is to suppress the switching level variations or deviations brought about by parasitic resistance caused by wiring. Hirano, col. 3, ll. 25–28. Hirano discloses that parasitic resistance is not generated for input buffer circuits disposed at close positions. Id. at col. 4, ll. 42–47, col. 4, l. 54 – col. 5, l. 12; Figs. 1B, 5A. Hirano further discloses that sufficient parasitic resistance in order to apply resistors is dependent on the length of wire and is not always necessary. Hirano col. 4, ll. 42–47. As argued by Appellant, Chakraborty does not mention any particular parasitic resistance issues. Appeal Br. 7 (arguing that “[t]he problem solved/addressed by Hirano is simply not present in the system of Chakraborty.”). Although it may be possible that Chakraborty’s frequency divider contains wiring in a sufficient length to give rise to parasitic resistance such that the resistors in Hirano may be beneficial, the Examiner does not point to any particular disclosures in Chakraborty that would tend to support this position, particularly for the clock buffers disclosed therein. Therefore, the Examiner’s reliance on Hirano for voltage fluctuations as a reason for adding resistors to the clock buffers of Chakraborty in not sufficiently supported by the record. As a result, we reverse the Examiner’s rejection of claims 1–8 as obvious over Chakraborty and Hirano. Appeal 2019-005122 Application 15/677,240 6 Rejection 2 We limit our discussion to claim 1, which is sufficient to resolve the issues associated with this rejection. The Examiner’s Rejection In rejecting claim 1 as obvious over the combination of Chakraborty and Oh, the Examiner made similar findings with respect to Chakraborty as discussed above for Rejection 1. Non-Final Act. 12–13. The Examiner found Oh discloses the first and second resistors missing from Chakraborty, where Oh discloses the addition of resistors to the circuit reduces noise at rising and falling edges of the signal. Id. at 13–14. The Examiner determined it would have been obvious to have combined the inverters for clock signals disclosed in Chakraborty with the resistors disclosed in Oh to control edges of the signals to reduce radiated noise in order to improve circuit performance. Id. at 14. Appellant’s contentions Appellant argues the resistors in Oh are not connected to source nodes of an inverter, and Oh does not disclose source nodes as recited in claim 1 to which the resistors can connect. Appeal Br. 9–10. Appellant argues Oh is directed to a system using the human body as a receiver, which has nothing to do with inverter circuits of a clock buffer circuit, and is not reasonably pertinent to the particular problem with which the applicant was concerned. Id. at 10. In this regard, Appellant contends the noise disclosed in Oh is from the human body when the human body is used as a receiver. Id. at 10– 11. Appellant argues the noise in Oh is a reception stage noise that is particular to the human body, which would not properly motivate a person Appeal 2019-005122 Application 15/677,240 7 skilled in the art to utilize the resistors of Oh in a clock buffer/inverter circuit of Chakraborty. Id. at 13. In addition, Appellant argues that adding resistors to a circuit does not necessarily improve noise immunity. Id. at 13– 14. Issue Has Appellant demonstrated reversible error in the Examiner’s position that it would have been obvious to have combined Chakraborty and Oh to arrive at the clock buffer circuit of claim 1? Discussion We are persuaded by Appellant’s argument that the Examiner did not provide a sufficient reason to utilize the resistors of Oh in a clock buffer/inverter circuit of Chakraborty. That is, Oh specifically relates to removing radiation noise from a human body when it is utilized as a receiver in communications. Oh, col. 1, ll. 15–22. Oh discloses the human body “operates as an antenna and thus surrounding noises absorbed from surroundings are added to a signal having been transmitted from a transmitter.” Id. at col. 1, ll. 36–39. Oh discloses a large peak current may be supplied from a digital power supply node or may flow out to a digital ground mode, where noise caused by the large peak current may be radiated in a wavelength from outside a receiver and absorbed again through the epidermis of the human body and transmitted again as a noise signal. Id. at col. 7, ll. 30–61. Oh discloses the receiver is configured with a resistor for removing reception stage noise radiation. Id. at col. 7, l. 61 –col. 8, l. 44; Fig. 4. Appeal 2019-005122 Application 15/677,240 8 Thus, Oh discloses a method for removing radiation noise caused by the human body receiver. Although we agree with the Examiner that Oh discloses resistors to improve noise immunity, which is a type of noise reduction (Ans. 21), we agree with Appellant that the Examiner has failed to provide sufficient reasoning as to why one of ordinary skill in the art would have looked to the resistors in Oh in order to improve the clock buffer/inverter circuit of Chakraborty, which does not involve the human body as a receiver. The Examiner has not sufficiently established that Chakraborty would be subject to the same or similar radiated noise that is addressed in Oh. As a result, we reverse the Examiner’s rejection of claims 1 and 5 as obvious over Chakraborty and Oh. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1–8 103 Chakraborty, Hirano 1–8 1, 5 103 Chakraborty, Oh 1, 5 Overall Outcome 1–8 REVERSED