Rambus Inc.

Patent Trials and Appeals BoardMar 1, 2021

2020005504 (P.T.A.B. Mar. 1, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 16/113,900 08/27/2018 Masum Hossain R-RA10815US04 3410 68325 7590 03/01/2021 PVF -- RAMBUS, INC. c/o PARK, VAUGHAN, FLEMING & DOWLER LLP 2820 FIFTH STREET DAVIS, CA 95618-7759 EXAMINER YU, LIHONG ART UNIT PAPER NUMBER 2631 NOTIFICATION DATE DELIVERY MODE 03/01/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): uspto-incoming@parklegal.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MASUM HOSSAIN and MARUF H. MOHAMMAD Appeal 2020-005504 Application 16/113,900 Technology Center 2600 Before MAHSHID D. SAADAT, ELENI MANTIS MERCADER, and BETH Z. SHAW, Administrative Patent Judges. SAADAT, Administrative Patent Judge. DECISION ON APPEAL1 STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the Examiner’s decision to reject claims 19, 20, 22–26, 28–33, and 35–38.3 We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 An oral hearing was held for this appeal on February 18, 2021. A transcript of the oral hearing will be entered into the record in due course. 2 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Rambus Inc. Appeal Br. 3. 3 Claims 1–18 have been canceled previously and claims 21, 27, and 34 are indicated as allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Appeal 2020-005504 Application 16/113,900 2 CLAIMED SUBJECT MATTER The claims are directed to sequence detection using at least one pre- cursor in addition to the main cursor to generate reference voltages that correspond to a particular sequence of symbols. See Spec. ¶¶ 4–9. According to the Specification, “an equalization technique is employed at the receiver to correct the channel induced interference, i.e., to remove or reduce all of the ISI [(inter-symbol interferences)] components from the received signal,” which “is generally data dependent and can include signal components with contributions based on prior (post-cursor) and post (pre- cursor) received signals.” Spec. ¶ 17. Claim 19, reproduced below, illustrates the claimed subject matter: 19. An integrated circuit (IC), comprising: a plurality of comparators, wherein each comparator has a respective reference voltage that is adjustable, wherein each comparator outputs a result signal based on comparing a received input from a communication channel with the comparator’s reference voltage, wherein reference voltages for the plurality of comparators are computed based on a main cursor and at least one pre-cursor associated with the communication channel, wherein the at least one pre-cursor corresponds to a future symbol, and wherein each computed reference voltage corresponds to a particular sequence of symbols; and a sequence-selection circuit to select a sequence of symbols based on result signals outputted by the plurality of comparators. See Appeal Br. 18 (Claims App.). Appeal 2020-005504 Application 16/113,900 3 REFERENCES AND REJECTIONS The prior art relied upon by the Examiner is: Name Reference Date Beidas US 6,278,732 B1 Aug. 21, 2001 Plasterer US 7,177,352 B1 Feb. 13, 2007 Kuramochi US 2008/0068245 A1 Mar. 20, 2008 Claims 19, 20, 22, 24–26, 28, 30–33, 35, 37, and 38 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Kuramochi and Plasterer. Final Act. 3–7. Claims 23, 29, and 36 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Kuramochi, Plasterer, and Beidas. Final Act. 7–8. ISSUE ON APPEAL Appellant’s arguments in the Appeal Brief present the following dispositive issue:4 Whether the Examiner erred in finding the combination of Kuramochi and Plasterer teaches or suggests “at least one pre-cursor associated with the communication channel, wherein the at least one pre-cursor corresponds to a future symbol,” as recited in claim 19 and similarly in independent claims 25 or 32. Appeal Br. 13–14 (emphasis added); see also Appeal Br. 18–22 (Claims App.). ANALYSIS We have reviewed the Examiner’s rejections in light of Appellant’s contentions in the Appeal Brief and the Reply Brief that the Examiner has erred, as well as the Examiner’s response to Appellant’s arguments in the 4 We do not address Appellant’s other contentions because this contention is dispositive of the issue on appeal. Appeal 2020-005504 Application 16/113,900 4 Appeal Brief. As discussed below, we are persuaded by Appellant’s contentions of Examiner error for the reasons discussed below. For the “pre-cursor” portion of the limitation at issue, the Examiner relies on the disclosure in Kuramochi of transmission of “the threshold values are determined based on bits previously determined, thus a pre- cursor.” Final Act. 4 (citing Kuramochi ¶¶ 9, 34, 37). The Examiner finds “[Kuramochi] does not explicitly disclose: the at least one pre-cursor corresponds to a future symbol,” and finds Plasterer discloses the missing limitation as explained below: Plasterer teaches: at least one pre-cursor corresponds to a future symbol (see Fig. 5, col. 5, lines 30-67 and col. 6, line 1- 3, where Plasterer describes slicer 516, slicer 522 and slicer 510, where slicer 516 and 522 slice the input signal with a positive and negative offset and slicer 510 slices the input signal with zero offset; see col. 2, lines 35-55, where Plasterer describes that the three slicers use three detection thresholds in parallel, and the three thresholds for slicing include the positive offset, the negative offset and no offset, the positive and negative offsets correspond to the expected pre-cursor component of the data channel, and the pre-cursor component is a result of symbols that have yet to arrive at the receiver). Final Act. 4–5. The Examiner also finds modifying Kuramochi with Plasterer’s pre-cursor would “cancel pre-cursor inter-symbol interference, as discussed by Plasterer (see col. 2, lines 35-40).” Final Act. 5. Appellant argues [i]n rejecting the independent claims, the Examiner fails to interpret the claim term “pre-cursor” consistently. While discussing paragraph [0037] in Kuramochi, the Examiner interprets the claim term “pre-cursor” as referring to “bits previously determined.” However, when discussing Fig. 5, col. 5, lines 30-67, col. 6, lines 1-3 in Plasterer, the Examiner interprets the claim term “precursor” as referring to future Appeal 2020-005504 Application 16/113,900 5 symbols. The claim term “pre-cursor” cannot simultaneously refer to past and future symbols, and the Examiner is improperly conflating the meaning of “past” and “future.” Therefore, the Examiner’s interpretation of the claim term “pre- cursor” is logically inconsistent. . . . Appeal Br. 13. Based on this distinction between “bits previously determined” and the “future symbols,” Appellant argues that the Examiner’s proposed combination is improper because modifying Kuramochi with Plasterer’s pre-cursor for the symbols that are yet to arrive would render Kuramochi unsatisfactory for its intended use and change the principle of its operation. Appeal Br. 14. In response, the Examiner explains that, absent any definition for the term “pre-cursor” recited in claim 19, “Kuramochi’s ‘bits previously determined’ is the Examiner’s broadest reasonable interpretation of the ‘pre- cursor.’” Ans. 3. The Examiner also explains that Plasterer’s pre-cursor inter-symbol interference (ISI) that “is a result of symbols that have yet to arrive at the receiver” teaches the recited “at least one pre-cursor corresponds to a future symbol.” Ans. 4 (citing Plasterer 2:45–46). With respect to how Kuramochi is modified with Plasterer’s pre-cursor, the Examiner finds: The Examiner considers that Kuramochi and Plasterer have the same functional structure, that is, a plurality of comparators connected to a selection circuit. The difference between Kuramochi and Plasterer is the method to compute the reference voltage based on a pre-cursor corresponding to a future symbol. Therefore, one of ordinary skill in the art can modify Kuramochi to use Plasterer’s method of computing the reference voltage. Ans. 5 (emphasis added). Appeal 2020-005504 Application 16/113,900 6 Based on a review of Kuramochi’s disclosure, we agree with Appellant that Kuramochi is concerned with sampling and processing the present or current input, as shown in Figure 10 and described in paragraphs 94–97. See Reply Br. 7–9. We further agree with Appellant’s assessment of Kuramochi’s Figure 10 stating “[n]ote that the claim feature ‘the at least one pre-cursor [that] corresponds to a future symbol’ corresponds to the ‘the next analog input signal’ in FIG. 10 of Kuramochi.” Reply Br. 9. That is, even if the references discuss a similar process with respect to using reference voltages for a plurality of comparators (see Ans. 5), the Examiner has not identified any teachings that relate to the recited method for computing the reference voltages based on a main cursor and a pre-cursor that corresponds to a future symbol. We also agree with Appellant’s assessment of the proposed combination asserting [t]herefore, Examiner is asserting that Kuramochi can use the next analog input signal to compute the threshold voltages for digitizing the present analog input signal. Appellant respectfully disagrees because this assertion makes no technical sense in the context of Kuramochi. The goal of the A-D converter of Kuramochi is to produce an accurate digital representation of the present analog input signal. If the next analog input signal is used to compute the threshold voltages for digitizing the present analog input signal, then the resulting m-bit digital value will not accurately represent the present analog input signal. Specifically, the Examiner’s modification would render Kuramochi’s method unsatisfactory for its intended purpose, namely, to accurately digitize the present analog input signal. Reply Br. 9. Therefore, we are persuaded that the Examiner erred in concluding “[t]he same structure can be used to function as an analog-to- Appeal 2020-005504 Application 16/113,900 7 digital converter when the thresholds are computed by using Kuramochi’s method, or to function to cancel pre-cursor inter-symbol interference when the thresholds are computed by using Plasterer’s method.” See Ans. 5. In view of the above analysis, and based on the record before us, we are constrained to conclude the Examiner errs in rejecting claim 19, as well as independent claims 25 and 32 that recite similar limitations, as obvious. CONCLUSION For the reasons stated above, we do not sustain the obviousness rejection of independent claims 19, 25, and 32, as well as claims 20, 22, 24, 26, 28, 30, 31, 33, 35, 37, and 38, dependent therefrom, over Kuramochi and Plasterer. The Examiner has not relied upon the additional references to teach or suggest the above-identified limitation in rejecting claim 19. See Final Act. 3–8. Accordingly, for reasons similar to those above for independent claims 19, 25, and 32, we do not sustain the remaining rejection. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 19, 20, 22, 24–26, 28, 30–33, 35, 37, 38 103 Kuramochi, Plasterer 19, 20, 22, 24–26, 28, 30–33, 35, 37, 38 23, 29, 36 103 Kuramochi, Plasterer, Beidas 23, 29, 36 Overall Outcome 19, 20, 22– 26, 28–33, 35–38 REVERSED