Rambus Inc.

Patent Trials and Appeals BoardMar 30, 2020

15389402 - (D) (P.T.A.B. Mar. 30, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/389,402 12/22/2016 Frederick A. Ware RBS2.P170C1 7808 44429 7590 03/30/2020 Peninsula Patent Group 2644 Placer St. Santa Cruz, CA 95062 EXAMINER BATAILLE, PIERRE MICHE ART UNIT PAPER NUMBER 2136 NOTIFICATION DATE DELIVERY MODE 03/30/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): lkreisman@peninsulaiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte FREDERICK A. WARE Appeal 2018-009235 Application 15/389,402 Technology Center 2100 Before JAMES R. HUGHES, CARL L. SILVERMAN, and SCOTT E. BAIN, Administrative Patent Judges. BAIN, Administrative Patent Judge. DECISION ON APPEAL Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s decision to reject claims 2–21, which constitute all claims pending in the application. Claim 1 has been cancelled. An oral hearing was held March 16, 2020. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Rambus, Inc. Appeal Br. 3. Appeal 2018-009235 Application 15/389,402 2 BACKGROUND The Claimed Invention Appellant’s claimed invention relates to “techniques for storing data and tags in different memory arrays.” Spec. ¶ 2. Claims 2, 9, and 15 are independent. Claim 2 is representative of the invention and the subject matter of the appeal, and reads as follows: 2. A device comprising: at least one memory device including a first bank group of memory storage locations; a second bank group of memory storage locations; interface circuitry coupled to a common bus, the interface circuitry responsive to a memory access command received via the common bus to select one of the first bank group of memory storage locations or the second bank group of memory storage locations for a memory access, the selection identified by a unique bank group address; wherein access to the first bank group of storage locations involves an access for first data; and wherein access to the second bank group of storage locations involves an access for first tag information associated with the first data. Appeal Br. 18 (Claims Appendix) (emphasis added). Reference The reference relied upon by the Examiner is: Name Reference Date Huffman et al. (“Huffman”) US 2002/0032838 A1 Pub. Mar. 14, 2002 The Rejections on Appeal Claims 2–21 stand rejected under 35 U.S.C. § 102(b) as unpatentable over Huffman. Final Act. 9–12. Appeal 2018-009235 Application 15/389,402 3 DISCUSSION We have reviewed the Examiner’s rejections in light of Appellant’s arguments presented in this appeal. Arguments which Appellant could have made but did not make in the Briefs are deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(iv). For the following reasons, on this record, we are persuaded of error. Appellant argues the Examiner erred in finding Huffman discloses selection of a first bank group or second bank group of memory storage locations, “the selection identified by a unique bank group address,” as recited in independent claim 2. Appeal Br. 12–13; Reply Br. 6–7. Appellant contends that Huffman discloses, at most, a generic DIMM memory access, rather than selecting (through a “memory access command received via the common bus”) a “unique bank group address,” as recited in the claim. Reply Br. 6–7. Appellant further argues that the Examiner erred in finding Huffman discloses a “memory device” and “access to the second bank group of storage locations involves an access for first tag information associated with the first data,” as recited in claim 2.2 We agree with Appellant’s arguments. The Examiner relies on Huffman Figure 2, which is reproduced below. 2 Appellant makes additional arguments regarding the “memory device” and “tag information” recited in claim 2. We need not reach these arguments. Appeal 2018-009235 Application 15/389,402 4 Figure 2 illustrates part of a “non-uniform memory access system” (NUMA), including “memory system X 110” and “memory system Y 120” coupled to “control arrangement 300” which “includes a memory/directory interface MD” and other components. Huffman ¶¶ 19, 24. In response to Appellant’s argument that Huffman does not disclose a “memory device,” the Examiner finds the arrangement illustrated in Figure 2 is the claimed “memory device,” and that the memory systems X and Y are “bank groups.” Ans. 8, 10. The Examiner reasons that Huffman’s description of accessing these memory locations necessarily includes selecting a unique “bank group address,” because “[w]ithout such bank group address, the memory directory interface would be unable to determine which bank group (memory system) to access.” Id. at 9. Huffman, however, describes memory systems X and Y as consisting of dual in-line memory modules (“DIMMs”). Huffman ¶ 28. Specifically, Huffman discloses “X controller 370 provides address and control information to dual in-line memory modules [] of the memory system X, while the Y controller 380 provides address and control information to DIMMs of the memory system Y.” Id. The Examiner does not explain, and Appeal 2018-009235 Application 15/389,402 5 we do not discern, any disclosure in Huffman that these DIMM modules can constitute the memory banks and bank groups as recited in claim 2. Appellant’s Specification defines memory “banks” and “bank groups” as follows: The memory cells in each of memory integrated circuits [] are arranged in banks, and the banks of memory cells are arranged in bank groups. Each memory integrated circuit [] has one or more bank groups. Each bank group operates independently and has separate address and data interfaces. Each bank group has multiple banks. Spec. ¶ 35 (emphases added). Accordingly, as Appellant argues, the Examiner’s finding that Huffman discloses an address identifying a particular DIMM location is not the same as finding Huffman discloses a unique address for a bank group, as recited in claim 2. Reply Br. 6–7. On this record, the Examiner has not sufficiently explained how a person of ordinary skill in the art would understand Huffman’s DIMM access as disclosing the disputed limitation of claim 2, as required for anticipation under § 102. For the foregoing reasons, we are persuaded of error regarding the rejection of claim 2. For the same reasons, we are persuaded of error regarding the rejection of the remaining claims, all of which include the same disputed limitation and were argued as a group with claim 2. Accordingly, we do not sustain the rejections of claims 2–21. Appeal 2018-009235 Application 15/389,402 6 SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 2–21 102 Huffman 2–21 DECISION We reverse the Examiner’s decision rejecting claims 2–21. REVERSED