Rajendra D. PendseDownload PDFPatent Trials and Appeals BoardAug 26, 201914329162 - (D) (P.T.A.B. Aug. 26, 2019) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/329,162 07/11/2014 Rajendra D. Pendse 2515.0307 CON 5855 112165 7590 08/26/2019 STATS ChipPAC/PATENT LAW GROUP: Atkins and Associates, P.C. 123 West Chandler Heights Road, Unit 12535 Chandler, AZ 85248 EXAMINER MENZ, LAURA MARY ART UNIT PAPER NUMBER 2813 NOTIFICATION DATE DELIVERY MODE 08/26/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): main@plgaz.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE _________________ ___________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ___________________ ____________ Ex parte RAJENDRA D. PENDSE ____________ Appeal 2018-008750 Application 14/329,162 Technology Center 2800 Before JEFFREY B. ROBERTSON, GEORGIANNA W. BRADEN, and MERRELL C. CASHION, JR., Administrative Patent Judges. ROBERTSON, Administrative Patent Judge. DECISION ON APPEAL1 STATEMENT OF THE CASE Appellant2 appeals under 35 U.S.C. § 134(a) from the Examiner’s Final Rejection of claims 1–13 and 26–37, which constitute all the claims 1 This Decision includes citations to the following documents: Specification filed July 11, 2014 and as amended January 22, 2016 (“Spec.”); Final Office Action mailed October 31, 2017 (“Final Act.”); Appeal Brief filed March 30, 2018 (“Appeal Br.”); Examiner’s Answer mailed July 12, 2018 (“Ans.”); and Reply Brief filed September 13, 2018 (“Reply Br.”). 2 Appellant identifies STATS Chip PAC Pte. Ltd. as the real party in interest. (Appeal Br. 1.) Appeal 2018-008750 Application 14/329,162 2 pending in this application. (Appeal Br. 6–20.) We have jurisdiction pursuant to 35 U.S.C. § 6(b). We AFFIM-IN-PART. THE INVENTION Appellant states the invention relates to semiconductor devices, and in particular to a semiconductor and method of forming high routing density interconnect sites on a substrate. (Spec. ¶ 2.) Claim 1 is representative and reproduced below from the Claims Appendix to the Appeal Brief: 1. A method of making a semiconductor device, comprising: providing a semiconductor component including a contact pad; providing a substrate including a conductive trace; and forming an interconnect structure in contact with the contact pad and an interconnect site of the conductive trace, wherein a width of the interconnect structure across the interconnect site is less than a length of the interconnect structure along the interconnect site, and the width of the interconnect structure is tapered along the length of the interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the interconnect sites. (Appeal Br. 22, (Claims Appendix).) Independent claims 7, 26, and 32 also recite methods of making a semiconductor device with similar limitations with respect to the length and width of the interconnect structure. (Id. at 23, 25–27.) Appeal 2018-008750 Application 14/329,162 3 REJECTIONS3 1. The Examiner rejected claims 1–6 under 35 U.S.C. § 112 (pre- AIA), second paragraph, as being indefinite. (Final Act. 2–3.) 2. The Examiner rejected claims 1, 7, and 32 under 35 U.S.C. § 103(a) as obvious over Benzler et al. (US 6,678,948 B1, issued January 20, 2004, “Benzler”) and Iwasaki et al. (US 6,462,425 B1, issued October 8, 2002, “Iwasaki”). (Final Act. 3–7.) 3. The Examiner rejected claims 1–13 and 26–37 under 35 U.S.C. § 103(a) as obvious over Iwasaki and Benzler. (Final Act. 7–14.) 4. The Examiner rejected claims 5, 11, 26–31, and 35 under 35 U.S.C. § 103(a) as obvious over Iwasaki, Benzler, and Watanabe et al. (US 6,218,281 B1, issued April 17, 2001, “Watanabe”). We limit our discussion to independent claim 1, which is sufficient for disposition of this appeal. Rejection 1 The Examiner determined claims 1–6 are indefinite because the recitation of “the semiconductor die” in the second-to-last line of the claim has insufficient antecedent basis in the claim. (Final Act. 2–3.) 3 We cite to the pre-AIA version of 35 U.S.C. because the effective filing date for the application from which this appeal is taken, based on the filing date of the parent Application, is before the effective date of the AIA legislation of March 16, 2013. Appeal 2018-008750 Application 14/329,162 4 Appellant does not provide argument in response to the Examiner’s rejection and states “Appellant will agree to amend claim 1 accordingly upon resolution of the pending rejections.” (Appeal Br. 7; see Reply Br. 1.) Accordingly, we summarily affirm the Examiner’s rejection of claim 1, and claims 2–6 dependent therefrom. Although the Examiner stated in the Final Action that the antecedent basis problem “precludes examination” (Final Act. 3), the Examiner nevertheless rejected claims 1–6 in view of prior art despite this deficiency. Therefore, we review the prior art rejections of claims 1–6 as applied to the claims by the Examiner. Rejections 2 and 3 ISSUE For Rejection 2, the Examiner found Benzler discloses a method of making a semiconductor device with the steps recited in claim 1, but Benzler fails to teach the width of the interconnect structure is tapered along the length of the interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the interconnect sites. (Final Act. 3–4.) The Examiner found Iwasaki discloses the width of the interconnect structure is tapered along the length of the interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the interconnect sites. (Id. at 4; citing Iwasaki, Fig. 12A reference numbers 22 and 21.) The Examiner determined it would have been obvious to have modified Benzler’s teachings with respect to the interconnect structure as taught by Iwasaki “because one of ordinary skill in Appeal 2018-008750 Application 14/329,162 5 the art understands that solder is a flux and can be modified to fit any desirable shape” and that “[s]hapes are a matter of design choice and can be modified to fit the shape of the underlying pads- and such shapes are taught in the prior art.” (Id. at 4.) For Rejection 3, in applying Iwasaki as the primary reference, the Examiner relied on the same disclosure in Iwasaki as to the width of the interconnect structure being tapered along the length of the interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the interconnect sites. (Id. at 8.) The Examiner found Iwasaki did not disclose “a width of the interconnect structure across the interconnect site is less than a length of the interconnect structure along the interconnect site.” (Id. at 13.) The Examiner found Benzler discloses the width of the interconnect structure across the interconnect site is less than a length of the interconnect structure along the interconnect site. (Id. at 13; citing Benzler, Fig. 10, reference number 24, oval shape, and Fig. 9 (a, b, d–g, i).) The Examiner determined it would have been obvious to modify Iwasaki to have the interconnect structure as taught by Benzler “because shaped bumps are well-known and commonly used in the art” and Benzler’s illustrated shapes of bumps “are also a matter of design choice.” (Id.) Appellant argues, inter alia, the Examiner erred in finding Iwasaki discloses the width of the interconnect structure as tapered along the length of the interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the interconnect sites. (Appeal Br. 10–12; Reply Br. 2–4.) Accordingly, the dispositive issue is: Did Appellant demonstrate reversible error on the part of the Examiner in finding Iwasaki discloses Appeal 2018-008750 Application 14/329,162 6 “width of the interconnect structure is tapered along the length of the interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the interconnect sites,” as recited in claim 1? DISCUSSION Claim 1 As the Examiner makes clear in the Answer, the Examiner relied on Iwasaki for the particular arrangement of the width of the interconnect structure recited in the claims. (Ans. 3, 5.) In particular, the Examiner annotated Figure 12A, reproduced below, to indicate how the interconnect structure (connecting conductor) 13 with portions 21 and 22 was tapered as recited in claim 1. (Ans. 4, Iwasaki Fig. 12A, col. 10, ll. 40–67.) Annotated Figure 12A of Iwasaki, reproduced above, depicts a sectional view of a semiconductor device (Iwasaki, col. 8, ll. 13–14), with annotations made by the Examiner of a line with an arrow pointed upward Appeal 2018-008750 Application 14/329,162 7 vertically in the plane of the page (the y direction) and labeled “Length dimension” and a line with an arrow pointed at portion 22 of connecting conductor 13 labeled “Tapered width.” Initially, we agree with Appellant—the Examiner does not correctly define the length dimension of interconnect structure of Iwasaki as it is defined in claim 1. Claim 1 recites “a length of the interconnect structure along the interconnect site” and recites the interconnect structure is “tapered along the length of the interconnect structure” (emphasis added). Thus, the length referred to with respect to tapering is the length of the interconnect structure along the interconnect site. Appellant presented annotated versions of Figures 23c and 23d of the instant Application, reproduced below, in order to illustrate the length and width recited in claim 1. (Appeal Br. 11.) Annotated Figure 23c, reproduced above, depicts a semiconductor die 324 with a wedge-shaped interconnect structure (bump) 362 bonded to a conductive trace 368 on a substrate 370. (Spec. ¶¶ 24, 98, 99.) Figure 23c is Appeal 2018-008750 Application 14/329,162 8 a companion drawing to Figure 23a, which depicts a “shorter aspect of narrowing taper co-linear with conductive trace 368.” (Spec. ¶ 99.) Appellant has annotated the drawing with an arrow on each side of interconnect structure pointing toward the side closer to where the interconnect structure contacts conductive trace 368, labeling the arrows “WIDTH.” Annotated Figure 23d, reproduced above, depicts a semiconductor die 324 with a wedge-shaped interconnect structure (bump) 362 bonded to a conductive trace 368 on a substrate 370. (Spec. ¶¶ 24, 98, 99.) Figure 23d is a companion drawing to Figure 23b, which is described as “normal” to Figure 23a, and depicts “the longer aspect of the wedge-shaped composite bump 362.” (Spec. ¶ 99.) Appellant has annotated the drawing with an arrow on each side of interconnect structure and labeled “LENGTH.” The express language of claim 1, as understood in light of the Specification, makes clear the direction of the length of the interconnect structure of “along the interconnect site” corresponds to a direction Appeal 2018-008750 Application 14/329,162 9 extending out of the page in Figure 12a of Iwasaki (the z direction) and not vertically in the plane of the page (the y direction) as the Examiner determined. In this regard, we agree with Appellant—Iwasaki does not disclose connecting conductor 13 is tapered along its length, but rather discloses a “circular form factor.” (Appeal Br. 12; see Iwasaki Figures 12B and 12C depicting circular cross sectional views of the structure in Figure 12A; col. 8, ll. 14–16.) Therefore, we reverse the Examiner’s rejections of claims 1 and 7, as well as dependent claims 2–6 and 8–13. Independent claims 26 and 32 contain similar language, and as a result, we reverse the Examiner’s rejections of claims 26 and 32, as well as dependent claims 27–31 and 33– 37. Rejection 4 The Examiner rejected claims 5, 11, 26–31, and 35 over Iwasaki and Benzler, adding Watanabe for the concept of a composite bump. (Final Act. 16.) Thus, Watanabe does not remedy the deficiencies identified above with respect to Iwasaki. Accordingly, we reverse Rejection 4 for similar reasons expressed for Rejections 2 and 3. DECISION We summarily affirm the Examiner’s decision rejecting claims 1–6 under 35 U.S.C. § 112 (pre-AIA), second paragraph, as being indefinite (Rejection 1). We reverse the Examiner’s decision rejecting claims 1–13 and 26–37 as obvious over prior art (Rejections 2–4). Appeal 2018-008750 Application 14/329,162 10 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). 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