QUALCOMM Incorporated

Patent Trials and Appeals BoardApr 20, 2021

2020000634 (P.T.A.B. Apr. 20, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/252,323 08/31/2016 Gregory Michael Wright 161480/1173-360 6117 115309 7590 04/20/2021 W&T/Qualcomm 106 Pinedale Springs Way Cary, NC 27511 EXAMINER GIROUX, GEORGE ART UNIT PAPER NUMBER 2125 NOTIFICATION DATE DELIVERY MODE 04/20/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ocpat_uspto@qualcomm.com patents@wt-ip.com us-docketing@qualcomm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte GREGORY MICHAEL WRIGHT Appeal 2020-000634 Application 15/252,323 Technology Center 2100 Before ADAM J. PYONIN, DAVID J. CUTITTA II, and PHILLIP A. BENNETT, Administrative Patent Judges. CUTITTA, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1–30, which are all the claims pending on appeal. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as QUALCOMM Incorporated. Appeal Brief filed July 2, 2019 (“Appeal Br.”) 3. Appeal 2020-000634 Application 15/252,323 2 CLAIMED SUBJECT MATTER Summary According to Appellant, the claimed subject matter relates to providing for “replay of partially executed instruction blocks in a processor employing a block-atomic execution model.” Spec. ¶ 6.2 “In a block-atomic execution model, a set of instructions (e.g., 128 instructions) is grouped into instruction blocks.” Id. ¶ 4. “A processor operating according to a block- atomic execution model logically fetches, executes, and commits the instruction block 100 as a single entity.” Id. ¶ 5. “A block-atomic execution model has an advantage of reducing the complexity of an out-of-order processor,” but “has a disadvantage of having to execute all instructions in an instruction block before external results are committed,” which makes “debugging more difficult in the presence of a multi-threaded CPU.” Id. ¶¶ 4, 5. Spec. ¶ 6. The claimed partial block replay (PBR) model may “be used to enhance debugging.” Id. ¶ 48. Exemplary Claim Claims 1, 22, 23, and 30 are independent. Independent claim 1, reproduced below with certain dispositive limitations at issue italicized, exemplifies the claimed subject matter: 1. A partial replay controller for controlling execution replay of an instruction block executed in a processor, comprising: 2 In addition to the above-noted Appeal Brief, throughout this Decision we refer to: (1) Appellant’s Specification filed August 31, 2016 (“Spec.”); (2) the Final Office Action (“Final Act.”) mailed January 7, 2019; (3) the Examiner’s Answer (“Ans.”) mailed September 12, 2019; and (5) the Reply Brief filed November 5, 2019 (“Reply Br.”). Appeal 2020-000634 Application 15/252,323 3 a detection circuit configured to set a record/replay state to an active state for an instruction block, in response to detection of an instruction associated with a potential architectural state modification or an occurrence of an exception in the processor; and a record/replay circuit configured to, in response to the record/replay state being an active state for the instruction block: inspect an entry state in a record/replay log file corresponding to a next load/store instruction to be executed in the instruction block to determine if previously produced data is recorded for the next load/store instruction; record produced data of the executed next load/store instruction in the record/replay log file, in response to the previously produced data not being recorded in the record/replay log file for the next load/store instruction; and execute the next load/store instruction using the previously produced data recorded for the next load/store instruction in the record/replay log file, in response to the previously produced data being recorded in the record/replay log file for the next load/store instruction. Appeal Br. 15 (Claims Appendix). REFERENCE AND REJECTIONS The Examiner rejects claims 1–5, 8–19, and 21–30 under 35 U.S.C. § 102(a)(1) as anticipated by Slavenburg et al. (US 5,832,202, issued Nov. 3, 1998) (“Slavenburg”). Final Act. 3–18. The Examiner rejects claims 6, 7, and 20 under 35 U.S.C. § 103 as unpatentable over Slavenburg in view of well-known practices in the art (i.e., Official Notice). Final Act. 19–20. Appeal 2020-000634 Application 15/252,323 4 OPINION We review the appealed rejection for error based upon the issues identified by Appellant and in light of Appellant’s arguments and evidence. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential). Claim 1, in part, recites: a detection circuit configured to set a record/replay state to an active state for an instruction block, in response to detection of an instruction associated with a potential architectural state modification or an occurrence of an exception in the processor; and a record/replay circuit configured to, in response to the record/replay state being an active state for the instruction block: inspect an entry state in a record/replay log file corresponding to a next load/store instruction to be executed in the instruction block to determine if previously produced data is recorded for the next load/store instruction; record produced data of the executed next load/store instruction in the record/replay log file, in response to the previously produced data not being recorded in the record/replay log file for the next load/store instruction. Appeal Br. 15. The Examiner finds Slavenburg discloses the above-recited limitations of claim 1 because, in Slavenburg, “the instruction pipeline and execution are controlled by a global controller . . . where record/replay is controlled by the replay mode signal which sets the active state of record or replay, set by instruction execution, as part of an exception handler setting replay signal REP=1.” Final Act. 21 (citing Slavenburg 5:3–13, 12, 13, 16:24–60, 17:52–18:28, abstract). Appeal 2020-000634 Application 15/252,323 5 Appellant argues that “Slavenburg does not disclose any element corresponding to the ‘record/replay’ circuit that is configured to ‘record produced data’ in response to (i.e., when triggered by) ‘detection of an instruction associated with a potential architectural state modification or an occurrence of an exception in the processor,’ as claim 1 recites.” Appeal Br. 12 (emphasis omitted). According to Appellant, Slavenburg does not disclose “recording data in response to ‘detection of an instruction associated with a potential architectural state modification’ ‘or an occurrence of an exception in the processor,’ as recited by claim 1.” Id. Instead, Slavenburg is “always recording data when not replaying (e.g., replaying caused by replay signal REP=l being set in response to an occurrence of an exception), and the ‘recording data’ mode . . . is not triggered by ‘detection of an instruction associated with a potential architectural state modification’ ‘or an occurrence of an exception,’” as recited in claim 1. Id. (emphasis omitted). In response, the Examiner repeats the finding that “Slavenburg teaches that the record/replay is controlled by the replay mode signal which sets the active state of record/replay, is set by instruction execution, as part of an exception handler setting replay signal REP=1.” Ans. 4 (citing Slavenburg 12, 13, 16:24–60). Appellant persuades us that the Examiner has not shown that Slavenburg initiates recording of produced data “in response to detection of . . . an occurrence of an exception in the processor,” as recited in claim 1. As an initial matter, we agree with the Examiner’s finding that Slavenburg’s record/replay circuit RRC provides for switching between a record mode and a replay mode. Final Act. 8. Slavenburg further discloses that “replay Appeal 2020-000634 Application 15/252,323 6 mode signal REP” causes record/replay circuit RRC to switch from the replay mode to the record mode. See Slavenburg 13:8–12 (“The replay mode signal REP therefore distinguishes a record mode, in which DM.O=DM.O', from a replay mode, in which DM.O=DREP.”). The Examiner, however, does not sufficiently explain how Slavenburg’s RRC circuit switches to a record mode in response to detection of an occurrence of an exception. Instead, the Examiner finds Slavenburg discloses that “the active state of record/replay, is set by instruction execution, as part of an exception handler setting replay signal REP=1.” Ans. 4 (emphasis added). However, the portions of Slavenburg cited by the Examiner (Ans. 4) refer to the REP signal alternatively as a “replay mode signal REP” or a “replay selection signal REP=1” rather than as “an exception handler setting replay signal REP=1;” nor do they otherwise disclose the claimed relationship between a record state and an occurrence of an exception (Slavenburg 13:1–7, 16:24–25). Accordingly, the Examiner does not sufficiently explain how Slavenburg’s switching from a replay mode to a record mode based on replay mode signal REP changing from logic ‘1’ to logic ‘0,’ is in response to the detection of an occurrence of an exception in the processor. Although Slavenburg discloses “an exception detection signal EXDET,” the Examiner has not explained how EXDET is employed to switch the record/replay circuit RRC to data record mode. The Examiner additionally explains that: the claim does not require that the three actions, including recording, all only happen in response to the active ‘record/replay state’. Rather, the claim recites that when the ‘record/replay state’ is active the controller performs the three actions listed. In other words a system, such as that taught by Slavenburg, which is always ‘recording produced data . . . ‘and Appeal 2020-000634 Application 15/252,323 7 then when a record/replay state becomes active, also begins to “inspect an entry state . . .” for recorded data to use to “execute the next load/store using the previously produced data . . .” (and is otherwise still recording if there is no recorded data to reuse/replay). Ans. 3–4 (citing Slavenburg 5:3–13, 12, 13, 16:24–60, 17:52–18:28, abstract). In response, Appellant argues: Any alleged prior art that “is always ‘recording produced data’” (as the Examiner's Answer acknowledges is the case with embodiments according to Slavenburg) cannot properly be said to be doing so “in response to” any specified condition being met. This is because the “recording [of] produced data” will happen regardless of whether the condition is ever met or not. Consequently, interpreting the express language of claim 1 to encompass prior art in which the recording of produced data is always taking place would effectively render superfluous the “in response to” claim language of claim 1. Reply Br. 2. We find Appellant’s argument persuasive because the Examiner’s finding that Slavenburg is “always ‘recording produced data’” necessarily reads out of claim 1 the limitation “set a record/replay state to an active state for an instruction block, in response to . . . occurrence of an exception in the processor.” Ans. 3. “It is highly disfavored to construe terms in a way that renders them void, meaningless, or superfluous.” Wasica Fin. GmbH v. Cont’l Auto. Sys., Inc., 853 F.3d 1272, 1288 n.10 (Fed. Cir. 2017). Thus, given the current record, the Examiner may have shown that Slavenburg discloses a record mode that “record[s] produced data,” but has not shown how Slavenburg discloses recording produced data in response to “an occurrence of an exception” as recited in claim 1. Appeal 2020-000634 Application 15/252,323 8 Accordingly, based on the record before us, the Examiner has not demonstrated that Slavenburg discloses all of the limitations of independent claim 1. Because we agree with at least one of the dispositive arguments advanced by Appellant, we need not reach the merits of Appellant’s other arguments for claim 1. We also do not sustain the anticipation rejection of independent claims 22, 23, and 30 for similar reasons, or the anticipation rejection of claims 2–5, 8–19, 21, and 24–29, which depend from claims 1 and 23. Because the Examiner does not rely on “well-known practices in the art” (Final Act. 19) to cure the deficiency of the anticipation rejection discussed above, we also reverse the obviousness rejection of dependent claims 6, 7, and 20. DECISION SUMMARY In summary: REVERSED Claims Rejected 35 U.S.C. § Reference(s)/ Basis Affirmed Reversed 1–5, 8– 19, 21–30 102(a)(1) Slavenburg 1–5, 8–19, 21–30 6, 7, 20 103 Slavenburg, well-known practices in the art 6, 7, 20 Overall Outcome 1–30