NVIDIA CORPORATION

Patent Trials and Appeals Board

Jul 15, 2020

2019005445 (P.T.A.B. Jul. 15, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/456,805 08/11/2014 Ilyas ELKIN NVDA/13-SC-0653-US 5727
102324 7590 07/15/2020
Artegis Law Group, LLP/NVIDIA
7710 Cherry Park Drive Suite T #104
Houston, TX 77095
EXAMINER
O NEILL, PATRICK
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
07/15/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
jmatthews@artegislaw.com
kcruz@artegislaw.com
sjohnson@artegislaw.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ILYAS ELKIN, GE YANG,
XI ZHANG, and JIANI YU
____________

Appeal 2019-005445
Application 14/456,805
Technology Center 2800
____________

Before MICHAEL P. COLAIANNI, DONNA M. PRAISS, and
MONTÉ T. SQUIRE, Administrative Patent Judges.

PRAISS, Administrative Patent Judge.

DECISION ON APPEAL1
Appellant2 appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 1, 2, 4, 5, 8, 9, 11–20, and 23–25. We have
jurisdiction over this appeal under 35 U.S.C. § 6(b).
We REVERSE.

1 Our Decision refers to the Specification (“Spec.”) filed Aug. 11, 2014, the
Final Office Action dated July 13, 2018 (“Final Act.”), the Advisory Action
dated Sept. 28, 2018 (“Adv. Act.”), Appellant’s Appeal Brief (“Appeal Br.”)
filed Feb. 28, 2019, the Examiner’s Answer (“Ans.”) dated May 10, 2019,
and Appellant’s Reply Brief (“Reply Br.”) filed July 9, 2019.
2 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies NVIDIA CORPORATION as the real
party in interest. Appeal Br. 3.
Appeal 2019-005445
Application 14/456,805

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STATEMENT OF THE CASE
The subject matter on appeal relates to a computer system with a
flip-flop element, and particularly to a low power flip-flop element with
gated clock. Spec. ¶¶ 1, 2. The Specification describes a flip-flop element
as a circuit that has two stable states used to store data that is typically
configured in a master-slave arrangement. Id. ¶¶ 2, 3. The Specification
describes a clock as a periodic signal that is applied to one input of the
flip-flop element to transfer the state of a second, data input signal to the
output on the rising edge of the clock. Id. ¶ 2. According to the
Specification, conventional flip-flop elements clock the input level to the
output regardless of whether the data input has changed from high to low or
not, resulting in numerous junction transitions. Id. ¶ 5. Appellant’s flip-flop
element is said to realize a substantial reduction in system power usage by
reducing the number of transitions and consequent power penalty associated
with the inverted clock. Id. ¶ 56.
Appellant’s Figure 4 below is a conceptual diagram of flip-flop
element 402. Id. ¶¶ 15, 52.

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Figure 4 above depicts clock input 420 of master latch 404, clock
input 430 of slave latch 406, and one input of NAND gate 408 coupled to
clock 412 by flip-flop element 402. Id. ¶ 53. The Specification describes all
clock inversion transitions within master latch 404 and slave latch 406 as
being controlled by gated-clock-not 414 as follows: (1) when
gated-clock-not 414 is at a high logic level, the high input to NAND gate
408 enables NAND gate 408 to produce the inversion of clock 412 at the
output as gated-clock-not 414 transitioning all coupled junctions between the
high and low level with each cycle of clock 412; and (2) when
gated-clock-not 414 is at a low logic level, the low input to NAND gate 408
forces the output of NAND gate 408 to a steady high state, and all transitions
of gated clock-not 414 cease. Id. ¶ 56.
Claim 1, reproduced below from the Claims Appendix to the Appeal
Brief, is illustrative (disputed limitations italicized).
1. A circuit element configured to perform a data capture
operation, the circuit element comprising:
a first latch element that:
receives a first data signal that has a first logic state,
inverts the first logic state to generate a second data
signal that has a first inverted logic state, and
receives a first clock signal;
a first logic element coupled to the first latch element that:
inverts the first clock signal to generate a first inverted
clock signal based on the second data signal, and
transmits the first inverted clock signal to the first latch
element, wherein the first latch element, in
response to the first inverted clock signal, inverts
the first data signal to generate a first inverted data
signal; and
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Application 14/456,805

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a second latch element comprising an input stack that receives a
third data signal that has the first logic state from the first
latch element, wherein the input stack comprises at least
two transistors of the same type.
ANALYSIS
We review the appealed rejections for error based upon the issues
Appellant identifies. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential) (cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed.
Cir. 2011) (“[I]t has long been the Board’s practice to require an applicant to
identify the alleged error in the examiner’s rejections.”)). After considering
the positions of both the Examiner and Appellant, we are persuaded the
Examiner reversibly erred for the reasons set forth in Appellant’s briefs and
discussed below.
The Examiner rejects the claims under 35 U.S.C. § 103 as follows:3
claims 1, 2, 8, 9, 12, 13, 15–20, and 23–25 as unpatentable over Baratam4 in
view of Mastrocola5 and claims 4, 5, 11, and 14 as unpatentable over
Baratam and Mastrocola in further view of Cai.6 Final Act. 2–10.
The Examiner finds Baratam discloses a circuit/flip-flop element as
required by each of independent claims 1, 12, and 17, except Baratam fails
to explicitly disclose an “input stack [comprises/comprising] at least two
transistors of the same type” as recited in each of independent claims 1, 12,
and 17. Id. at 2–6. The Examiner finds Mastrocola teaches replacing an
inverter and transmission gate with a tristate inverter that has an input stack

3 Claims 21 and 22 are objected to as being dependent upon a rejected base
claim. Final Act. 10.
4 US 9,306,545 B2, issued Apr. 5, 2016.
5 US 6,356,132 B1, issued Mar. 12, 2002.
6 US 9,350,325 B2, issued May 24, 2016.
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comprising two transistors of the same type. Id. at 3, 7 (citing Mastrocola
Figs. 3, 4A, 4B, 7:3–40). The Examiner determines it would have been
obvious to replace Baratam’s inverter and transmission gate with
Mastrocola’s tristate inverter because it would have been a simple
substitution of one known element for another to obtain predictable results.
Id. The Examiner elaborates that the tristate inverter would achieve the
same effect of preventing toggling of the component while the gated clock
signal is held at a fixed value. Adv. Act. 3.
Appellant challenges the combination of Baratam with Mastrocola on
the basis that modifying Baratam with Mastrocola’s tristate inverter would
render Baratam’s system inoperable for its intended purpose and/or
fundamentally change its principle of operation. Appeal Br. 13. According
to Appellant, Baratam’s master-slave flip-flop circuit operates in multiple
phases, including where the transmission gate is non-conducting when the
gated clock signal is 0 and the inverted clock signal is 1, whereas
Mastrocola’s ON and ONB signals are complementary signals such that
when the ON signal is asserted, the ONB signal is not asserted. Id. at 14.
Appellant contends that the proposed modification would not result in a
tri-stated circuit, but, instead, the tristatable inverter circuit would produce
an output signal (OUT) when the inverted clock signal (nclk) is 1 and the
gated clock signal (bclk) is 0. Id. (emphasis omitted). According to
Appellant, this would not prevent toggling of the output signal (OUT) when
the gated clock signal (bclk) is held at a fixed, low value because the M1 and
M4 switches would be in an ON state. Id. Appellant argues each of
independent claims 1, 12, and 17 recites substantially similar limitations,
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Application 14/456,805

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therefore the Examiner’s rejections of claims 1, 12, and 17, as well as their
dependent claims, are all flawed for the same reasons. Id. at 15.
The Examiner responds that Appellant misinterprets the combination
of Baratam and Mastrocola because the Examiner does not find
Mastrocola’s ON and ONB signals to be equivalent to clock signals, but,
rather, that Mastrocola’s tristatable inverter may replace Baratam’s inverter
and transmission gate and achieve the same function. Ans. 4 (citing
Mastrocola 7:31–35). The Examiner finds Baratam discloses signal bclk is
connected to the gate of the NIMOS transistor in the transmission gate and
signal nclk is connected to the gate of the PMOS transistor in the
transmission gate, which means the bclk signal would correspond to the ON
signal and the nclk signal would correspond to the ONB signal in
Mastrocola’s Figs. 3–4B (opposite Appellant’s modified Baratam Figure
12). Id. The Examiner finds Baratam discloses as a purpose of its system
reducing the power consumed by the master slave flip-flop by using a gated
clock signal to prevent toggling of clocked components when the gated
clock signal is held at a fixed value and concludes the modification with a
tristable inverter would not render Baratam’s system inoperable for its
intended purpose. Id. at 5 (citing Baratam 1:62–67, 6:34–40).
In the Reply Brief, Appellant contends that the tristatable inverter
circuit of Mastrocola is designed to implement an ON signal and an ONB
signal that are always complements of each other, which would render
Baratam’s system inoperable for its intended purpose. Reply Br. 8.
According to Appellant, Baratam’s bclk signal is at a fixed low value as the
Examiner posits only when the gating control signal has a value of logical 0;
when the gating control signal has a value of logical 1, gated clock signal
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bclk tied to a fixed value (logical 0) would be independent of the input clock
signal CK and inverted clock signal nclk, thus the nclk and bclk signals
would no longer be complements of one another. Id.
Appellant’s arguments are persuasive of harmful error.
We are persuaded by Appellant that the Examiner’s reason for
modifying Baratam with Mastrocola is unsupported by a preponderance of
the evidence in the record. Rather, based on the record cited in this Appeal,
the Examiner’s modification of Baratam appears to be based on improper
hindsight rather than an apparent reason to combine known elements in the
fashion claimed. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 419, 418 (2007).
As Appellant points out (Reply Br. 8; Appeal Br. 14), Mastrocola’s
tristatable inverter circuit is designed for complementary ON and ONB
signals, that is, when the ON signal is asserted, the ONB signal is not
asserted. The Examiner does not adequately address Appellant’s argument
that Mastrocola’s tristable inverter circuit would not have been substitutable
for Baratram’s inverter and transmission gate based on this complementary
signal design. Therefore, the preponderance of the evidence does not
support the Examiner’s determination (Ans. 5) that the modified Baratram
circuit is capable of operating as Baratram intends to prevent toggling of
clocked components when the gated clock signal is held at a fixed value.
In view of the above and for the reasons provided in the Appeal Brief
and the Reply Brief, we reverse the Examiner’s rejection of claim 1.
Because each of the remaining claims is rejected based on the same
combination of Baratram and Mastrocola and Cai does not remedy the
deficiency discussed above, we likewise reverse the rejection of claims 2, 4,
5, 8, 9, 11, 12, 13, 14, 15–20, and 23–25.
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Application 14/456,805

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CONCLUSION
For these reasons and those the Appellant provides, we reverse the
Examiner’s rejections of claims 1, 2, 4, 5, 8, 9, 11–20, and 23–25 under 35
U.S.C. § 103.

DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C.
§ References/Basis Affirmed Reversed
1, 2, 8, 9,
12, 13, 15–
20, 23–25
103 Baratam, Mastrocola
1, 2, 8, 9,
12, 13, 15–
20, 23–25
4, 5, 11, 14 103 Baratam, Mastrocola, Cai 4, 5, 11, 14
Overall
Outcome
1, 2, 4, 5,
8, 9, 11–
20, 23–25

REVERSED