Newport Fab, LLC dba Jazz Semiconductor, Inc.

Patent Trials and Appeals Board

Jun 4, 2021

2020004085 (P.T.A.B. Jun. 4, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/459,488 03/15/2017 Roda Kanawati TSJ-010 (15JAZ0008) 7915
22888 7590 06/04/2021
BEVER HOFFMAN & HARMS, LLP
c/o Carrie Reddick, Office Manager
18486 Spring Valley Drive
Grass Valley, CA 95945
EXAMINER
NGUYEN, CUONG QUANG
ART UNIT PAPER NUMBER
2811
NOTIFICATION DATE DELIVERY MODE
06/04/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
creddick@beverlaw.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
_______________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________
Ex parte RODA KANAWATI
_______________
Appeal 2020-004085
Application 15/459,488
Technology Center 2800
_______________
Before KAREN M. HASTINGS, DEBRA L. DENNETT, and LILAN REN,
Administrative Patent Judges.
DENNETT, Administrative Patent Judge.
DECISION ON APPEAL1
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the
Examiner’s decision to reject claims 1–4, 11–13, and 15–17 of Application
15/459,488. See Final Act. 1; Appeal Br. 6. We have jurisdiction under
35 U.S.C. § 6(b).

1 In our Decision, we refer to the Specification filed Mar. 15, 2017 (“Spec.”)
of Application 15/459,488 (“the ’488Application”); the Final Office Action
dated Apr. 18, 2019 (“Final Act.”); the Appeal Brief filed Nov. 18, 2019
(“Appeal Br.”); the Examiner’s Answer dated Mar. 20, 2020 (“Ans.”); and
the Reply Brief filed May 12, 2020 (“Reply Br.”).
2 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies Newport Fab, LLC dba Jazz Semiconductor, Inc. Appeal Br. 4.
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Application 15/459,488
2
For the reasons set forth below, we AFFIRM IN PART.
BACKGROUND
The subject matter of the ’488 Application relates to radio frequency
(RF) switches including silicon-on-insulator complementary metal-oxide
semiconductor transistors. Spec. ¶ 1. According to the applicant, a RF
switch structure with reduced on-resistance and reduced off-capacitance is
desirable. Spec. ¶ 15. The invention provides a RF switch in which the
thickness of the polysilicon gate is thinner than the typical thickness of a
polysilicon gate associated with the process used to fabricate the device.
Spec. ¶ 16.
Claims 1 and 11 are representative of the ’488 Application’s claims
and are reproduced below from the Claims Appendix of the Appeal Brief.
1. A radio frequency (RF) switch comprising:
a plurality of silicon-on-insulator (SOI) CMOS
transistors, each including a polysilicon gate electrode having a
first thickness and a first length, wherein the first length is at
least about 0.18 microns and defines a length of a channel of
the transistor between a source region and a drain region of the
transistor, and wherein the first thickness is less than 1450
Angstroms, each of the transistors further including dielectric
sidewall spacers formed adjacent to the polysilicon gate
electrode;
a pre-metal dielectric layer located over the plurality of
SOI CMOS transistors; and
contacts extending through the pre-metal dielectric layer
to provide contact to the source region and the drain region of
each of the plurality of the SOI CMOS transistors.

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11. A radio frequency (RF) switch comprising:
a plurality of silicon-on-insulator (SOI) CMOS
transistors fabricated in accordance with a semiconductor
process having a first minimum line width of 0.18 microns,
wherein the semiconductor process conventionally implements
a polysilicon gate layer having a first thickness of about 2000
Angstroms, wherein each of the plurality of SOI CMOS
transistors is fabricated with polysilicon gate electrodes having
a second thickness, less than the first thickness, and wherein
each of the plurality of SOI CMOS transistors includes
dielectric sidewall spacers formed adjacent to the polysilicon
gate electrode; and
an interconnect structure that couples the plurality of SOI
CMOS transistors in series to form the RF switch, wherein the
interconnect structure includes a pre-metal dielectric layer
located over the plurality of SOI CMOS transistors, and
contacts extending through the pre-metal dielectric layer to
provide contact to source and drain regions of the plurality of
the SOI CMOS transistors.
Appeal Br. 18, 19 (Claims App.).
REFERENCES
The Examiner relies on the following references in rejecting the
claims:
Name Reference Date
Kamath et al.
(“Kamath”)
US 2008/0042212 A1 Feb. 21, 2008
Yamazaki et al.
(“Yamazaki ’801”)
US 2012/0164801 A1 June 28, 2012
Yamazaki
(“Yamazaki ’178”)
US 2012/0256178 A1 Oct. 11, 2012
REJECTIONS
The Examiner maintains the following rejections under 35
U.S.C. § 103 as obvious: (1) claims 1–4 over Kamath in view of Yamazaki
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Application 15/459,488
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’801 and Yamazaki ’178; and (2) claims 11–13 and 15–17 over Kamath in
view of Yamazaki ’801, Yamazaki ’178, and Figure 1 of the ’488
Application (Applicant Admitted Prior Art (“AAPA”)). Final Act. 2–6.
DISCUSSION
We review the appealed rejections for error based upon the issues
identified by Appellant and in light of the arguments and evidence produced
thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential)
(cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011))
(“[I]t has long been the Board’s practice to require an applicant to identify
the alleged error in the [E]xaminer’s rejections.”). After considering the
evidence presented in this Appeal and each of Appellant’s arguments, we are
not persuaded that Appellant identifies reversible error in the Examiner’s
rejections of claims 1–4, 11–13, 15, or 16. We, however, reverse the
rejection of claim 17 for the reason discussed below.
Rejection of claims 1–4 as obvious over Kamath, Yamazaki ’801, and
Yamazaki ’178
Appellant argues claims 1–3 as a group. Appeal Br. 9–13. We select
claim 1 as representative of the group. Claims 2 and 3 stand or fall with
claim 1. 37 C.F.R. § 41.37(c)(1)(iv). Below we separately address
Appellant’s arguments regarding claim 4.
Claim 1
Regarding claim 1, the Examiner finds that Kamath discloses a RF
switch a plurality of SOI CMOS transistors, each including a polysilicon
gate electrode having a first thickness and a first length falling within the
requirements of claim 1, each of the transistors further including dielectric
sidewall spacers formed adjacent to the polysilicon gate electrode. Final
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Act. 2–3. The Examiner finds that Yamazaki ’801 and Yamakazi ’178
disclose a SOI CMOS device comprising a pre-metal dielectric layer formed
over a plurality of CMOS transistors, wherein the pre-metal layer has a
thickness of about 4,000 Angstroms and contacts extending through the pre-
metal dielectric layer to provide contact to the source region and drain
region of each of the plurality of SOI CMOS transistors. Id. at 3. The
Examiner finds that it was known in the art that a semiconductor device is
commonly formed as a multi-level structure with more than one device
formed as a stacked arrangement to save the planar space of the substrate
wafer. Ans. 8. The Examiner concludes that it would have been obvious to
one of ordinary skill in the art at the time of invention to form the pre-metal
dielectric layer taught by Yamazaki ’801 and Yamazaki ’178 in order to
separate the CMOS transistors from other devices (Final Act. 3–4), and to
include appropriate source and drain contacts to provide signal or power
transfer between source/drain regions (Ans. 8).
Appellant argues that Kamath teaches that an interlayer dielectric is
only fabricated if the doped dielectric layers are removed. Appeal Br. 11
(citing Kamath ¶¶ 9, 76). According to Appellant, “Kamath teaches away
from forming both the doped dielectric layers and an interlayer dielectric,
because forming both of these structures would undesirably (and
unnecessarily) require additional processing steps.” Id.
Appellant’s argument is not persuasive of reversible error.
When references teach away from the claimed combination, it is
improper to combine them in an obviousness rejection. In re Grasselli, 713
F.2d 731, 743 (Fed. Cir. 1983). However, teaching away requires that a
reference “criticize, discredit, or otherwise discourage the solution claimed”
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by Appellant. In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004).
Appellant relies on the following disclosures in Kamath:
Optionally, the dopant dielectric film can be left in place as an
interlayer dielectric, further eliminating additional dielectric
removal/deposition/patterning steps.
. . .
After printing the interconnect metal, if the doped dielectric is
removed, an interlayer dielectric . . . may be printed to cover
any exposed active areas.
Kamath ¶¶ 9, 76.
Contrary to Appellant’s position, Kamath fails to criticize, discredit,
or discourage doped dielectric layers and an interlayer dielectric. A
“teaching away” requires more than the mere expression an optional path.
See DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 567 F.3d 1314,
1327 (Fed. Cir. 2009) (“A reference does not teach away . . . if it merely
expresses a general preference for an alternative invention but does not
‘criticize, discredit, or otherwise discourage’ investigation into the invention
claimed.”) (internal citation omitted). Disclosed options do not constitute a
teaching away from a broader disclosure. In re Susi, 440 F.2d 442, 446 n.3
(CCPA 1971). “[A]ll of the relevant teachings of the cited references must
be considered in determining what they fairly teach to one having ordinary
skill in the art.” In re Mercier, 515 F.2d 1161, 1165 (CCPA 1975).
Appellant also argues that it would not have been obvious to combine
the teachings of Kamath with those of Yamazaki ’801 and Yamazaki ’178
because the fabrication methods described in Kamath are specific to all-
printed thin film transistors, which may “provide results similar to structures
formed by more conventional approaches, but at a much lower cost and at a
much higher throughput . . . than conventional process technology, and
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reduce the number of processing tools used for manufacturing operational
devices.” Appeal Br. 12 (quoting Kamath ¶ 98).
Kamath’s disclosure of advantages in its printed approach to
source/drain layers in the fabrication of MOS or thin film integrated circuits
does not negate combining Kamath’s structure with structures disclosed by
Yamazaki ’801 and Yamazaki ’178. The Examiner explains that it was
known in the art that a semiconductor device is commonly formed as a
multi-level structure with more than one device formed as a stacked
arrangement to save the planar space of the substrate wafer. Ans. 8.
“Evidence of a motivation to combine prior art references ‘may flow from
the prior art references themselves, the knowledge of one of ordinary skill in
the art, or, in some cases, from the nature of the problem to be solved.’”
Medichem, S.A. v. Rolabo, S.L., 437 F.3d 1157, 1165 (Fed. Cir. 2006)
(quoting Brown & Williamson Tobacco Corp. v. Philip Morris Inc., 229
F.3d 1120, 1125 (Fed.Cir.2000). The Examiner’s explanation of the reasons
a person of ordinary skill in the art would have had to combine the prior art
teachings is sufficient when an allowance is made for “the inferences and
creative steps that a person of ordinary skill in the art would employ.” KSR
Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
A given course of action often has simultaneous advantages and
disadvantages, and this does not necessarily obviate motivation to combine.
See Winner Int’l Royalty Corp. v. Wang, 202 F.3d 1340, 1349 at n. 8 (Fed.
Cir. 2000) (“The fact that the motivating benefit comes at the expense of
another benefit, however, should not nullify its use as a basis to modify the
disclosure of one reference with the teachings of another. Instead, the
benefits, both lost and gained, should be weighed against one another.”).
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The prior art must be considered as a whole for what it teaches. In re
Young, 927 F.2d 588, 591 (Fed. Cir. 1991).
Although the combination of teachings in Kamath, Yamazaki ’801,
and Yamazaki ’178 may have associated costs, the combination provides the
advantage of allowing a stacked structure and a minimized footprint.
We sustain the rejection of claim 1 as obvious over Kamath in view of
Yamazaki ’801 and Yamazaki ’178. For the same reasoning, we sustain the
rejection of claims 2 and 3 as obvious over these references.
Claim 4
Claim 4 depends from claim 1 and recites, “wherein the pre-metal
dielectric layer has a thickness of about 4,000 to 10,000 Angstroms.”
Appeal Br. 18 (Claims App.).
The Examiner rejects claim 4 as obvious over Kamath in view of
Yamazaki ’801 and Yamazaki ’178, finding that Yamazaki ’801’s disclosure
of a pre-metal dielectric layer having a thickness of 4,000 Angstroms meets
the claim limitation. Final Act. 3.
Appellant does not dispute that Yamazaki ’801 discloses a 4,000
Angstrom thickness, but argues that “there is no context to suggest that a
pre-metal dielectric layer of this thickness should be used in combination
with the ‘all-printed thin film transistor’ described by Kamath.” Appeal Br.
13.
This argument is unpersuasive for the reasons given in relation to
claim 1. In addition, Yamazaki ’801 discloses interlayer insulating film 231
is formed at a thickness of 4,000 Angstroms, which falls within the claimed
“thickness of about 4,000 to 10,000 Angstroms.” Yamazaki ’801 ¶ 95.
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We sustain the rejection of claim 4 over Kamath in view of Yamazaki
’801 and Yamazaki ’178.
Rejection of claims 11–13 and 15–17 as obvious over Kamath,
Yamazaki ’801, Yamazaki ’178, and AAPA
Appellant argues claims 11–13, 15, and 16 as a group. Appeal Br.
13–16. We select claim 11, as representative. Claims 12, 13, 15, and 16
stand or fall with claim 11. 37 C.F.R. § 41.37(c)(1)(iv). We address
Appellant’s arguments regarding claim 17 separately below.
Claim 11
The Examiner refers to the discussion of Kamath’s teachings for claim
1 in rejecting claim 11. Final Act. 4. The Examiner finds that Yamazaki
’801 and AAPA teach an interconnect structure that couples the plurality of
SOI CMOS transistors in series to form an RF switch. Id. The Examiner
determines that it would have been obvious to one of ordinary skill in the art
to form an interconnect structure as claimed because such connection is
commonly formed in CMOS structures. Id.
The Examiner finds that claim 11’s limitation “fabricated in
accordance with a semiconductor process having a first minimum line width
of 0.18 microns” is a product-by-process limitation, and does not confer
patentability over a prior art product that is identical or only slightly
different. Id.
As with claim 1, Appellant argues that the “specialized ‘all-printed’
process of Kamath teaches away from the formation of both doped dielectric
layers . . . and a pre-metal dielectric layer, and therefore teaches away from
steps that allow for the formation of both ‘dielectric sidewall spacers’ and a
‘pre-metal dielectric layer’ in the manner recited by claim 11.” Appeal Br.
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14. According to Appellant, therefore it would not have been obvious to one
of ordinary skill in the art to include a pre-metal dielectric layer as disclosed
by Yamazaki ’801, Yamazaki ’178, or AAPA over the doped dielectric
layers of Kamath. Id.
Appellant also argues that the cited references fail to teach or suggest
a structure including “transistors fabricated in accordance with a
semiconductor process having a first minimum line width of 0.18 microns”
and “polysilicon gate electrodes having a second thickness, less than” about
2000 Angstroms as recited in claim 11. Id. at 15.
Appellant’s “teaching away” argument is unpersuasive of reversible
error for the reasons given in relation to claim 1 supra.
Appellant’s argument that the references fail to teach the claimed
structure is also unpersuasive.
“A product-by-process claim is ‘one in which the product is defined at
least in part in terms of the method or process by which it is made.’”
SmthKline Beecham Corp. v. Apotex Corp., 439 F.3d 1312, 1315 (Fed. Cir.
2006) (quoting Bonito Boats, Inc. v. Thunder Craft Boats, Inc., 489 U.S.
141, 158 n. (1989)). A product-by-process claim is limited by and defined
by the process, but determination of patentability is based on the product
itself. In re Thorpe, 777 F.2d 695, 697 (Fed. Cir. 1985) (citations omitted).
“The patentability of a product does not depend on its method of
production.” Id. “If the product in a product-by-process claim is the same
as or obvious from a product of the prior art, the claim is unpatentable even
though the prior product was made by a different process.” Id.
Claim 11’s recitation of “transistors fabricated in accordance with a
semiconductor process having a first minimum line width of 0.18 microns”
describes the process by which a plurality of SOI CMOS transistors is
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fabricated, but it does not describe structure. As a consequence, disclosure
of this process in the prior art is not required in order to show obviousness.
The structure required by claim 11 includes polysilicon gate
electrodes having a second thickness that is less than about 2000 Angstroms.
See Appeal Br. 19 (Claims App.). Kamath discloses a polysilicon gate
having a thickness as low as “about 50 nm” (500 Angstroms), falling within
the thickness required by claim 11. Kamath ¶ 42. For this reason in
combination with the discussion above, the RF switch of claim 11 is not
patentable over the combined prior art references.
We sustain the rejection of claim 11 over Kamath in view of
Yamazaki ’801, Yamazaki ’178, and AAPA. We likewise sustain the
rejection of claims 12, 13, 15, and 16 over the same references.
Claim 17
Claim 17 depends from claim 11 and recites, “wherein polysilicon
gate electrodes fabricated in accordance with the semiconductor process
typically have the first thickness and a first dopant concentration, and
wherein the polysilicon gate electrodes having the second thickness have a
second dopant concentration, greater than the first dopant concentration.”
Appeal Br. 20 (Claims App.).
The Examiner finds that the portion of claim 17 quoted above is a
product-by-process limitation. Final Act. 5.
Appellant argues that the cited reference fail to teach “the polysilicon
gate electrodes having the second thickness have a second dopant
concentration, greater than the first dopant concentration.” Appeal Br. 16.
We agree with the Examiner that “wherein polysilicon gate electrodes
fabricated in accordance with the semiconductor process typically have the
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first thickness and a first dopant concentration” describes a process, not
structure per se, yet it does mean the gate electrodes have a “first dopant
concentration” relative to the later recited second dopant concentration. The
remainder of claim 17 describes structure such that the second dopant
concentration is greater than the first dopant concentration. The Examiner
makes no findings regarding dopant concentrations in the cited references.
See generally Final Act., Ans. Therefore, we do not sustain the rejection of
claim 17 as obvious over Kamath in view of Yamazaki ’801, Yamazaki
’178, and AAPA.
DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1–4 103 Kamath, Yamazaki ’801, Yamazaki ’178 1–4
11–13, 15–
17 103
Kamath, Yamazaki
’801, Yamazaki ’178,
AAPA
11–13, 15,
16 17
Overall
Outcome
1–4, 11–
13, 15, 16 17
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED IN PART