Nam Wook KANG

Patent Trials and Appeals Board

Aug 23, 2021

2020001517 (P.T.A.B. Aug. 23, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/958,050 12/03/2015 Nam Wook KANG 8947-000960-US 1416
30593 7590 08/23/2021
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON, VA 20195
EXAMINER
CHAN, TRACY C
ART UNIT PAPER NUMBER
2137
NOTIFICATION DATE DELIVERY MODE
08/23/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
dcmailroom@hdp.com
jcastellano@hdp.com
jhill@hdp.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte NAM WOOK KANG

Appeal 2020-001517
Application 14/958,050
Technology Center 2100

Before CARL W. WHITEHEAD JR., DAVID M. KOHUT, and
IRVIN E. BRANCH, Administrative Patent Judges.

KOHUT, Administrative Patent Judge.

DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–10. We have jurisdiction under
35 U.S.C. § 6(b).
We AFFIRM.

1 We use “Appellant” to reference the applicant as defined in
37 C.F.R. § 1.42. Appellant identifies the real party in interest as
“Samsung Electronics Co[.], Ltd.” Appeal Br. 1.
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STATEMENT OF THE CASE
Appellant’s Invention
Appellant’s invention relates to “erasing memory cells of [a]
nonvolatile memory . . . and prohibiting an erase of the erased memory cells
for a critical time.” Spec., abst. Claim 1, reproduced below, is illustrative of
argued subject matter.
1. An operation method of a storage device including a
nonvolatile memory and a memory controller configured to
control the nonvolatile memory, the operation method
comprising:
erasing memory cells of the nonvolatile memory using the
memory controller; and
prohibiting an erase of the erased memory cells for a critical
time after the erasing the memory cells using the memory
controller.
Appeal Br. 17.
Rejections
Claim 8 stands rejected under 35 U.S.C. § 112(b) as being indefinite.
Final Act. 5–6.
Claims 1–7, 9, and 10 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Kitsunai (US 2010/0049907 A1; Feb. 25, 2010) and
Suzuki (US 2013/0051144 A1; Feb. 28, 2013). Final Act. 7–12.
INDEFINITENESS
Claim 8 is rejected as indefinite. Final Act. 5–6. We are unpersuaded
of error in this rejection of claim 8. We therefore sustain the Examiner’s
decision to reject claim 8.
Claim 8 depends from claim 1 and recites in relevant part: “mapping
at least a part of physical addresses of each of the erased memory blocks to a
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logical address of an out-of-range area of a logical address of the storage
device.” Appeal Br. 18.
The Examiner finds: “Claim 8 recites ‘a logical address of an
out-of-range area of a logical address’. It is unclear what is the meaning and
scope of ‘out-of-range area of a logical address’[.] Particularly, it is unclear
what relationship there is between the two “logical address[es’.]”
Final Act. 6 (emphasis omitted).
Appellant contends:
The features of claim 8 read on operation S120 in FIG. 1,
operation S210 in FIG. 5, the out-of-range area OORA in
paragraph [0129] and F1G. 13 of the present application.
Because FIG. 13 and [0129] of the present application provide
guidance on what is meant by the “out-of-range area” in claim
8, Appellants respectfully submits that the scope of claim 8 . . .
would be clear to one of ordinary skill in the art.
Appeal Br. 7.
The Examiner responds that “neither Fig. 13 nor [the] specification
[0129] discloses the meaning and scope of ‘a logical address of an
out-of-range area of a logical address of the storage device’[.]” Ans. 4.
Appellant replies:
The out-of-range area OORA in the second table T2 [of
FIG. 13] is for logical addresses (e.g., LPN 17) that [are] not
part of the user area UA. Paragraph [0129] . . . explains the
logical page address LPN of the out-of-range area OORA may
be a virtual address that is not discriminate as a storage space of
the storage device 100.
Reply Br. 3.
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We are unpersuaded of error. We agree with the Examiner that
Appellant does not show what is meant by the claimed “logical address of an
out-of-range area of a logical address” (Ans. 4 (quoted above)). We explain
with reference to Appellant’s Figure 13, which illustrates a table mapping
logical addresses of memory to physical addresses of memory (Spec. ¶ 129).
Figure 13 illustrates a table mapping logical
addresses of memory to physical addresses of
memory. Spec. ¶ 129.
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Generally speaking, and as shown, the invention “sets at least one of
pages of [a] memory block BLK2 as a virtual valid so that the . . . memory
block BLK2 is erase-prohibited” and does so by “add[ing] an OORA
(out-of-range area) to the . . . table T2 as shown.” Id. Specifically, the
logical address LPN17 is mapped to physical address PPN5 of memory
block BLK2, LPN17 is also set as an out-of-range area OORA, and these
actions set the entire memory block BLK2 as “virtual valid” so that its erase
is prohibited.2 Id.
However, we do not find that these teachings clarify what is
specifically meant by the “logical address of an . . . area of . . . a logical
address” recited with the claimed “logical address of an out-of-range area of
a logical address.” Further, the Specification does not disclose a logical
block-address, much less one representing multiple logical page-addresses.
We have considered whether the “logical address of an . . . area of
. . . a logical address” recites a logical address that is an out-of-range logical
address. And, we have considered whether this language recites a logical
address representing an OORA of the storage device (i.e., an out-of-range
physical address). We find that both interpretations are conceivable and
comport with Appellant’s Figure 13 and its written description
(Spec. ¶ 129). This reflects the principle problem; the claim language is
incomprehensibly open to interpretation. See In re Katz Interactive Call
Processing Patent Litig., 639 F.3d 1303 (Fed. Cir. 2011) (“[If] the public is
left to guess [what] the claims cover . . . [, they ] fail to fulfill the ‘public

2 This is a means whereby the invention can perform the claimed
“prohibiting an erase of the erased memory cells for a critical time after
the[ir] erasing” (claim 1).
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notice function’ of 35 U.S.C. § 112 ¶ 2.”); In re Miller, 441 F.2d 689, 693
(CCPA 1971) (describing indefiniteness as an issue of whether “those
skilled in the art will be . . . uncertain[ of] what subject matter falls within
the scope of the claims”). Further, even assuming (arguendo) the language
is comprehensible, it would be amenable to the multiple above
interpretations. See Ex Parte Miyazaki, 89 USPQ2d 1207, 1211 (BPAI
2008) (precedential) (“[I]f a claim is amenable to two or more plausible
claim constructions, the USPTO is justified in . . . holding the claim . . . as
indefinite.”).
OBVIOUSNESS
Claims 1–7, 9, and 10 are rejected as obvious. Final Act. 7–12.
We select claim 1 as representative. 37 C.F.R. § 41.37(c)(1)(iv). We are
unpersuaded of error in this rejection of claim 1 and therefore sustain the
Examiner’s decision to reject claims 1–7, 9, and 10 under 35 U.S.C. § 103.
Appellant’s first dispute (contentions presented infra) is whether the
applied prior art—that is, the Examiner’s proposed Kitsunai-Suzuki
combination—achieves the claimed “prohibiting an erase of the erased
memory cells for a critical time after the erasing the memory cells.”
Appeal Br. 13; Reply Br. 7, 10.
In determining the combination achieves the claimed prohibiting step,
the Examiner presents three determinations. First, the Examiner finds
Kitsunai teaches to maximize the duration between the prior erase and next
erase of a non-volatile memory block (herein “block”) but does not
“explicitly” teach a critical duration. Final Act. 7; Ans. 6–10; see also
Kitsunai ¶ 139. Second, the Examiner finds that Suzuki teaches a minimum
duration between a prior erase-program of a block (i.e., a substantially
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coincident erasing and then programming of the block) and a next
erase-program of the block. Final Act. 8; Ans. 6–11; see also Suzuki ¶¶ 113,
115, 129. Third, the Examiner concludes that these teachings suggest a
device that implements a minimum duration between erases of a block and
thereby achieves the claimed “prohibiting an erase of the erased memory
cells for a critical time after the erasing the memory cells.” Final Act. 8;
Ans. 9.
Appellant contends Kitsunai “does not mention erase-erase intervals
that correspond with the [claimed] ‘prohibiting an erase of the erased
memory cells for a critical time after the erasing the memory cells[.]”
Reply Br. 10; see also Appeal Br. 13 (“For clarification, . . . the erase-erase
interval corresponds to the [claimed ‘prohibiting[.’”]). Appellant further
contends: “[Kitsunai] merely teach[es] erasing [of] the oldest block[. By
this] teaching[,] erasing a memory block and then erasing the same memory
block without any programming is [only] possible[.]” Reply Br. 7; see also
id. (“It is well known . . . that successively erasing memory cells may be
necessary in some circumstances such as bad checking, erase retry, user’s
instruction, etc.”). We are unpersuaded of Examiner error.
Appellant has not provided sufficient evidence or reasoning that “the
erased memory cells” of the claimed “prohibiting an erase of the erased
memory cells for a critical time after the erasing the memory cells” are
presently-erased cells, i.e., of an erase-erase interval as opposed to cells that
were erased and then programmed. Reply Br. 7, 10; see also In re Jung,
637 F.3d 1356, 1365 (Fed. Cir. 2011) (affirming because appellant “merely
argued that the claims differed from [the prior art], and chose not to proffer a
serious explanation of this difference.”); SmithKline Beecham Corp. v.
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Apotex Corp., 439 F.3d 1312, 1320 (Fed. Cir. 2006) (“[I]ssues adverted to in
a perfunctory manner, unaccompanied by some effort at developed
argumentation, are deemed waived.”). Per claim drafting convention, “the
erased memory cells” might merely reference the cells of claim 1’s
prior-recited erasing step (i.e., as a matter of antecedent basis). Thus,
Appellant has not persuaded us that the claimed prohibiting step recites an
“erase-erase interval” (Reply Br. 10; Appeal Br. 13).
Additionally, Appellant contends an artisan would have understood
that consecutive erases of a block can occur with or without intervening
programming (i.e., writing) of the block. Reply Br. 7, 10. Appellant further
contends that Kitsunai’s teaching to maximize the duration between
consecutive erases is therefore not a teaching to maximize the duration
between consecutive erases without intervening programming. Id. We
disagree with Appellant. These contentions are inconsistent because a
teaching for all species of an element (consecutive erases with and without
intervening programming) would be understood as a teaching for each
particular species of the element (consecutive erases without intervening
programming). See PAR Pharm., Inc. v. TWI Pharms., Inc., 773 F.3d 1186,
1196 (Fed. Cir. 2014) (“[T]o . . . establish the [inherent] existence of a claim
limitation . . . in an obviousness analysis[,] the limitation at issue necessarily
must be present[] or the natural result of the combination of elements[.]”).
Appellant also contends “Kitsunai does not prevent the erase of
memory cells for a critical time after the last erase.” Appeal Br. 10. We
disagree with Appellant..
First, Appellant mischaracterizes the rejection as reading the claimed
“critical time” on Kitsunai alone. As discussed, the Examiner reads the
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claimed “critical time” on the Kitsunai-Suzuki combination. See supra 6–7
(explaining the combination); see also In re Merck & Co., Inc., 800 F.2d
1091, 1097 (Fed. Cir. 1986) (“Non-obviousness cannot be established by
attacking references individually where the rejection is based upon the
teachings of a combination of references.”).
Second, contrary to Appellant’s argument, Kitsunai teaches the
claimed “critical time.” Namely, Kitsunai teaches that the duration between
erases should be at least “the sufficiently long recovery time of the [given
memory block’s] retention characteristic.” Kitsunai ¶ 126.
Appellant also contends: “Suzuki merely teaches lengthening [a]
program-erase interval and shortening [an] erase-program interval using a
threshold. [An artisan] cannot recognize [from these teachings] whether [an]
erase-erase interval [of the Kitsunai-Suzuki combination] should be
lengthened, shortened or maintained[.]” Appeal Br. 13. We disagree with
Appellant.
First, Appellant is contending but has not provided sufficient evidence
or reasoning that the claimed prohibiting step recites an erase-erase interval.
We add, in this regard, that adding Suzuki’s critical duration for a
program-erase interval to the Kitsunai-Suzuki combination achieves the
claimed prohibiting step if not reciting an erase-erase interval. It would do
so because the erasing immediately precedes the programming (Suzuki
¶¶ 13, 115; see also Ans. 10–11) and, thus, the program-erase interval
constitutes a duration between the prior erase (that immediately preceded the
occurred programming of the program-erase interval) and the next erase
(that is the erasing of the next program-erase interval).
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Second, even assuming (arguendo) the claimed prohibiting step
recited an erase-erase interval, Kitsunai teaches a critical duration between
an erase-erase of a block. Kitsunai ¶ 126. Namely, Kitsunai teaches that the
duration between erases should be at least “the sufficiently long recovery
time of the [given memory block’s] retention characteristic.” Id.
Claim 2
Claim 2 depends from claim 1 and adds:
wherein the prohibiting the erase of the erased memory cells for
the critical time includes:
setting at least some memory cells among the erased
memory cells to store valid data;
managing a table to indicate that the valid data is stored
in the at least some memory cells; and
releasing the at least some memory cells after the critical
time has elapsed.
Appeal Br. 17.
Though Appellant addresses claim 2 separately (Appeal Br. 13–14),
Appellant contends without sufficient evidence or explanation: Kitsunai’s
paragraph 112 and Figure 10 “describe[] a block allocation process that
generates a load concentration degree” and not the claimed “setting some
memory cells among the erased memory cells to store valid data” (Appeal
Br. 14); and Suzuki’s paragraph 193 “describes a reclaim process” and not
the claimed “releasing some memory cells after a critical time has elapsed”
(id. at 15). These contentions do not constitute developed arguments for
separate patentability of claim 2. See Jung, 637 F.3d at 1365 (described
supra); SmithKline, 439 F.3d at 1320 (described supra).
Further, Appellant’s contentions fail to sufficiently address the
Examiner’s specific findings. Final Act. 8–9; Ans. 13. The Examiner does
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not merely state that Kitsunai’s paragraph 112 and Figure 10 teach the
claimed setting step and that Suzuki’s paragraph 193 teaches the claimed
releasings step. Id. The Examiner rather provides additional citations, a
description of the relied-upon teachings, and an explanation of how the
teachings of Kitsunai and Suzuki applied in-combination for each of the
above two claim steps. Id.
We are, accordingly, unpersuaded of error. We therefore sustain the
Examiner’s decision to reject claim 2.
DECISION SUMMARY
Claims
Rejected
35 U.S.C.
§

Reference(s)/Basis Affirmed Reversed
8 112(b) Indefiniteness 8
1–7, 9, 10 103 Kitsunai, Suzuki 1–7, 9, 10
Overall
Outcome 1–10

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this Appeal may be extended under 37 C.F.R. § 1.136(a). See
37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED