Monterey Research, LLC

Patent Trials and Appeals BoardDec 8, 2021

IPR2020-01017 (P.T.A.B. Dec. 8, 2021)

Trials@uspto.gov Paper 36 571-272-7822 Date: December 08, 2021 UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD ADVANCED MICRO DEVICES, INC., Petitioner, v. MONTEREY RESEARCH, LLC, Patent Owner. IPR2020-01017 Patent 6,961,807 B1 Before KRISTEN L. DROESCH, JOHN F. HORVATH, and JASON W. MELVIN, Administrative Patent Judges. DROESCH, Administrative Patent Judge. JUDGMENT Final Written Decision Determining All Challenged Claims Unpatentable 35 U.S.C. § 318(a) Dismissing Motion to Exclude 37 C.F.R. § 42.64(c) IPR2020-01017 Patent 6,961,807 B1 2 I. INTRODUCTION We have authority to hear this inter partes review under 35 U.S.C. § 6, and this Final Written Decision is issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73 (2019). For the reasons that follow, we determine that Petitioner establishes by the preponderance of the evidence that claims 1–5 and 7–17 (“challenged claims”) of U.S. Patent No. 6,961,807 B1 (Ex. 1001, “’807 Patent”) are unpatentable. A. Procedural History Advanced Micro Devices, Inc. (“Petitioner”) filed a Petition (Paper 2, “Pet.”) requesting an inter partes review of claims 1–5 and 7–17 of the ’807 Patent. Monterey Research, LLC (“Patent Owner”) timely filed a Preliminary Response. Paper 8 (“Prelim. Resp.”). Pursuant to 35 U.S.C. § 314, we instituted trial on December 14, 2020, as to all of the challenged claims of the ’807 Patent (Paper 10, “Institution Decision” or “Dec.”). After institution of trial, Patent Owner filed a Response (Paper 16, “PO Resp.”), to which Petitioner filed a Reply (Paper 20, “Pet. Reply”), to which Patent Owner filed a Sur-reply (Paper 26, “PO Sur-reply”). Petitioner filed a Motion to Exclude Evidence (Paper 28, “Mot.”) to which Patent Owner filed an Opposition (Paper 29, “Opp.”), to which Petitioner filed a Reply (Paper 30, “Reply Opp.”). Petitioner relies on a Declaration of David H. Albonesi, Ph.D. (Ex. 1003) to support its Petition. Patent Owner relies on a Declaration of Michael C. Brogioli, Ph.D (Ex. 2003) to support its Patent Owner Response. IPR2020-01017 Patent 6,961,807 B1 3 Dr. Albonesi and Dr. Brogioli were cross-examined during trial, and transcripts of Dr. Albonesi’s deposition (Ex. 2005) and Dr. Brogioli’s deposition (Ex. 1020) are included in the record. Oral argument was held on September 16, 2021. A transcript of the oral argument is included in the record. Paper 34 (“Tr.”). B. Related Matters The parties indicate the ’807 Patent is the subject of litigation in Monterey Research, LLC v. Advanced Micro Devices Inc., Case No. 1:19- cv-02149-NIQA–LAS (D. Del.). See Pet. 81; Paper 5, 1. C. The ’807 Patent (Ex. 1001) The ’807 Patent relates to an integrated circuit device and method that includes a microprocessor, a multi-purpose memory coupled with the microprocessor, a cache controller, and a first and second memory port. See Ex. 1001, code (57), 1:66–2:3. “[T]he first memory port is provided for coupling a first external memory device with the cache controller, and the second memory port is provided for coupling a second external memory device with the multipurpose memory.” Id. at code (57), 2:3–7; 3:55–58. “[T]he first memory port may be adapted to be coupled with a Flash ROM [(read-only memory)], and the second memory port may be adapted to be coupled with an EEPROM [(electrically erasable programmable read-only memory)].” Id. at code (57), 2:8–10. The multipurpose memory has at least two different operating modes. See id. at 2:13–21, 3:38–43. In a first operating mode, the multipurpose memory caches instructions previously loaded from the Flash ROM coupled with the first memory port. See id. at 2:13–17, 3:62–67, 4:47–50, Figs. 2–3. In a second operating mode, the IPR2020-01017 Patent 6,961,807 B1 4 multipurpose memory stores program instructions copied from an EEPROM coupled with the second memory port during initialization. See id. at 2:17– 23, 4:3–10, 5:26–29, Figs. 4A–4B, 5. D. Illustrative Claim Claims 1, 7, and 13 are independent and claims 2–5, 7–12, and 14–17 depend therefrom, respectively. Claim 1 is illustrative and reproduced below: 1. An integrated circuit device, comprising: a microprocessor, a multipurpose memory coupled with the microprocessor; a cache controller; a first memory port for coupling a first external memory device with said cache controller; and a second memory port for coupling a second external memory device with said multipurpose memory; wherein the multipurpose memory has a first operating mode for dynamically storing as a cache memory portions of a program obtained from the first external memory device for execution by the microprocessor under control of the cache controller, and the multipurpose memory has a second operating mode for storing an entire program obtained from the second external memory device to be run by the microprocessor. IPR2020-01017 Patent 6,961,807 B1 5 E. Asserted Challenges to Patentability and Asserted Prior Art Petitioner asserts the following challenges to the patentability of claims 1–5 and 7–17: Claim(s) Challenged 35 U.S.C. § Reference(s)/Basis 1–4, 7–17 1031 Saulsbury2, Cullison3 1–4, 7–17 103 Kumar4, Cullison 5 103 Saulsbury, Cullison, Gupta5 5 103 Kumar, Cullison, Gupta II. ANALYSIS A. Claim Construction The Board applies the same claim construction standard as that applied in federal courts. See 37 C.F.R. § 42.100(b). The claim construction standard used in a civil action under 35 U.S.C. § 282(b) is generally referred to as the Phillips standard. See Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). Under the Phillips standard, “words of a claim ‘are generally given their ordinary and customary meaning.’” Phillips, 415 F.3d at 1312 (quoting Vitrionics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996)). The parties do not provide explicit claim constructions for any claim term or phrase. See Pet. 10; PO Resp. 12. As demonstrated in the analysis 1 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284 (2011), amended 35 U.S.C. § 103 effective March 16, 2013. Because the ’807 Patent has an effective filing date prior to the effective date of the applicable AIA amendment, we refer to the pre-AIA versions of § 103. 2 Ex. 1004, US 2002/0087821A1, published July 4, 2002 (“Saulsbury”). 3 Ex. 1005, US 5,155,833 A, issued Oct. 13, 1992 (“Cullison”). 4 Ex. 1006, US 5,970,069 A, issued Oct. 19, 1999 (“Kumar”). 5 Ex. 1007, US 5,996,083 A, issued Nov. 30, 1999 (“Gupta”). IPR2020-01017 Patent 6,961,807 B1 6 below, we need not expressly construe any claim terms or phrases. See Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co. Ltd., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (“[W]e need only construe terms ‘that are in controversy, and only to the extent necessary to resolve the controversy.’” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))). B. Principles of Law A claim is unpatentable under 35 U.S.C. § 103 if the differences between the claimed subject matter and the prior art are such that the subject matter, as a whole, would have been obvious at the time the invention was made to a person having ordinary skill in the art to which the subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The question of obviousness is resolved on the basis of underlying factual determinations, including: (1) the scope and content of the prior art; (2) any differences between the claimed subject matter and the prior art; (3) the level of skill in the art; and (4) if in evidence, so-called secondary considerations. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).6 C. Level of Ordinary Skill in the Art Petitioner asserts: [a] person of ordinary skill in the art (“POSITA”) of the ’807 patent would have been a person with a bachelor’s degree in electrical or computer engineering, computer science, applied physics, or a related field, and at least two years of experience in design, development, and/or testing of integrated circuits, 6 Patent Owner does not present evidence of secondary considerations. See generally PO Resp. IPR2020-01017 Patent 6,961,807 B1 7 computer systems, or memory circuits, or the equivalent, with additional education substituting for experience and vice versa. Pet. 10 (citing Ex. 1003 ¶¶ 22–25). Patent Owner adopts Petitioner’s definition of a person of ordinary skill in the art. See PO Resp. 12. We adopt Petitioner’s definition of a person of ordinary skill in the art as it is consistent with the evidence of the level of ordinary skill in the art provided by the prior art references. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In re Oelrich, 579 F.2d 86, 91 (CCPA 1978). D. Challenges to Patentability 1. Challenge to Claims 1–4 and 7–17 over Saulsbury and Cullison a. Overview of Saulsbury (Ex. 1004) Saulsbury is directed to a “processor chip having a processing core and memory fabricated on the same silicon die.” Ex. 1004 ¶ 2. The memory can act as either physical memory or cache memory. See id. IPR2020-01017 Patent 6,961,807 B1 8 Figure 1 of Saulsbury is reproduced below. Figure 1 depicts a block diagram of processor chip 10 “having the processor logic and memory on the same integrated circuit.” Ex. 1004 ¶¶ 11, 17. Processor chip 10 comprises processor core 12, plurality of memory banks 14 (shown as dynamic random access memory (DRAM) Banks), memory controller 20, distributed shared memory (DSM) controller 22 (shown as DSM Engines), external memory interface 24 (shown as External DRAM Interface), high-speed input/output (I/O) link 26 (shown as S- Connect), boot interface 28, and diagnostic interface 30. See id. ¶ 17. Memory controller 20 is connected between and communicates with processor core 12 and memory banks 14. See id. ¶ 20. Memory controller 20 handles I/O requests to memory banks 14 from processor core 12 and other processors and I/O devices. See id. DSM controller 22 is connected to memory controller 20 and is configured to receive I/O requests IPR2020-01017 Patent 6,961,807 B1 9 and data messages from off-chip devices and route the requests and messages to memory controller 20 for access to memory banks 14. See id. Processor chip 10 includes external memory interface 24 connected to memory controller 20 and configured to communicate memory I/O requests from memory controller 20 to external memory. See id. ¶¶ 22, 77. Processor chip 10 also includes boot interface 28 connected to processor core 12. See id. ¶ 22. Boot interface 28 comprises an interface to a boot programmable read-only memory (PROM) holding a system bootstrap program and is configured to receive a bootstrap program for cold booting processor core 12 when needed. See id. ¶¶ 22, 78. b. Overview of Cullison (Ex. 1005) Cullison discloses a master-slave multiprocessor system. See Ex. 1005, code (57), 2:17–20. IPR2020-01017 Patent 6,961,807 B1 10 Figure 1 of Cullison is reproduced below. Figure 1 depicts a block diagram of a master-slave multiprocessor system. See Ex. 1005, 2:10–12, 2:17. The multiprocessor system includes master processor 120 and a duplicate slave processor 110. See id. at 2:20–25. Slave processor 110 is connected to an I/O slot of system bus 100. See id. at 2:25–27. Main on-line memory 109 and I/O subsystem 108, such as a disk, are connected to other slots of system bus 100. See id. at 2:27–30. System bus 100 includes address bus 101, data bus 102, board select lines 103, and system reset line 104. See id. at 2:33–35. Slave IPR2020-01017 Patent 6,961,807 B1 11 processor 110 includes control status register (CSR) 115 connected to one line of board select lines 103, reset line 104, data lines 142, address lines 141, reset request line 144, bus request line 146, and CACHEON line 148. See id. at 2:49–55. Reset request line 144 and bus request line 146 connect CSR 115 with central processing unit/memory management unit (CPU/MMU) 111. See id. at 2:56–57. Slave processor 110 includes static random access memory (SRAM) array 119 connected to address lines 141 and data lines 142. See id. at 2:58–61. SRAM array 119 is controlled by cache controller 117 through read and write (RW) strobe line 149. See id. at 2:61–62. Cache controller 117 is divided into two control portions 131, 132, each active at different times and each of which causes SRAM array 119 to operate in a different mode. See id. at 2:65–68. “Control portion 132 causes array 119 to operate in conventional cache memory mode, as a virtual address-and-data cache memory for buffering information passing between CPU/MMU 111 and main memory 109.” Id. at 2:68–3:4. “Control portion 131 causes array 119 to operate in ‘diagnostic’ mode, wherein individual locations of array 119 may be addressed, and read or written.” Id. at 3:10–13. CSR 115 selects, via CACHEON line 148, one of control portions 131 or 132 to be active, thereby selecting the operating mode of SRAM array 119. See id. at 3:18–21. When the system is powered-up or is reinitialized, master processor 120 pulses or momentarily asserts SYSTEM RESET line 104. See Ex. 1005, 3:25–31. Following assertion of SYSTEM RESET line 104, master processor 102 retrieves a boot program for initializing CPU/MMU 111 from either main memory 109 or secondary memory (i.e., disk) of I/O subsystem 108, and stores the program in SRAM 119. See id. at 3:45–50. IPR2020-01017 Patent 6,961,807 B1 12 Following reset, initialization of CPU/MMU 111 occurs by executing the boot program stored at a single address in the SRAM array 119. See id. at 4:22–43. c. Analysis of Claim 1 (1) An integrated circuit device, comprising: a microprocessor; a multipurpose memory coupled with the microprocessor; a cache controller; Petitioner contends that Saulsbury teaches “[a]n integrated circuit device, comprising: a microprocessor, a multipurpose memory coupled with the microprocessor, a cache controller,” as recited in claim 1, based on Saulsbury’s disclosure of processor chip 10 comprising processor core 12, on-chip DRAM memory 14 coupled with processor core 12, and memory controller 20/DSM controller 22. See Pet. 16–18 (reproducing Ex. 1004, Fig. 1; quoting Ex. 1004 ¶¶ 17, 20 67, 68, 69, 70; citing Ex. 1004, code (57), ¶¶ 5, 6, 8, 74; Ex. 1003 ¶¶ 45–47). Petitioner also contends that Cullison teaches this limitation based on Cullison’s disclosure of slave processor 110 comprising CPU/MMU 111, SRAM 119 coupled with CPU/MMU 111 and cache controller 117. See id. at 18–19 (reproducing Ex. 1005, Fig. 1; quoting Ex. 1005, 1:41–64, 2:36–48, 2:58–62; citing Ex. 1005, 2:18–32, 5:9–12; Ex. 1003 ¶ 48). Patent Owner does not dispute Petitioner’s assertions addressing these limitations of claim 1. See generally PO Resp. Nonetheless, the burden remains on Petitioner to demonstrate unpatentability. See Dynamic Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015). IPR2020-01017 Patent 6,961,807 B1 13 Based on the entire trial record, we determine Petitioner has shown by a preponderance of the evidence that Saulsbury and Cullison teach “[a]n integrated circuit device, comprising: a microprocessor; a multipurpose memory coupled with the microprocessor; a cache controller,” as recited in claim 1. (2) a first memory port for coupling a first external memory device with said cache controller; and Petitioner contends that Saulsbury teaches “a first memory port for coupling a first external memory device with said cache controller,” as recited in claim 1, based on Saulsbury’s disclosure of external memory interface 24 for coupling external memory with memory controller 20/DSM controller 22. See Pet. 20–21 (reproducing Ex. 1004, Fig. 1; quoting Ex. 1004 ¶¶ 22, 77; citing Ex. 1004 ¶¶ 69–70; Ex. 1003 ¶ 50). Petitioner also contends that Cullison teaches this limitation based on Cullison’s disclosure of coupling main memory 109 with cache control unit 117. See id. at 21 (quoting Ex. 1005, 2:63–3:21; Ex. 1003 ¶¶ 51–52). Patent Owner does not dispute Petitioner’s assertions addressing this limitation. See generally PO Resp. In any event, the burden remains on Petitioner to demonstrate unpatentability. See Dynamic Drinkware, 800 F.3d at 1378. Based on the entire trial record, we determine Petitioner has shown by a preponderance of the evidence that Saulsbury and Cullison teach “a first memory port for coupling a first external memory device with said cache controller,” as recited in claim 1. IPR2020-01017 Patent 6,961,807 B1 14 (3) wherein the multipurpose memory has a first operating mode for dynamically storing as a cache memory portions of a program obtained from the first external memory device for execution by the microprocessor under control of the cache controller, Petitioner asserts that Saulsbury teaches “the multipurpose memory has a first operating mode for dynamically storing as a cache memory portions of a program obtained from the first external memory device for execution by the microprocessor under control of the cache controller,” as recited in claim 1. Pet. 23 (citing Ex. 1003 ¶¶ 58–62); see id. at 23–26. Petitioner’s assertion is based on Saulsbury’s disclosure that memory bank 14 operates in two modes, including a cache memory mode under the control of memory controller 20/DSM controller 22. See id. at 23–24 (quoting Ex. 1004 ¶¶ 5, 8, 67, 68, 70, 77; citing Ex. 1004 ¶¶ 20 22, 69, 74; Ex. 1003 ¶ 58; incorporating by reference Pet. 16–19). Petitioner contends that Saulsbury’s memory bank 14 can be configured as a second-level cache memory that dynamically stores portions of a program by caching program instructions. See id. at 24 (citing Ex. 1004 ¶¶ 22, 24–26, 69, 70; Ex. 1005, 1:11–23, 1:48–55; Ex. 1003 ¶ 59). The cache controller would then direct memory requests from the microprocessor to memory bank 14 if the requested instructions/data are cached there. Id. Petitioner also asserts that Cullison teaches this limitation based on Cullison’s disclosure of using SRAM 119 with two modes, including a first cache memory mode for dynamically storing portions of program instructions obtained from main memory 109 for execution by CPU/MMU 11 in cache memory under control of cache controller 117. See id. at 24–25 (quoting Ex. 1005, 1:40–64, 2:63–3:4; citing Ex. 1005, 1:11–23, 1:47–57, 2:58–62, 4:58–68; Ex. 1003 ¶¶ 60–61). IPR2020-01017 Patent 6,961,807 B1 15 Patent Owner does not dispute Petitioner’s assertions addressing this limitation of claim 1. See generally PO Resp. Nonetheless, the burden remains on Petitioner to demonstrate unpatentability. See Dynamic Drinkware, 800 F.3d at 1378. Based on the entire trial record, we determine Petitioner has shown by a preponderance of the evidence that Saulsbury and Cullison teach “wherein the multipurpose memory has a first operating mode for dynamically storing as a cache memory portions of a program obtained from the first external memory device for execution by the microprocessor under control of the cache controller,” as recited in claim 1. (4) a second memory port for coupling a second external memory device with said multipurpose memory; (5) and the multipurpose memory has a second operating mode for storing an entire program obtained from the second external memory device to be run by the microprocessor. Petitioner contends that the combination of Saulsbury and Cullison teaches “a second memory port for coupling a second external memory device with said multipurpose memory,” as recited in claim 1. See Pet. 21 (citing Ex. 1003 ¶¶ 54–57). Petitioner asserts that Saulsbury teaches boot interface 28 for coupling a second external memory device (e.g., a PROM). See id. (quoting Ex. 1004 ¶ 78; citing Ex. 1004 ¶¶ 17, 22, Fig. 1). Petitioner acknowledges that Saulsbury does not teach that the second external memory device is coupled DRAM memory 14. See id. at 21–22. Petitioner asserts that Cullison teaches coupling secondary memory 108, such as disk storage, with SRAM 119 to retrieve a boot program from the secondary memory and store it in SRAM 119 during bootup. See id. at 22 (quoting Ex. 1005, 3:45–51, 2:18–32; citing Ex. 1005, code (57), 1:41–57, Fig. 1; IPR2020-01017 Patent 6,961,807 B1 16 Ex. 1003 ¶ 55). According to Petitioner, “[t]hus, Saulsbury and Cullison both teach loading a boot program from a secondary memory device including PROM and disks.” Id. Petitioner contends that it would have been obvious to one of ordinary skill in the art to modify Saulsbury in view of Cullison by coupling Saulsbury’s multi-purpose memory to Saulsbury’s second external memory device through the boot interface, and storing an entire boot program in the multi-purpose memory. See Pet. 22–23 (incorporating by reference Pet. 10– 16, 26–28). In particular, Petitioner asserts that the modification would enable the entire boot program to be quickly and efficiently loaded during the boot process, and would provide several advantages, including improved cost, speed, and performance. See id. (citing Ex. 1005, 3:45–4:20; Ex. 1003 ¶ 56; incorporating by reference Pet. 10–16). More specifically, Petitioner contends that the combination offers the following advantages: (1) lowers cost because Cullison teaches that having two memory modes lowers cost and reduces circuit area; (2) increases speed because Saulsbury teaches reducing latency by fabricating both the central processing functionality and memory on a single chip; and (3) increases the range of potential applications and improves performance, allowing for configuration in low and high performance applications. See id. at 13 (citing Ex. 1005, 1:64–2:3; Ex. 1004 ¶ 3). According to Petitioner, “[c]onfiguring Saulsbury’s multipurpose on-chip memory for storing a boot program, as taught by Cullison, would have increased performance without significantly increasing cost.” Id. (citing Ex. 1003 ¶ 33). Petitioner further asserts that a person of ordinary skill in the art: IPR2020-01017 Patent 6,961,807 B1 17 would have been motivated to combine Cullison’s teachings regarding cache memory mode–including the cache controller– with Saulsbury’s teachings of using on-chip DRAM as cache memory because it reduces memory latency, and to add a configuration for booting up, in which the onboard DRAM is configured to store the entire boot program, loaded from the external memory device through the boot interface to the onboard multipurpose memory, as Cullison teaches. . . . This would have been advantageous for applications where the boot program is too large to fit in the processor core’s level 1 cache, which was typically in the lower kB [(kilobyte)] range, whereas Saulsbury’s on-chip DRAM would have been orders of magnitude larger and more than sufficient to store typical boot programs. Pet. 12 (citing Ex. 1005, 3:45–4:20; Ex. 1004 ¶¶ 22, 78; Ex. 1003 ¶¶ 32–34). According to Petitioner, a person of ordinary skill in the art: would have been motivated to apply Cullison’s teaching of storing the boot program in multipurpose memory to take advantage of faster RAM access speed and improve bootup times without requiring extra memory. When only portions of the boot program are stored in the instruction cache, the processor may stall while waiting for subsequent portions to be retrieved from slower external memory. Pet. 12–13 (citing Ex. 1003 ¶ 35). Petitioner also asserts that the combination amounts “to using a known technique (e.g., using memory in cache and boot modes) to improve similar devices (e.g., processor devices) in the same way (e.g., with a multipurpose onboard memory). . . . to yield predictable results (e.g., a memory that operates as a cache, in cache mode, and to store a boot program, in boot mode).” Pet. 16 (citing Ex. 1003 ¶ 42; KSR, 550 U.S. at 416–417). Petitioner contends that a person of ordinary skill in the art “would have had a reasonable expectation of success when combining IPR2020-01017 Patent 6,961,807 B1 18 Saulsbury and Cullison given the similarities in their teachings and given that multipurpose on-chip memory, cache memory, boot memory, SRAM, DRAM, cache controllers, and memory ports were well-known, conventional components for processors and integrated circuits.” Id. at 15 (citing Ex. 1003 ¶ 40). Petitioner further asserts that it would have been within the level of ordinary skill in the art to apply Cullison’s teachings to Saulsbury’s multipurpose DRAM despite any differences between SRAM and DRAM memory types and further would have been capable of applying Cullison’s teachings to uniprocessor systems. See id. at 15–16 (citing Ex. 1003 ¶¶ 40–41). Petitioner further asserts that the combination of Saulsbury and Cullison teaches “the multipurpose memory has a second operating mode for storing an entire program obtained from the second external memory device to be run by the microprocessor,” as recited in claim 1. Pet. 26 (citing Ex. 1003 ¶¶ 63–66; incorporating by reference Pet. 10–16); see id. at 26–28. More specifically, Petitioner asserts that Cullison teaches SRAM 119 has two modes of operation, including a boot memory mode for storing an entire boot program obtained from I/O subsystem 108 to be run by CPU/MMU 111. See id. at 27 (quoting Ex. 1005, 1:40–64 3:45–51, 4:8–43; citing Ex. 1005, 3:32–4:7, 5:9–12, Fig. 2; Ex. 1003 ¶ 63; incorporating by reference Pet. 10–16). Petitioner incorporates by reference its reasons for combining the teachings of Saulsbury and Cullison, discussed immediately above addressing the limitation “a second memory port for coupling a second external memory device with said multipurpose memory.” See id. at 27–28 (citing Ex. 1004 ¶¶ 17, 22, 78, Fig. 1; Ex. 1003 ¶¶ 64–65; incorporating by reference Pet. 10–16, 21–23). IPR2020-01017 Patent 6,961,807 B1 19 Patent Owner contends that a person of ordinary skill in the art would not have been motivated to combine Saulsbury and Cullison because “the ’807 Patent promotes a flexible integrated circuit that can be connected to different external memories for use in systems with differing memory requirements,” and “Saulsbury and Cullison are directed to different goals.” PO Resp. 24–25 (citing Ex. 2003 ¶ 109); see id. at 38–39 (similar argument, quoting Ex. 1001, 3:43–45; citing Ex. 2003 ¶ 130). Patent Owner contends that Saulsbury and Cullison teach away from the goals of the ’807 Patent. See id. at 38 (quoting ActiveVideo Networks, Inc. v. Verizon Comm’ns, Inc., 694 F.3d 1312, 1328 (Fed. Cir. 2012); citing Ex. 2003 ¶¶ 130–131). Patent Owner contends that both Saulsbury and Cullison teach away from accessing external memories because “Saulsbury is directed to avoiding ‘processing latencies that occur from accessing memory on separate memory chips,’” and “Cullison is directed to ‘eliminating extra memory devices,’ so as to ‘lower system cost and reduce circuit board area occupied by memory devices.’” Id. at 39 (quoting Ex. 1004 ¶ 3; Ex. 1005 2:1–3; citing Ex. 2003 ¶ 131); see also id. at 25 (similar arguments, citing Ex. 2003 ¶ 109), 49–50 (similar argument, citing Ex. 1004 ¶ 3; Ex. 1005, 2:1–3; Ex. 2003 ¶ 152). According to Patent Owner, “Saulsbury and Cullison, in the context of the understanding of the art in August 2002 would have discouraged a [person of ordinary skill in the art] from making the combinations and modifications necessary to reach [Petitioner’s] proposed combination.” Id. at 25 (citing Ex. 2003 ¶ 109). Patent Owner also argues that a person of ordinary skill in the art “in August 2002 would not have found it obvious to apply Cullison’s teachings to Saulsbury to achieve the ‘second operating mode’ limitation of IPR2020-01017 Patent 6,961,807 B1 20 the challenged claims . . . because the references teach away from each other.” Id. at 46–47 (citing Ex. 2003 ¶ 149). We do not agree with Patent Owner’s arguments because any differences in the teachings of the references do not necessarily constitute a teaching away from the claimed invention. “Under the proper legal standard, a reference will teach away when it suggests that the developments flowing from its disclosures are unlikely to produce the objective of the applicant’s invention.” Syntex (U.S.A.) LLC v. Apotex, Inc., 407 F.3d 1371, 1380 (Fed. Cir. 2005) (citing In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994)). “A reference does not teach away, however, if it . . . does not ‘criticize, discredit, or otherwise discourage’ investigation into the invention claimed.” DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 567 F.3d 1314, 1327 (Fed. Cir. 2009) (quoting In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004)). We also do not agree with Patent Owner’s contentions that Saulsbury and Cullison teach away from and do not meet the ’807 Patent’s goal of providing greater flexibility. “In determining whether the subject matter of a patent claim is obvious, neither the particular motivation nor the avowed purpose of the patentee controls.” KSR, 550 U.S. at 419 (finding that the Court of Appeals for the Federal Circuit erred by holding that courts and patent examiners should only look to the problem the patentee was trying to solve). Patent Owner further argues that a person of ordinary skill in the art working in August 2002 would not have been motivated to combine Saulsbury and Cullison, because substantial modifications would have been necessary to configure Saulsbury’s multipurpose on-chip DRAM to store a boot program during bootup and then act as a cache memory at other times. IPR2020-01017 Patent 6,961,807 B1 21 See PO Resp. 25 (quoting Ex. 1003 ¶ 32; citing Ex. 2003 ¶¶ 109, 111); see also id. at 46–47 (arguing that a person of ordinary skill in the art “in August 2002 would not have found it obvious to apply Cullison’s teachings to achieve the ‘second operating mode’ limitation of the challenged claims because the combination would require numerous significant modifications,” citing Ex. 2003 ¶ 149). According to Patent Owner, the “modifications . . . would defeat the purpose of the Saulsbury disclosure.” Id. at 25 (citing Ex. 1003 ¶ 32, Ex. 2003 ¶ 111). More specifically, Patent Owner contends that Saulsbury is not missing a boot procedure that would require a person of ordinary skill in that art to search for additional references like Cullison. See id. at 26. According to Patent Owner, “Saulsbury already discloses a boot procedure, which does not involve storing a boot program in Saulsbury’s on- chip DRAM,” and instead “discloses loading a ‘bootstrap program [] into an instruction cache in the processing core via the boot interface.’” Id. (quoting Ex. 1003 ¶ 34; citing Ex. 1004 ¶¶ 22, 78; Ex. 2003 ¶ 112); see PO Sur- reply 7 (similar argument, citing Ex. 1003 ¶ 34; Ex. 1004 ¶¶ 22, 78; Ex. 2003 ¶ 112; PO Resp. 26–27). Patent Owner further points out that the only path from Saulsbury’s boot interface 28 is directly into processor core 12. See PO Resp. 26–27 (reproducing Ex. 1004, Fig. 1 (with annotations); citing Ex. 2003 ¶ 112); see PO Sur-reply 7–8 (similar argument, reproducing Ex. 1004, Fig. 1 (with annotations); citing PO Resp. 27). Patent Owner contends that the combination ignores Saulsbury’s straightforward boot procedure that involves “simply loading the bootstrap program directly from the programmable read-only memory (PROM) through boot interface 28 directly into the instruction cache in processor IPR2020-01017 Patent 6,961,807 B1 22 unit 12 for execution.” PO Resp. 28 (citing Ex. 1003 ¶ 34; Ex. 1004 ¶ 78; Ex. 2003 ¶ 113). According to Patent Owner, Petitioner proposes modifying Saulsbury in a way never intended and contradicting the very purpose of Saulsbury—bypassing the processing core 12 instruction cache, and having the bootstrap program travel through boot interface 28, through memory controller 20 into DRAM memory 14, and then back through memory controller 20 for execution by processing core 12. PO Resp. 28; see id. at 29 (reproducing Ex. 1004, Fig. 1 (annotations added)). In the Reply, Petitioner contends that the proposed combination does not bypass Saulsbury’s instruction cache, and that Saulsbury teaches using the instruction cache together with the DRAM. See Pet. Reply 8, 11–12 (quoting Ex. 1020, 70:3–15; citing Ex. 1004 ¶ 39, Figs. 1, 3; Ex. 1020, 63:23–64:13). Petitioner contends that the combination “does not change Saulsbury’s CPU core, which executes using an instruction cache as was typical for CPUs at the time.” Id. at 10–11 (quoting Ex. 1020, 72:14–74:4; citing Ex. 1020, 54:17–55:13, 67:10–68:12, 70:16–72:2). According to Petitioner, “[t]he combination does not alter [Saulsbury’s] architecture, which is consistent with the typical memory hierarchy, where higher layers are faster and lower layers are larger but slower.” Id. at 11 (reproducing Ex. 1025, 2 (illustration of simplified computer memory hierarchy); quoting Ex. 1020, 62:18–63:22; citing Ex. 1020, 58:4–24, 59:11–25, 60:2–62:2; 62:18–63:22). According to Petitioner, the patentability challenge “combines the teachings in a conventional manner: for boot programs too large to fit in the processor’s instruction cache, load the program into the multipurpose memory, as Cullison teaches. . . . This takes advantage of faster DRAM access speed, as compared to PROM, to improve bootup IPR2020-01017 Patent 6,961,807 B1 23 times.” Id. at 9 (citing Pet. 12–13); see also id. at 10 (similar argument, citing Pet. 12; Ex. 1020, 57:16–24); see also id. at 12 (arguing the true comparison looks to DRAM access time compared with off-chip ROM). Petitioner contends that loading programs into memory, commonly DRAM, was the typical approach for executing programs, and also because access to non-volatile storage, such as hard disks or ROM, provide orders of magnitude slower access. See id. at 9 (quoting Ex. 1021 § 2.6; Ex. 1018, 10; Ex. 1019, 3, 4–5; Ex. 1022, 3, 4; citing Ex. 1018, 3; Ex. 1020, 56:4–17, 105:21–106:10). Petitioner asserts that Patent Owner’s witness, Dr. Brogioli, “agrees that running programs out of memory . . . is faster than loading programs off non-volatile storage such as PROM or hard disks.” Id. at 10 (quoting Ex. 1020, 90:13–91:21, 93:21–94:12, 100:9–19; citing Ex. 1020, 98:5–100:8). We do not agree with Patent Owner’s arguments that a person of ordinary skill in the art would not have combined the teachings of Saulsbury and Cullison because substantial modifications would have been necessary, and would defeat the purpose of Saulsbury. As an initial matter, we agree with Petitioner that the proposed combination of Saulsbury and Cullison would not result in bypassing Saulsbury’s processor core and instruction cache. To the extent that Patent Owner argues that modifying Saulsbury to include storing the boot program in DRAM would defeated the purpose of Saulsbury we do not agree because, in either case –whether the boot program is stored in cache or stored in DRAM and cache––Saulsbury’s purpose of reducing latency caused by the distance between a processor and an external memory can be met. To the extent that Patent Owner argues that there must be an identified deficiency in the prior art (i.e., a missing boot IPR2020-01017 Patent 6,961,807 B1 24 procedure) in order to motivate a person of ordinary skill in the art to look to consider the teachings of additional references, we also do not agree. Patent Owner does not direct us to persuasive authority to support its position regarding a deficiency in the prior art. Instead, the Supreme Court instructs that it is often necessary “to look to interrelated teachings of multiple patents; the effects of demands known to the design community or present in the marketplace; and the background knowledge possessed by a person having ordinary skill in the art, all in order to determine whether there was an apparent reason to combine.” KSR, 550 U.S. at 418. Patent Owner also argues that the combination of Saulsbury and Cullison rests on impermissible hindsight because boot programs in August 2002 were only on the order of a few kilobytes and a person or ordinary skill in the art would not have been motivated to execute the boot procedure from DRAM because boot programs were typically executed by instruction caches from external non-volatile memory. See PO Resp. 29–30 (quoting Ex. 2005, 149:25–150:8; citing Ex. 2003 ¶ 114). In Reply, Petitioner asserts that an instruction cache, at the time, was on the order of a few kilobytes and typical boot programs were orders of magnitude larger, typically hundreds of kilobytes for PCs by the 1990s and larger by 2002. See Pet. Reply 18–19 (quoting Ex. 2006; Ex. 1014, Table 1; Ex. 1015, 2; Ex. 1016, 2; Ex. 1017, 1; Ex. 1020, 68:13–69:15; citing Ex. 1006 Fig. 3, 8:65; Ex. 1020, 79:7–12, 195:18–196:20, 197:8–200:4, 202:11–203:10, 203:23–205:13; 207:8– 208:12). Petitioner also argues that Patent Owner does not cite sufficient support for its argument that boot programs were “only on the order of a few kilobytes” in 2002. See id. at 19 (citing PO Resp. 29). More specifically, Petitioner contends that Exhibit 2008, cited by Patent Owner does not IPR2020-01017 Patent 6,961,807 B1 25 describe the size of boot programs, but at best describes an exemplary master boot record (MBR). See id. (quoting Ex. 2008, 3; citing Ex. 2008, 4; Ex. 1020, 191:15–192:5). In the Sur-reply, Patent Owner further contends that nowhere does Saulsbury state that its boot program was too large for the instruction cache. See PO Sur-reply 14–15. According to Patent Owner, Saulsbury’s disclosures “teach[] a [person of ordinary skill in the art] that Saulsbury’s instruction cache can store the entire boot program.” Id. at 15 (citing Ex. 1004 ¶ 78). Patent Owner further contends that Petitioner’s reliance on extrinsic documents to support its contention that a person of ordinary skill in the art would have modified Saulsbury to accommodate larger boot programs demonstrates that the combination rests on impermissible hindsight. See id. According to Patent Owner, “even if a larger boot program was stored in Saulsbury’s PROM, a [person of ordinary skill in the art] would have simply understood to appropriately size Saulsbury’s instruction cache to the bootstrap program and maintain Saulsbury’s simple boot process, not complicate the boot process as [Petitioner] has.” Id. We do not agree with Patent Owner’s arguments. To the extent that Patent Owner asserts that a prior art reference must identify a problem (i.e., a boot program too large for the instruction cache) in order to provide a reason to combine it with the teachings of additional references, we do not agree. The Supreme Court instructs: “[w]hen a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or a different one. If a person of ordinary skill can implement a predictable variation, § 103 likely bars its patentability.” KSR, 550 U.S. at 417. In addition, the preponderance of the evidence IPR2020-01017 Patent 6,961,807 B1 26 supports Petitioner’s position that, in 2002, cache memory was on the order of a few kilobytes and boot programs were on the order of hundreds of kilobytes. See Ex. 1006, Fig. 3, 6:26–27, 8:63–65; Ex. 1014, 2, 25 (Table 1); Ex. 1015, 2; Ex. 1016, 2–3; Ex. 1017, 1; Ex. 1020, 68:13–69:15. We cannot agree with Patent Owner’s contention and Dr. Brogioli’s testimony that boot programs in 2002 were “only on the order of a few kilobytes” because Dr. Brogioli’s testimony is not supported by a sufficient underlying factual basis, and, thus, is entitled to little weight. See Ex. 2003 ¶ 114; Ex. 2008, 1; 37 C.F.R. § 42.65(a) (“Expert testimony that does not disclose the underlying facts or data on which the opinion is based is entitled to little or no weight.”). Also unsupported by a sufficient underlying factual basis is Patent Owner’s contention that a person or ordinary skill in the art would not have been motivated to execute the boot procedure from DRAM because boot programs were typically executed by instruction caches from external non-volatile memory, not DRAM, as Dr. Abonesis admits. See PO Resp. 29–30 (quoting Ex. 2005, 149:25–150:8; citing Ex. 2003 ¶ 114). Dr. Albonesi’s deposition testimony, cited by Patent Owner, does not address typical execution of boot programs. See Ex. 2005, 149:25–150:8. Instead, Dr. Albonesi testifies that, in the case when a system is shut down and the power is removed, restarting the system would involve executing a boot procedure through an external, non-volatile memory. See id. at 148:7– 151:20. We also are not swayed by Patent Owner’s following unsupported attorney arguments that: (1) Saulsbury’s disclosures teach a person of ordinary skill in the art that Saulsbury’s instruction cache can store the entire boot program; and (2) should a larger boot program be stored in Saulsbury’s PROM, a person of ordinary skill in the art would have simply understood to IPR2020-01017 Patent 6,961,807 B1 27 appropriately size Saulsbury’s instruction cache to the boot program and maintain Saulsbury’s simple boot process. Argument of counsel cannot take the place of objective evidence. See Gemtron Corp. v. Saint-Gobain Corp., 572 F.3d 1371, 1380 (Fed. Cir. 2009) (unsworn attorney argument is not evidence). Patent Owner also argues that the combination would not have been obvious because “changing Saulsbury’s processor chip 10 to provide a path from boot interface 28 through DSM controller 22 and memory controller 20 and DRAM memory 14 would increase costs, increase latency, and reduce performance––exactly the opposite of Saulsbury’s goals.” PO Resp. 27–28 (citing Ex. 2003 ¶ 113); see PO Sur-reply 7 (similar argument). Specific to reducing performance, Patent Owner argues that a person of ordinary skill in the art “would understand that executing the boot program directly from the DRAM 14 would be slower than (and defeat the purpose of) executing the boot program from the instruction cache––which in August 2002 was designed to operate at much faster clock rates than DRAM banks.” PO Resp. 31 (citing Ex. 2003 ¶ 116); see id. at 28–29 (reproducing Ex. 1004, Fig. 1 (with annotations)). Patent Owner also contends that the combination of Saulsbury and Cullison would increase the latency for executing the boot program because it “would increase, not decrease, the distance between Saulsbury’s processing core 12 and the memory containing a bootstrap program by having the DRAM memory 14 store the program instead of the instruction cache already present in processing core 12.” Id. at 37 (citing Ex. 2003 ¶ 128); see id. (arguing an increase in latency for executing the boot program would destroy Saulsbury’s purpose of transferring data at a much faster rate than between a processor and off-chip memory, citing IPR2020-01017 Patent 6,961,807 B1 28 Ex. 1004 ¶ 65; Ex. 2003 ¶ 128,), 40 (arguing the combination would increase the distance the bootstrap program must travel before execution by the processing core, citing Ex. 1004 ¶ 3; Ex. 2003 ¶ 134; incorporating by reference PO Resp. 25–33,), 50 (arguing the proposed combination would increase the distance between the processing core 12 and memory containing the bootstrap program, increase the latency for executing the boot program, and destroy one of Saulsbury’s key objectives, quoting Ex. 1004 ¶ 65; citing Ex. 2005:162:25–163:21; Ex. 2003 ¶¶ 152–153). We do not agree with Patent Owner’s arguments because they misstate Petitioner’s proposed combination. As pointed out by Petitioner, the combination of Saulsbury and Cullison does not eliminate or bypass Saulsbury’s CPU instruction cache in favor of DRAM, but instead uses the cache and DRAM together. See Pet. Reply 12 (quoting Ex. 1020, 70:3–15; citing Ex. 1004 ¶ 39, Figs. 1, 3; Ex. 1020, 63:23–64:13); see also Pet. 12–13 (asserting that “[w]hen only portions of the boot program are stored in the instruction cache, the processor may stall while waiting for subsequent portions to be retrieved from slower external memory”). We also concur with Petitioner’s observation that the applicable comparison should be between DRAM access time compared with off-chip ROM access time. See Pet. Reply 12. Also directed to its argument that Petitioner’s combination would have resulted in increased latency and decreased performance (see PO Resp. 33–35; PO Sur-reply 9–13), Patent Owner asserts that the Petition “does not propose removing or replacing the PROM storing Saulsbury’s bootstrap program.” PO Resp. 34 (citing Ex. 2005, 156:25–157:10, 162:16– 23; Ex. 2003 ¶ 121); see also id. at 37–38 (similar argument, citing IPR2020-01017 Patent 6,961,807 B1 29 Ex. 2005, 156:25–157:10, 162:16–23; Ex. 2003 ¶ 128). Patent Owner asserts that Petitioner’s witness, Dr. Albonesi, acknowledges that the PROM storing Saulsbury’s bootstrap program and other non-volatile memories “were often slower than RAM.” See id. at 33–34 (quoting Ex. 1003 ¶ 35; citing Ex. 2005, 161:4–12; Ex. 2003 ¶ 121). According to Patent Owner, “even in the Saulsbury and Cullison combination, the system would still have to access the PROM––and accept the slower access speed and reduced latency involved with accessing the PROM––in order to load the bootstrap program into the DRAM memory 14 before booting the processing core 12.” Id. at 34 (citing Ex. 2005, 161:4–12; Ex. 2003 ¶ 121); see PO Sur-reply 9 (similar argument). Patent Owner also contends that the combination would have decreased performance because the combination would have required involvement by the memory controller 20, but “memory controllers in August 2002 were far less powerful and processed and provided data much slower than CPUs or CPU instruction caches.” PO Resp. 34–35 (citing Ex. 1003 ¶ 35; Ex. 2003 ¶¶ 122–123); PO Sur-reply 12 (similar argument). According to Patent Owner, “[r]equiring Saulsbury’s memory controller 20 to arbitrate the boot procedure would have slowed [Petitioner]’s combination to the speed of the memory controller, far slower than the speed of the CPU.” PO Resp. at 35 (citing Ex. 2003 ¶ 123); see PO Sur-reply 12–13 (similar arguments). In Reply, Petitioner reiterates that the patentability challenge “combines the teachings in a conventional manner: for boot programs too large to fit in the processor’s instruction cache, load the program into the multipurpose memory, as Cullison teaches. . . . This takes advantage of faster DRAM access speed, as compared to PROM, to improve bootup IPR2020-01017 Patent 6,961,807 B1 30 times.” See Pet. Reply 9 (citing Pet. 12–13); see also id. at 10 (similar argument, citing Pet. 12; Ex. 1020, 57:16–24), 12 (similar argument). Petitioner contends that loading programs into memory, commonly DRAM, was the typical approach for executing programs, and also because access to non-volatile storage, such as hard disks or ROM, provide orders of magnitude slower access. See id. at 9 (quoting Ex. 1021 § 2.6; Ex. 1018, 10; Ex. 1019, 3, 4–5; Ex. 1022, 3, 4; citing Ex. 1018, 3; Ex. 1020, 56:4–17, 105:21–106:10). According to Petitioner, “Dr. Brogioli agrees that running programs out of memory . . . is faster than loading programs off non-volatile storage such as PROM or hard disks.” Id. at 10 (quoting Ex. 1020, 90:13– 91:21, 93:21–94:12, 100:9–19; citing Ex. 1020, 98:5–100:8). Petitioner also contends that accessing the PROM to retrieve the boot program “is true for all programs, which are stored in slower non-volatile storage (e.g., ROM or hard drives) and then loaded into memory.” Id. at 13 (citing PO Resp. 37– 38). According to Petitioner, “Dr. Brogioli[,] admits[] the typical practice is to run programs from memory (e.g., DRAM) instead of running them straight out of non-volatile storage.” Id. (quoting Ex. 1020, 100:18–19; citing Ex. 1018, 3, 10; Ex. 1019, 4–5; Ex. 1020, 90:13–93:15, 95:10–96:5, 98:5–100:19). Petitioner asserts that running programs from memory “improves performance for subsequent access because it is faster to access portions of programs stored in faster memory, like cache or DRAM, as compared to slower storage like PROM or hard drives.” Id. at 13–14 (citing Ex. 1020, 72:14–74:4, 91:22–93:15, 100:9–19). According to Petitioner, “temporal and spatial locality cause portions of programs to be accessed repeatedly within a time window (e.g., due to program loops) and therefore subsequent reads to a faster memory––such as cache or DRAM––will reduce IPR2020-01017 Patent 6,961,807 B1 31 latency even if the first read operation loads the data from a slower memory.” Id. at 14 (citing Ex. 1020, 43:15–45:14, 72:14–74:4). Patent Owner contends that Petitioner’s arguments “oversimplify Saulsbury’s modified boot process and focus only on one step––accessing DRAM.” PO Sur-reply 9 (emphasis omitted). Patent Owner asserts that Petitioner ignores that when a computing system is shut down and power is removed, a volatile memory such as a DRAM would lose its contents, including a boot program, necessitating re-loading the boot program back in the DRAM every time the computer has to be initialized. See id. (citing Ex. 2005, 149:25–150:18, 151:10–20, 152:2–8). Patent Owner contends that the combination of Saulsbury and Cullison would lead to an undesirable decrease in performance and an increase in latency of the overall boot process because Petitioner “proposes modifying Saulsbury’s boot process by not only retaining Saulsbury’s original two steps but also adding steps by having the bootstrap program travel (and therefore copied multiple times) through boot interface 28, DSM controller 22, memory controller 20 into DRAM memory 14, and then back through memory controller 20 for execution by processing core 12.” Id. at 10 (reproducing Ex. 1004, Fig. 1 (annotations added)); see id. at 11 (quoting Ex. 2003 ¶ 114; citing PO Resp. 33–35). Patent Owner further contends that Petitioner does not dispute that the “modified boot process would have required the involvement of additional slower components (i.e., memory controllers) thus decreasing performance and increasing latency of the overall boot process, and counseling against the proposed combination.” Id. at 13. We do not agree with Patent Owner’s arguments that the combination would not have been obvious because the combination would result in a IPR2020-01017 Patent 6,961,807 B1 32 reduction in performance and increased latency compared to Saulsbury’s use of the processor core instruction cache for bootup. Although the combination of Saulsbury and Cullison may result in some reduction in performance and some increase in latency due to the fact that DRAM will be erased if power is lost, the retention of a slow external non-volatile memory (i.e., PROM) for storing the boot program, and the use of a slow memory controller to access the boot program in the external non-volatile memory compared to Saulsbury’s use of only the processor core instruction cache for bootup, we do not agree that these disadvantages undercut Petitioner’s showing of the advantages of the combination. More specifically, Patent Owner’s arguments do not undercut Petitioner’s showing that the combination of Saulsbury and Cullison: (1) would be advantageous for applications where the boot program is too large to fit in Saulsbury’s processor core’s level 1 cache by adding a configuration in which the onboard DRAM is configured to store the entire boot program, loaded from the external memory to the onboard multipurpose memory; and (2) would allow faster RAM access speed and improved bootup time without requiring extra memory because, when only portions of the boot program are stored in the instruction cache, the processor may stall while waiting for subsequent portions to be retrieved from slower external memory. See Pet. 12–13 (citing Ex. 1004 ¶ 67; Ex. 1003 ¶ 35). “[A] given course of action often has simultaneous advantages and disadvantages, and this does not necessarily obviate motivation to combine.” Medichem, S.A. v. Rolabo, S.L., 437 F.3d 1157, 1165 (Fed. Cir. 2006). “The fact that the motivating benefit comes at the expense of another benefit, however, should not nullify its use as a basis to modify the disclosure of one reference with the teachings of another. IPR2020-01017 Patent 6,961,807 B1 33 Instead, the benefits, both lost and gained, should be weighed against one another.” Id. (quoting Winner Int’l Royalty Corp. v. Wang, 202 F.3d 1340, 1349 n.8 (Fed. Cir. 2000)). As to increased cost, Patent Owner, contends that “[r]equiring the extra circuitry and logic necessary to load the boot program in the manner required by the Saulsbury and Cullison combination would have increased costs, particularly in order to fabricate a new data path from boot interface 28 through memory controller 20 to DRAM memory 14.” PO Resp. 32 (citing Ex. 2003 ¶ 118); see PO Sur-reply 14 (similar argument). Patent Owner contends that “Cullison seeks to eliminate ‘special purpose memories,’ such as a ‘boot memory—typically a read only memory (ROM)—that stores a boot program whose execution by the processor’s central processing unit (CPU) upon system power-up or reset automatically initializes the CPU.’” PO Resp. 32 (citing Ex. 1005, 1:11–18; Ex. 2003 ¶ 118). Patent Owner asserts that the “combination does not eliminate a special purpose memory,” but “retains the extra memory device storing the bootstrap program.” Id. at 33 (quoting Pet. 37; citing Ex. 1003 ¶ 56; Ex. 2003 ¶ 119; Ex. 2005, 156:25–157:10, 162:16–23), PO Sur-reply 14 (similar argument); see also PO Resp. 38 (arguing the combination still includes the PROM storing the bootstrap program and does not meet Cullison’s objective, citing Ex. 1005, 1:34–38; Ex. 2003 ¶ 128, Ex. 2005, 156:25–157:10, 162:16–23), 40 (arguing the combination fails to eliminate extra memory devices, citing Ex. 1005, 2:1–3; Ex. 2003 ¶ 134; incorporating by reference PO Resp. 23–35), 50 (arguing the proposed combination would not eliminate extra special purpose memories, citing Ex. 2005, 149:25– 150:8, 150:9–18, 151:10–20, 152:2–8; Ex. 2003 ¶ 153). According to Patent IPR2020-01017 Patent 6,961,807 B1 34 Owner, “Cullison’s teachings regarding lowering system cost and reducing circuit board area are inapplicable, and in any event, are outweighed by the costs of having to fabricate new data paths from boot interface 28 through controller 20 to DRAM memory 14.” PO Resp. 33 (citing Ex. 2003 ¶ 120). In Reply, Petitioner asserts that Patent Owner generically argues that adding new functionality would increase cost, and that Dr. Brogioli raised this generic argument against nearly every type of processor and memory discussed in the background section of his declaration testimony including integrated circuits comprising multiprocessors and memory, master-slave processors, VLIW (very long instruction word) processors, and cache. See Pet. Reply 23 (citing Ex. 2003). Petitioner contends that Dr. Brogioli alleges that each of these features increase cost and complexity, yet each of these features is taught by Saulsbury and Cullison. See id. (citing Ex. 1004 ¶¶ 1, 16; Ex. 1005, 2:17–31). According to Petitioner, “a generic notion of increased cost did not discourage [persons of ordinary skill in the art] based on the express teachings of [the] references.” Id. at 23–24. Petitioner points out that Saulsbury teaches a VLIW processor which, according to Dr. Brogioli “increases the complexity, but you get more performance,” and “target[s] some of the high performance computing space” where “there is a priority on performance.” Id. at 24 (quoting Ex. 1020, 50:19–53:7; citing Ex. 1004 ¶ 16; Ex. 1020, 48:23–49:12, 83:7–84:4). According to Petitioner, “[b]ecause Saulsbury targets high-performance computing, cost is less of a concern, as Dr. Brogioli admits.” Id. Petitioner further asserts that “[e]ven if there were some additional cost, this would not have obviated the motivation to combine, particularly for high-performance VLIW computing.” Id. (quoting Allied Erecting and Dismantling Co., Inc. v. IPR2020-01017 Patent 6,961,807 B1 35 Genesis Attachments, LLC, 825 F.3d 1373, 1381 (Fed. Cir. 2016); In re Dance, 160 F.3d 1339, 1334 (Fed. Cir. 1998); citing Novartis Pharm. Corp. v. W.-Ward Pharm. Int’l Ltd., 923 F.3d 1051, 1059–1060 (Fed. Cir. 2019)). Petitioner further contends that Patent Owner’s “aversion to cost would preclude any obviousness modification, [because] added functionality intrinsically includes some amount of cost.” Id. We do not agree with Patent Owner’s arguments that the combination would not have been obvious because it would have resulted in increased costs due to fabricating a new data path from boot interface 28 through memory controller 20 to DRAM memory 14. Although the combined teachings of Saulsbury and Cullison may result in some increase in cost for fabricating an additional data path, we do not agree that such an increase in cost undercuts Petitioner’s showing of the aforementioned advantages of the combination. See Medichem, 437 F.3d at 1165. We find misplaced Patent Owner’s arguments that Cullison’s teachings regarding lowering system cost and reducing circuit board area are inapplicable because the combination does not eliminate a special purpose memory such as a boot memory, but retains the extra memory device storing the bootstrap program. Contrary to Patent Owner’s suggestion, Cullison does not teach eliminating main memory 109 or secondary memory 108 that stores the boot program. See Ex. 1005, 2:28–32, 3:45–53, Fig. 1. Instead, Cullison teaches utilizing a memory 119 that is capable of providing two functions (e.g., cache memory and boot memory) at different times so that separate memory devices for each function do not need to be included in the system, thus eliminating extra memory devices for each specific function in order to lower system cost and reduce circuit board area. See id. at 1:41–2:3, 2:58–3:21, 4:11–66. IPR2020-01017 Patent 6,961,807 B1 36 In sum, we do not agree with Patent Owner’s arguments that the combination would not have been obvious because it would increase costs, increase latency, and reduce performance. Although modifying the teachings of Saulsbury in view of Cullison may result in some increase in cost, some increase in latency, and some reduction in performance when compared to the teachings of the system of Saulsbury, we do not find that such disadvantages undercut the advantages of the combination set forth by Petitioner. Patent Owner also argues that a person of ordinary skill in the art “working in August 2002 would not have found it obvious to apply Cullison’s teachings regarding an SRAM array for a slave processor to Saulsbury’s DRAM bank for a VLIW processor, particularly because SRAM and DRAM devices are not easily interchangeable.” PO Resp. 36 (citing Ex. 2003 ¶ 124; incorporating by reference PO Resp. 9–10). Patent Owner contends that Petitioner and Dr. Albonesi do not “address any of the substantial differences in performance, cost, space, and use cases between SRAM and DRAM.” Id. (citing Ex. 2003 ¶ 126); see id. at 36–37 (quoting TQ Delta, LLC v. Cisco Sys. Inc., 942 F.3d. 1352, 1362 (Fed. Cir. 2019); citing Ex. 2003 ¶ 125); see PO Sur-reply 16 (similar argument). We do not agree with Patent Owner’s arguments. As pointed out by Petitioner, the Petition does not propose modifying Saulsbury’s teachings by physically incorporating Cullison’s SRAM. See Pet. Reply 21 (quoting PO Resp. 36; In re Mouttet, 686 F.3d at 1332; citing Pet. 22–23). Moreover, Cullison’s teachings of storing a boot program in a multipurpose memory that can function as a boot memory and a cache are not limited to SRAMs. A prior art “reference must be considered for everything it teaches by way of IPR2020-01017 Patent 6,961,807 B1 37 technology and is not limited to the particular invention it is describing and attempting to protect.” EWP Corp. v. Reliance Universal Inc., 755 F.2d 898, 907 (Fed. Cir. 1985) (emphasis omitted). Patent Owner contends that a person of ordinary skill in the art would not have had a reasonable expectation of success in combining the teachings of Saulsbury and Cullison because they disclose different systems, are used for different purposes, and with different components. See PO Resp. 40 (citing Ex. 2003 ¶ 133). Reiterating arguments already addressed above, Patent Owner contends that Saulsbury and Cullison are directed to different teachings such that their combination would destroy a key objective of each reference by increasing the distance the bootstrap program must travel before execution by the processing core and failing to eliminate extra memory devices. See id. (citing Ex. 1004 ¶ 3; Ex. 1005, 2:1–3; Ex. 2003 ¶ 134; incorporating by reference PO Resp. 25–35). Patent Owner further contends that “replacing cache memory, boot memory, SRAM, DRAM, and cache controllers was neither simple nor routine, depending on the use to which each component was put.” Id. at 40–41 (citing Ex. 2003 ¶ 135). More specifically, Patent Owner argues: (1) replacing SRAM or DRAM with one another, depending on the application, required additional circuitry, logic, and power; (2) memory controllers, cache controller, and I/O controllers are distinct and serve distinct purposes; (3) boot operations are different from regular processing operations, with different operational requirements. See id. at 41–42 (citing Ex. 2003 ¶¶ 135–140; Ex. 2005, 177:13–22, 178:9–17, 178:19–179:5, 179:7–180:6, 180:21–181:17; incorporating by reference PO Resp. 9–11). IPR2020-01017 Patent 6,961,807 B1 38 For same reasons as those explained above, we do not agree that the combination of Saulsbury and Cullison would destroy key objectives of Saulsbury and Cullison. We also do not agree with Patent Owner’s arguments for the reasons stated by Petitioner––the Petition does not propose bodily incorporating Cullison’s SRAM into Saulsbury’s system. See Pet. Reply 25 (citing PO Resp. 40; incorporating by reference Pet. Reply 21–23). The preponderance of the evidence supports Petitioner’s assertion that a person of ordinary skill in the art would have had a reasonable expectation of success when combining the teachings of Saulsbury and Cullison due to the similarities of the teachings and on the basis that multipurpose on-chip memory, cache memory, boot memory, SRAM, DRAM, cache controllers, and memory ports were well-known, conventional components for processors and integrated circuits. See Pet. 15 (citing Ex. 1003 ¶ 40; incorporating by reference Pet. 10). Patent Owner agrees with Petitioner’s definition of a person of ordinary skill in the art as a person who would have had a bachelor’s degree in electrical or computer engineering, computer science, applied physics, or a related field, and at least two years of experience in design, development, and/or testing of integrated circuits, computer systems, or memory circuits, or the equivalent. See Pet. 10 (citing Ex. 1003 ¶¶ 22–25); PO Resp. 12 (adopting Petitioner’s definition). Yet, aside from pointing out the different systems, purposes, and components disclosed by Saulsbury and Cullison, Patent Owner offers insufficient explanation to overcome Petitioner’s showing that a person of ordinary skill in the art would have had a reasonable expectation of success in combining the teachings of Saulsbury and Cullison. IPR2020-01017 Patent 6,961,807 B1 39 Patent Owner argues that the combination of Saulsbury and Cullison does not disclose a second memory port for coupling a second external memory device with said multipurpose memory because Saulsbury, and the combination of Saulsbury and Cullison, does not disclose coupling boot interface 28 with DRAM bank 14. See PO Resp. 42–44 (reproducing Ex. 1004, Fig. 1 (with annotations); quoting Pet. 22; Dec. 14; Ex. 1003 ¶ 34; Ex. 1004 ¶ 78, citing Pet. 21–23; Ex. 2003 ¶¶ 143–146). Patent Owner asserts that Saulsbury does not disclose any mechanism to connect boot interface 28 to DRAM bank 14. See id. at 44–45 (citing Ex. 2003 ¶ 146). Patent Owner contends that Petitioner “does not point to any disclosure in Cullison evidencing a second memory port coupled with a multipurpose memory.” Id. at 45 (citing Ex. 2003 ¶ 146). According to Patent Owner, “Cullison discloses only a single access between CPU/MMU 111, SRAM array 119 and ‘main memory 109’ or ‘I/O subsystem 108’: DATA lines 142.” Id. (reproducing Ex. 1005, Fig. 1 (with annotations); citing Ex. 1005, 2:59–61; Ex. 2003 ¶ 146). Relying on previous arguments, Patent Owner contends that a person of ordinary skill in the art would not have been motivated to combine Saulsbury and Cullison. See id. at 44 (citing Ex. 2003 ¶ 146; incorporating by reference PO Resp. 23–39). We do not agree with Patent Owner’s arguments because, as pointed out by Petitioner, the arguments address the teachings of Saulsbury alone and Cullison alone, instead of addressing the teachings of Saulsbury and Cullison, as combined by Petitioner. See Pet. Reply 8 (citing Dec. 16). One cannot show nonobviousness by attacking references individually. See In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986). As explained above, the Petition relies on Saulsbury for teaching an external memory and boot IPR2020-01017 Patent 6,961,807 B1 40 interface which is modified in view of the teachings of Cullison such that Saulsbury’s external memory and boot interface is coupled with DRAM memory. Contrary to Patent Owner’s suggestion, the Petition does not propose modifying Saulsbury’s teachings to bodily incorporate Cullison’s data lines 142. For this reason, we cannot deduce the relevance of Patent Owner’s argument that Cullison’s data lines 142 only disclose a single access (see PO Resp. 45) and Petitioner’s arguments that a direct connection and two separate ports are not required by the claim language (see Pet. Reply 3–8). Finally, for all of the same reasons as those explained above, we do not agree with Patent Owner’s argument that a person of ordinary skill in the art would not have been motivated to combine the teachings of Saulsbury and Cullison. Based on the entire trial record, we determine that Petitioner sets forth sufficient articulated reasoning with rational underpinning to support the conclusion that it would have been obvious to one of ordinary skill in the art to modify the teachings of Saulsbury in view of Cullison by coupling Saulsbury’s multi-purpose memory to Saulsbury’s second external memory device through the boot interface, and storing an entire boot program in the multi-purpose memory such that the multipurpose memory includes a second boot memory mode. See Ex. 1003 ¶¶ 29–42, 54–56, 63–65; KSR, 550 U.S. at 418. (6) Conclusion Regarding the Analysis of Claim 1 Based on the entire trial record, Petitioner has established by a preponderance of the evidence that the subject matter of claim 1 would have been obvious over the combined teachings of Saulsbury and Cullison. IPR2020-01017 Patent 6,961,807 B1 41 d. Analysis of Independent Claims 7 and 13 Claim 7 recites a method that recites limitations nearly identical to the above-addressed limitations of claim 1. Compare Ex. 1001, 8:28–47 (claim 7), with Ex. 1001, 7:45–61 (claim 1). Petitioner asserts that the combination of Saulsbury and Cullison teaches “[a] method for forming an integrated circuit on a die, comprising: providing a microprocessor on the die, providing a multipurpose memory on the die; providing a cache controller on the die” as recited in claim 7, based on Petitioner’s assertions with respect to claim 1. See id. at 30 (citing Ex. 1003 ¶ 80; incorporating by reference Pet. 16–19). Petitioner further asserts that Saulsbury teaches a processor chip having a processing core and memory fabricated on a silicon die and providing memory controller 20/DSM controller 22 on the same die. See id. at 30–32 (reproducing Ex. 1004, Fig. 1; quoting Ex. 1004 ¶¶ 2, 3; citing Ex. 1004 ¶¶ 6, 16, 17, 65, 77 84; Ex. 1003 ¶¶ 81–83; incorporating by reference Pet. 10–19). For the remaining limitations of claim 7, Petitioner relies on its assertions with respect to claim 1, and its assertions addressing the preamble of claim 7. See id. at 32–33 (citing Ex. 1003 ¶¶ 84–89; incorporating by reference Pet. 20–28, 30–32). Claim 13 recites similar limitations as those recited in independent claims 1 and 7, in the form of a system that includes an external memory device and an integrated circuit that includes a microprocessor, a multipurpose memory coupled with the microprocessor, a cache controller coupled with the multipurpose memory. Compare Ex. 1001, 9:14–10:11 (claim 13), with Ex. 1001, 7:45–61 (claim 1), and Ex. 1001, 8:28–47 (claim 7). Petitioner asserts that the combination of Saulsbury and Cullison teaches and renders obvious the limitations of claim 13, relying primarily on IPR2020-01017 Patent 6,961,807 B1 42 its arguments addressing claim 1. See Pet. 37–41 (citing Ex. 1003 ¶¶ 105–117; incorporating by reference Pet. 10–30). Petitioner also asserts that the combination of Saulsbury and Cullison teaches and renders obvious “wherein said first and second memory ports are not simultaneously active to pass data to said multipurpose memory,” as recited in claim 13. See id. at 39 (citing Ex. 1003 ¶ 112; incorporating by reference Pet. 20–28, 37–38). Specifically, Petitioner asserts that Saulsbury teaches mode control that causes memory bank 14 to operate in one mode or another. See id. at 40 (quoting Ex. 1004 ¶ 68; citing Ex. 1004, code (57), ¶ 5). Petitioner also contends that Cullison teaches a cache memory mode and a boot memory mode that are exclusive of each other. See id. (quoting Ex. 1005, 1:41–2:3, 2:63–3:21; citing Ex. 1005, 4:1–43, 4:58–68; Ex. 1003 ¶¶ 113–114; incorporating by reference Pet. 23–28). Patent Owner does not dispute specifically Petitioner’s assertions addressing the limitations of claims 7 and 13. See generally PO Resp. Nonetheless, the burden remains on Petitioner to demonstrate unpatentability. See Dynamic Drinkware, 800 F.3d at 1378. Based on the entire trial record, and including the reasons explained above addressing claim 1, we determine Petitioner has shown by a preponderance of the evidence that the subject matter of independent claims 7 and 13 would have been obvious over the combined teachings of Saulsbury and Cullison. e. Analysis of Dependent Claims 2–4, 8–12, and 14–17 Claims 2–4 depend from claim 1, claims 8–12 depend from independent claim 7, and claims 14–17 depend from independent claim 13. Ex. 1001, 7:44–8:3, 8:28–10:24. We have reviewed Petitioner’s contentions IPR2020-01017 Patent 6,961,807 B1 43 and supporting evidence addressing how the combination of Saulsbury and Cullison teaches or suggests the additional limitations recited in dependent claims 2–4, 8–12, and 14–17. See Pet. 28–30, 33–37, 41–42 (citations omitted). Patent Owner does not dispute specifically Petitioner’s assertions addressing the limitations of dependent claims 2–4, 8–12, and 14–17. See generally PO Resp. Nonetheless, the burden remains on Petitioner to demonstrate unpatentability. See Dynamic Drinkware, 800 F.3d at 1378. Based on the entire trial record, and including the reasons explained above addressing independent claims 1, 7, and 13, we determine Petitioner has shown by a preponderance of the evidence that the subject matter of dependent claims 2–4, 8–12, and 14–17 would have been obvious over the combined teachings of Saulsbury and Cullison. f. Summary For all of the foregoing reasons, we determine Petitioner has established by a preponderance of the evidence that claims 1–4 and 7–17 are unpatentable under 35 U.S.C. § 103 over Saulsbury and Cullison. 2. Challenge to Claim 5 over Saulsbury, Cullison, and Gupta a. Overview of Gupta (Ex. 1007) Gupta is directed to a microprocessor having software controllable power management. See Ex. 1007 code (57), 1:4–6. In one embodiment, the microprocessor includes a multiported static random access memory (SRAM) having two ports. See id. at 4:10–14, 8:20–22, Fig. 7. Each port has a sense amplifier, a driver, an address decoder, and pull-up transistors. See id. at 8:22–24. The sense amplifier, driver, decoder and pull-up transistors for one or both of the ports is selectively disabled responsive to a IPR2020-01017 Patent 6,961,807 B1 44 value stored in a power control register field. See id. at 4:10–14, 8:25–28. By selectively enabling and disabling the components for each port, the execution rate and power dissipation of the multiported memory can be adjusted accordingly. See id. at 4:14–17, 8:44–47. Gupta further discloses that using software instead of hardware to adjust the rate of the execution and power dissipation is advantageous because software can look much further into the future to determine what functional units will be required. See id. at 11:59–65. Units that will not be required (i.e., SRAM, ports) can be set to low power or a no power state by setting the appropriate value in the corresponding power control register field. See id. at 11:65–12:1. b. Analysis Claim 5 depends from claim 1 and further recites “wherein when said first memory port is coupled with said first external memory device, said second memory port is not coupled with the second external memory device.” Ex. 1001, 8:4–7. Petitioner asserts that “Gupta teaches a multi- ported SRAM where one or more of the ports is decoupled (e.g., disabled and powered off) when not in use.” Pet. 78–79 (reproducing Ex. 1007, Fig. 7; quoting Ex. 1007, 8:25–47; citing Ex. 1007, 4:10–21, 8:14–24; Ex. 1003 ¶ 238). Petitioner asserts that it would have been obvious to one of ordinary skill in the art to modify the combined teachings of Saulsbury and Cullison to electrically decouple the second external memory that stores the boot program from the boot interface when the multipurpose memory is in cache memory mode in order to save costs and reduce power consumption because the boot program is no longer needed. See id. at 76–78 (citing Ex. 1003 ¶¶ 229–235), 79–80 (citing Ex. 1003 ¶ 239; incorporating by reference Pet. 20–21, 23–26); KSR, 550 U.S. at 418. IPR2020-01017 Patent 6,961,807 B1 45 In Response, Patent Owner relies on its arguments addressing the combination of Saulsbury and Cullison to assert that Saulsbury, Cullison, and Gupta cannot render obvious claim 5. See PO Resp. 70. For the same reasons as those explained above addressing claim 1, we do not agree with Patent Owner’s arguments. Based on the entire trial record, we determine Petitioner sets forth sufficient articulated reasoning with rational underpinning to support the conclusion that it would have been obvious to one of ordinary skill in the art to modify the combined teachings of Saulsbury and Cullison in view of Gupta’s teachings to decouple the second memory from the boot interface when in cache mode to save costs and reduce power consumption. See Ex. 1003 ¶¶ 229–235, 239; KSR, 550 U.S. at 418. Based on the entire trial record, and including the reasons explained above addressing claim 1, we determine Petitioner has shown by a preponderance of the evidence that the subject matter of claim 5 would have been obvious over the combined teachings of Saulsbury, Cullison, and Gupta, and, therefore, claim 5 is unpatentable under 35 U.S.C. § 103 over Saulsbury, Cullison, and Gupta. 3. Challenges to Claims 1–4 and 7–17 over Kumar and Cullison and Claim 5 over Kumar, Cullison, and Gupta Petitioner also challenges claims 1–4 and 7–17 under 35 U.S.C. § 103 over Kumar and Cullison and claim 5 over Kumar, Cullison, and Gupta. See Pet. 42–76, 80. We need not determine the merits of those challenges because, as explained above, Petitioner has demonstrated the unpatentability of those claims over Saulsbury and Cullison, and Saulsbury, Cullison, and Gupta. See Beloit Corp. v. Valmet Oy, 742 F.2d 1421, 1423 (Fed. Cir. 1984) IPR2020-01017 Patent 6,961,807 B1 46 (finding an administrative agency is at liberty to reach a decision based on a single dispositive issue because doing so “can not only save the parties, the [agency], and [the reviewing] court unnecessary cost and effort,” but can “greatly ease the burden on [an agency] faced with a . . . proceeding involving numerous complex issues and required by statute to reach its conclusion within rigid time limits”). 4. New and Nonresponsive Arguments Patent Owner contends that Petitioner presents a new theory in its Reply to support its motivation to combine––that loading the entire boot program into DRAM was common and consistent with industry practice. See PO Sur-reply 13 (quoting Pet. Reply 17; citing Pet. Reply 16–18). We agree. Compare Pet. Reply 16–18, with Pet. 10–16, 22–23, 27–28. Petitioner’s new theory exceeds the proper scope of a reply and has not been considered in rendering this Final Written Decision. See 37 C.F.R. § 42.23(b); Patent Trial and Appeal Board Consolidated Trial Practice Guide November 2019 (“CTPG”) 73–74. Patent Owner argues in its Sur-reply that a person of ordinary skill in the art would not have had a reasonable expectation of success in combining Saulsbury and Cullison because Saulsbury’s processor core cannot communicate with memory controller until the processor core is booted and Saulsbury never contemplated that memory controller could communicate with unbooted processor core. See PO Sur-reply 11 (citing Ex. 1004 ¶¶ 78, 82; PO Resp. 28–29). The Sur-reply does not identify arguments in Petitioner’s Reply or issues raised in the Institution Decision to which this argument responds. See id. Patent Owner also did not raise this argument in its Response. See PO Resp. 28–29 (arguing that Petitioner proposes IPR2020-01017 Patent 6,961,807 B1 47 modifying Saulsbury in a way never intended by bypassing processing core 12 instruction cache and having the bootstrap program travel through boot interface 28 through memory controller 20 into DRAM 14 and back through memory controller 20 for execution by processing core), 32 (arguing the memory controller 20 would not be used to communicate with external non- volatile memory), 34–35 (arguing the speed of a memory controller to arbitrate boot procedure is slower than CPU speed). Patent Owner’s new argument exceeds the proper scope of a sur-reply and has not been considered in rendering this Final Written Decision. See CTPG 73–74. III. PETITIONER’S MOTION TO EXCLUDE EVIDENCE Petitioner moves to exclude Exhibit 2007 under Rule 901 of the Federal Rules of Evidence. See Mot. 1–2; Reply Opp. 1. Patent Owner opposes the Motion. See Opp. It is unnecessary to resolve this evidentiary dispute because we have determined that Petitioner prevails even when considering Exhibit 2007. Thus, we dismiss as moot Petitioner’s Motion to Exclude Exhibit 2007. IPR2020-01017 Patent 6,961,807 B1 48 IV. CONCLUSION7 For the reasons explained above, we conclude: Claim(s) 35 U.S.C. § Reference(s)/Basis Claim(s) Shown Unpatentable Claim(s) Not Shown Unpatentable 1–4, 7–17 103 Saulsbury, Cullison 1–4, 7–17 1–4, 7–17 1038 Kumar, Cullison 5 103 Saulsbury Cullison, Gupta 5 5 1039 Kumar, Cullison, Gupta Overall Outcome 1–5, 7–17 V. ORDER In consideration of the foregoing, it is hereby: ORDERED that claims 1–5 and 7–17 are unpatentable under 35 U.S.C. § 103; FURTHER ORDERED that Petitioner’s Motion to Exclude Exhibit 2007 is dismissed as moot; and 7 Should Patent Owner wish to pursue amendment of the challenged claims in a reissue or reexamination proceeding subsequent to the issuance of this decision, we draw Patent Owner’s attention to the April 2019 Notice Regarding Options for Amendments by Patent Owner Through Reissue or Reexamination During a Pending AIA Trial Proceeding. See 84 Fed. Reg. 16,654 (Apr. 22, 2019). If Patent Owner chooses to file a reissue application or a request for reexamination of the challenged patent, we remind Patent Owner of its continuing obligation to notify the Board of any such related matters in updated mandatory notices. See 37 C.F.R. § 42.8(a)(3), (b)(2). 8 This challenge was not reached for the reasons explained above. 9 This challenge was not reached for the reasons explained above. IPR2020-01017 Patent 6,961,807 B1 49 FURTHER ORDERED that, because this is a Final Written Decision, parties to the proceeding seeking judicial review of the decision must comply with the notice and service requirements of 37 C.F.R. § 90.2. IPR2020-01017 Patent 6,961,807 B1 50 PETITIONER: Harper Batts Jeffrey Liang Chris Ponder SHEPPARD, MULLIN, RICHTER & HAMPTON LLP HBatts@sheppardmullin.com CPonder@sheppardmullin.com JLiang@sheppardmullin.com PATENT OWNER: Christopher R. O’Brien Theodoros Konstantakopoulos, Ph.D. Kevin McNish Yung-Hoon Ha Jordan N. Malz Michael A. Wueste Ryan G. Thorne DESMARAIS LLP cobrien@desmaraisllp.com tkonstantakopoulos@desmaraisllp.com kkm-ptab@desmaraisllp.com yha@desmaraisllp.com jmalz@desmaraisllp.com mwueste@desmaraisllp.com rthorne@desmaraisllp.com