MLC INTELLECTUAL PROPERTY , LLC (ASSIGNEE) et al.

Patent Trials and Appeals Board

Nov 2, 2020

90014245 - (D) (P.T.A.B. Nov. 2, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
90/014,245 12/18/2018 5764571 4293
37086 7590 11/02/2020
POLSINELLI PC
(NDQ REEXAMINATION GROUP)
1000 LOUISIANA STREET
Suite 6400
HOUSTON, TX 77002
EXAMINER
LEE, CHRISTOPHER E
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
11/02/2020 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MLC INTELLECTUAL PROPERTY, LLC
Patent Owner and Appellant
____________

Appeal 2020-005915
Reexamination Control 90/014,245
United States Patent 5,764,571
Technology Center 3900
____________

Before ALLEN R. MacDONALD, JOHN A. JEFFERY, and
KEVIN F. TURNER, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. §§ 134 and 306 the Examiner’s
decision to reject claims 1, 9, 30, 42, and 45. We have jurisdiction under 35
U.S.C. §§ 134 and 306, and we heard the appeal on October 26, 2020.
We AFFIRM.

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies the real party in interest as MLC
Intellectual Property, LLC. Appeal Br. 1.
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STATEMENT OF THE CASE
This proceeding arose from a request for ex parte reexamination filed
on December 18, 2018 of United States Patent 5,764,571 (“the ’571 patent”),
issued to Gerald J. Banks on June 9, 1998.
The ’571 patent describes an electrically-alterable, non-volatile multi-
bit memory cell with predetermined memory states. The cell’s programming
is verified by (1) selecting a reference signal corresponding to information to
be stored, and (2) comparing a cell signal with the selected reference signal.
See Abstract. Claim 1 is illustrative of the invention and is reproduced
below:
1. A multi-level memory device comprising:
an electrically alterable non-volatile multi-level memory cell
for storing input information in a corresponding one of Kn
predetermined memory states of said multi- level memory cell, where
K is a base of a predetermined number system, n is a number of bits
stored per cell, and Kn >2;
memory cell programming means for programming said multi-
level memory cell in accordance with said input information;
reference voltage selecting means for selecting one of a plurality of
reference voltages in accordance with said input information, each of said
reference voltages corresponding to a different one of said predetermined
memory states; and
comparator means for comparing a voltage of said multi-level
memory cell with the selected reference voltage, said comparator means
further generating a control signal indicating whether the state of said
multi-level memory cell is the state corresponding to said input
information.

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RELATED PROCEEDINGS
This appeal is said to be related to various pending proceedings. First,
Appellant informs us of related copending litigation, namely MLC
Intellectual Property, LLC v. Micron Technology, Inc., No. 3:14-cv-03657
(N.D. Cal. Aug. 12, 2014). Appeal Br. 1.2
Appellant also informs us that the ’571 patent was the subject of two
inter partes review (IPR) proceedings, IPR2015-00504 and IPR2015-00517,
where the Board denied institution in both proceedings. Id. Appellant adds
that the ’571 patent is also the subject of two ex parte reexamination
proceedings, control numbers 90/020,112 and 90/014,421, where the former
confirmed the claims’ patentability over the combination of Kitamura (cited
in full below) and Connolly, the latter reference not at issue here. See id.;
see also Ans. 6. Although the ’421 reexamination proceeding is still
pending, it is directed to claims 15–17 of the ’571 patent that are not at issue
here. See Appeal Br. 1.

THE REJECTION
The Examiner rejected claims 1, 9, 12, 30, 42, and 45 under 35 U.S.C.
§ 103 as unpatentable over Kitamura (JP60-175105 A; published Feb. 14,
1987) and Noguchi (US 5,262,984; issued Nov. 16, 1993). Final Act. 6–16.

2 Throughout this opinion, we refer to (1) the Final Rejection mailed January
14, 2020 (“Final Act.”); (2) the Appeal Brief filed March 23, 2020 (“Appeal
Br.”); (3) the Examiner’s Answer mailed June 12, 2020 (“Ans.”); and (4) the
Reply Brief filed August 12, 2020 (“Reply Br.”).
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CONTENTIONS, FINDINGS, AND CONCLUSIONS
The Examiner finds that Kitamura’s multi-level memory device
includes, among other things, a reference voltage converter for generating
one of plural reference voltages, namely threshold voltages VT, according to
input information, namely digital signals B1 and B2. Final Act. 6–8.
Although the Examiner acknowledges that Kitamura’s converter does not
select a reference voltage according to the input information, the Examiner
cites Noguchi for teaching this feature in concluding that the claim would
have been obvious. Final Act. 8. According to the Examiner, substituting
Noguchi’s input data changeover circuit 40 and constant voltage changeover
circuit 44 in Figure 12, which the Examiner maps collectively to the recited
reference voltage selecting means, for Noguchi’s digital-to-analog (D/A)
conversion circuit 10 in Figure 1 would have been a simple substitution to
obtain predictable results. Id. This substitution is said to provide more
versatility than Kitamura’s D/A converter by enabling analog output voltage
levels to be set independently to best suit the memory cell’s characteristics.
Id.
Appellant argues that the Examiner not only contradicts the Board’s
earlier determinations, the Examiner’s proposed replacement of Kitamura’s
D/A converter with Noguchi’s multiplexer is based solely on impermissible
hindsight, and there is no reason to combine the references as the Examiner
proposes. Appeal Br. 7–27; Reply Br. 9–13. Appellant adds that the
Examiner’s proposed substitution not only changes Kitamura’s principle of
operation from two-way uniform conversion to non-uniform selection and
conversion, the proposed substitution renders Kitamura inoperable for its
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intended purpose by, among other things, eliminating shared circuitry
needed to maintain the operating margin between verification and testing.
Appeal Br. 18–31; Reply Br. 1–9. Because claims 9, 12, 30, 42, and 45 are
not argued separately with particularity (see generally Appeal Br.; Reply
Br.), we determine this appeal on the basis of claim 1.

ISSUE
Under § 103, has the Examiner erred in rejecting claim 1 by finding
that Kitamura and Noguchi collectively would have taught or suggested a
reference voltage selecting means for selecting one of plural reference
voltages in accordance with stored input information? This issue turns on
whether substituting Noguchi’s input data changeover circuit and constant
voltage changeover circuit for Kitamura’s D/A conversion circuit as the
Examiner proposes renders Kitamura unsuitable for its intended purpose.

ANALYSIS
We begin by noting that because the ’571 patent expired, we construe
the claims under the standard set forth in Phillips v. AWH Corp., 415 F.3d
1303 (Fed. Cir. 2005) (en banc). See In re Rambus, Inc., 753 F.3d 1253,
1256 (Fed. Cir. 2014). Accord Final Act. 2 (construing the claims under the
Phillips standard given the ’571 patent’s expiration).
Under the Phillips standard, claim terms are generally given their
ordinary and customary meaning, namely the meaning the term would have
to an ordinarily skilled artisan at the time of the invention. Phillips, 415
F.3d at 1312. In construing the claim, we begin with the intrinsic evidence
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of record, namely the claim language, the patent specification, and, if in
evidence, the prosecution history. See id. at 1313.
Turning to claim 1, the claim recites, in pertinent part, reference
voltage selecting means for selecting one of plural reference voltages in
accordance with input information, each reference voltage corresponding to
a different one of the multi-level memory cell’s predetermined memory
states (“the reference voltage selecting means limitation”). Under § 112,
sixth paragraph, this means-plus-function limitation is construed in light of
the corresponding structure in the Specification and its equivalents. See In
re Donaldson Co., Inc., 16 F.3d 1189, 1193 (Fed. Cir. 1994) (en banc).
Accord Final Act. 5 (construing the reference voltage selecting means
limitation under § 112, sixth paragraph); MLC Intellectual Property, LLC v.
Micron Technology, Inc., No. 14-cv-03657-SI, 2016 WL 6563343, at *3–4
(N.D. Cal. 2016) (unpublished) (noting the parties’ agreement that the
reference voltage selecting means limitation is a means-plus-function
limitation construed under § 112, sixth paragraph).
It is undisputed that the verify reference voltage select circuit 222 in
the ’571 patent’s Figure 8 is the structure corresponding to the recited
reference voltage selecting means. See Final Act. 6; Appeal Br. 3 (referring
to verify reference voltage select circuit 222 as a selecting device for
selecting a verify reference voltage or signal); Micron Tech., Inc. v. MLC
Intellectual Property, LLC, IPR2015-00504, IPR2015-00517, Paper 8 at 6–7
(PTAB July 20, 2015) (“IPR Dec.”) (noting that the verify reference voltage
select circuit 222 is the structure corresponding to the reference voltage
selecting means limitation). Accord Micron Tech., Inc. v. MLC Intellectual
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Property, LLC, No. 14-cv-03657-SI, 2018 WL 4616255 (N.D. Cal. 2018)
(unpublished), at *3–5 (articulating a similar construction).
Turning to the rejection, the Examiner acknowledges that Kitamura
does not disclose the recited reference voltage selecting means for selecting
one of plural reference voltages, but rather discloses a reference voltage
converter for converting one of plural reference voltages, namely D/A
conversion circuit 10 in Figure 1. See Final Act. 7–8. The Examiner,
however, concludes that substituting Noguchi’s input data changeover
circuit 40 and constant voltage changeover circuit 44 in Figure 12, which the
Examiner maps collectively to the recited reference voltage selecting means,
for Noguchi’s D/A conversion circuit, would have been a simple substitution
to obtain predictable results. Final Act. 8.
On this record, we see no error in the Examiner’s proposed
combination. First, the Examiner’s findings and conclusions do not conflict
with those of the Board in the related IPR proceedings, despite Appellant’s
arguments to the contrary. See Appeal Br. 10–11. As the Examiner
indicates (Ans. 6–7, 10–11), the Board did not consider the
Kitamura/Noguchi combination at issue here, but rather considered whether
the Petitioner was reasonably likely to prevail in showing that at least one of
the challenged claims was unpatentable as obvious over either the Kitamura
or Mehrotra references, the latter not at issue here. See IPR Dec. 3–15.
Although the Board concluded that the Petitioner was not reasonably likely
to prevail in showing that the claimed invention would have been obvious
based on Kitamura (or Mehrotra) alone, Noguchi was simply not at issue in
the IPR proceeding, let alone the proposed Kitamura/Noguchi combination
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at issue here. Accord Declaration of David Kuan-Yu Liu, dated Dec. 17,
2018 (“Liu Decl.”) ¶ 53 (noting that the obviousness grounds in the IPR
petitions each involved obviousness over a single reference). Appellant’s
contention, then, that the Board ostensibly already considered and rejected
the argument that Kitamura and Noguchi allegedly perform the same
function (Appeal Br. 23) is, at best, overstated since Noguchi was not before
the Board in the related IPR proceedings.
In the related IPR proceedings, the Board found that Kitamura does
not disclose the D/A conversion circuit’s specific functioning, let alone
selecting between reference voltages or signals. See IPR Dec. 10. In
reaching its conclusion, the Board noted that a D/A converter’s normal
function is not selecting between reference voltages, but rather rendering
digital input into analog form. Id. The Board added that the Petitions in
those proceedings provided no rationale why Kitamura’s disclosure of D/A
conversion renders selecting a reference voltage or signal obvious. Id.
Our emphasis underscores that the Board’s findings and conclusions
in this regard were based solely on Kitamura—not Kitamura combined with
other references, let alone Noguchi, as is the case here. Nevertheless, the
Examiner’s findings regarding Kitamura reasonably comport with those of
the Board in the related IPR proceedings, namely that Kitamura does not
disclose the recited reference voltage selecting means for selecting one of
plural reference voltages, but rather discloses a reference voltage converter
for converting one of plural reference voltages, namely D/A conversion
circuit 10 in Figure 1. See Final Act. 7–8; Ans. 2 (noting that Kitamura
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discloses every recited element except for the reference voltage selecting
means).
Notably, the Examiner’s obviousness rejection is not based on
Kitamura alone as in the related IPR proceedings, but rather Kitamura and
Noguchi collectively. Moreover, the Examiner articulates why it would have
been obvious for an ordinarily skilled artisan3 to select reference voltages in
Kitamura in light of Noguchi, namely to provide more versatility to
Kitamura’s D/A conversion circuit by enabling independently setting output
voltages to best suit the memory cell’s characteristics. See Final Act. 8;
Ans. 3–5, 8–9, 21, 40. Accord Liu Decl. ¶ 79 (noting that Noguchi’s
approach in Figure 12 would provide more versatility than a typical D/A
converter because Noguchi’s constant voltage circuits independently
generate their respective constant voltages, thus allowing the system
designer to set voltage levels independently for each input bit combination to

3 Both Dr. Lee and Dr. Liu describe the level of ordinary skill in the
pertinent art similarly. See Declaration of Dr. Jack Lee, dated Apr. 26, 2019
(“Lee Decl.”) ¶ 11; see also Declaration of David Kuan-Yu Liu, dated Dec.
17, 2018 (“Liu Decl.”) ¶ 12; Supplemental Declaration of David Kuan-Yu
Liu, dated May 31, 2019 (“Supp. Liu Decl.”) ¶ 8. Therefore, we find, as did
the court in a related proceeding, that one of ordinary skill in the art at the
time of the invention would have (1) an undergraduate degree in electrical
engineering (or equivalent subject), along with three to four years of post-
graduate experience designing semiconductor and memory devices, or (2) a
master’s degree in electrical engineering (or equivalent subject) together
with one or two years of post-graduate experience designing semiconductor
and memory devices. Accord MLC Intellectual Property, LLC v. Micron
Technology, Inc., No. 3:14-cv-03657-SI, 2016 WL 6563343 (N.D. Cal. Nov.
4, 2016), at *2–3 (adopting this skill level).
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best suit memory cell characteristics); Supp. Liu Decl. ¶ 24 (reiterating
Noguchi’s more versatile approach).4
On this record, we see no error in Examiner’s conclusion. As shown
in Noguchi’s Figure 12, reproduced below, input buffers for binary data D0
and D1 are connected to input data changeover circuit 40 that is connected to
constant voltage changeover circuit 44. See Noguchi, col. 10, ll. 3–58.

Noguchi’s input data and constant voltage changeover circuits in Figure
12

As noted previously, the Examiner maps Noguchi’s input data and
constant voltage changeover circuits 40 and 44 collectively to the recited

4 Although Dr. Liu’s declarations also discuss the Briner reference that is not
at issue here, Dr. Liu’s discussion regarding Kitamura, Noguchi, and their
combinability is nonetheless pertinent to the obviousness rejection before us.
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reference voltage selecting means. See Final Act. 8; Ans. 4, 7, 9, 14–15, 18–
19, 28.
We see no error in this mapping. As Dr. Liu explains, Noguchi’s
input data and constant voltage changeover circuits 40 and 44 collectively
perform the same overall function as a 2-bit D/A converter by (1) receiving a
2-bit input (D0 and D1), and (2) outputting one of four constant analog
voltages corresponding to the input by selecting that voltage—functionality
commensurate with that of an analog multiplexer. See Liu Decl. ¶¶ 78–87.
Accord Ans. 16 (referring to Dr. Liu’s testimony in this regard).
Given Noguchi’s D/A conversion and voltage selection functionality,
we see no error in the Examiner’s conclusion that providing such selection
functionality in addition to D/A conversion under Examiner’s proposed
combination would have been at least an obvious variation yielding a
predictable result. Such an enhancement uses prior art elements predictably
according to their established functions—an obvious improvement. See KSR
Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007).
Appellant’s contention that Noguchi’s constant voltage changeover
circuit is not a D/A converter because the digital input and analog outputs
ostensibly have no relationship is unavailing. See Appeal Br. 12 (citing
Declaration of Jerry Banks Pursuant to 37 CFR 1.132, dated Nov. 7, 2019
(“Banks Decl.”) ¶ 19). Although we appreciate Mr. Banks’ insights in this
regard, the fact that he is an interested party, namely the inventor, in this
proceeding reduces the probative value of his declaration, at least with
respect to his views regarding patentability of his invention over the cited
prior art. See Ashland Oil, Inc. v. Delta Resins & Refractories, Inc., 776
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F.2d 281, 294 (Fed. Cir. 1985) (noting that an expert’s interest in the
outcome of the case is a factor in assessing the probative value of an expert
opinion). Moreover, Mr. Bank’s averments regarding Noguchi’s alleged
lack of a D/A converter are undercut by Dr. Liu’s averments to the contrary.
See Liu Decl. ¶ 78 (noting that Noguchi’s input data and constant voltage
changeover circuits 40 and 44 collectively perform the same overall function
as a 2-bit D/A converter). Therefore, to the extent that Appellant contends
that the proposed combination somehow eliminates D/A conversion, we
disagree given Noguchi’s D/A conversion and selection functionality noted
above. Accord Ans. 16 (noting this dual functionality).
Nor are we persuaded that combining the teachings of Noguchi with
those of Kitamura as the Examiner proposes would render Kitamura
inoperable or unsuitable for its intended purpose as Appellant contends. See
Appeal Br. 27–30; Reply Br. 4–9. As Dr. Liu explains, Noguchi’s circuits
40 and 44 collectively achieve the same result and conversion function,
namely converting digital input to analog output, as Kitamura’s D/A
conversion circuit 10. Supp. Liu Decl. ¶ 23. Therefore, using Noguchi’s
circuits 40 and 44 in place of Kitamura’s D/A conversion circuit 10 would
simply use Noguchi’s 4-input analog multiplexer structure to perform in the
same predictable manner that the 4-input multiplexer performs in Noguchi
as Dr. Liu indicates. Id.
Notably, as Dr. Liu explains in paragraph 26 of his supplemental
declaration, the Kitamura/Noguchi combination does not alter Kitamura’s
programming verification and overall memory cell programming technique.
With the proposed combination, Kitamura’s comparator 9 still uses the
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output of the modified D/A conversion circuit in the same manner Kitamura
discloses. See Supp. Liu Decl. ¶ 26. In short, differences in the way
Kitamura uses the output of D/A conversion circuit 10 and the way Noguchi
uses the output of circuit 44 do not make Noguchi’s conversion technique
any less applicable to Kitamura. Id. Although Kitamura and Noguchi use
the outputs of their conversions differently, ordinarily skilled artisans would
nonetheless recognize the conversions themselves are commensurate, and
that Noguchi’s circuits 40 and 44 could be used to perform Kitamura’s
conversion as Dr. Liu indicates. Id. ¶ 38. Such an enhancement uses prior
art elements predictably according to their established functions—an
obvious improvement. See KSR, 550 U.S. at 417. So even assuming,
without deciding, that Noguchi’s constant voltage changeover circuit is not
used for verification as Appellant contends (Appeal Br. 20–21) and Dr. Lee
avers in paragraph 85 of his declaration,5 the fact that Noguchi’s conversion
output is not used for this particular purpose does not mean that Noguchi’s
converter cannot be used for another purpose, such as that in Kitamura as the
Examiner proposes. Nor has Appellant shown persuasively that the cited
references criticize, discredit, or otherwise discourage the Examiner’s
proposed combination to teach away from that approach. See Norgren Inc.
v. Int’l Trade Comm’n, 699 F.3d 1317, 1326 (Fed. Cir. 2012); see also In re
Kahn, 441 F.3d 977, 990 (Fed. Cir. 2006).
Appellant’s contention that replacing Kitamura’s D/A conversion
circuit 10 with that shown in Noguchi’s Figure 12 would break the
uniformity of characteristics of Kitamura’s D/A and A/D conversion circuits

5 Declaration of Dr. Jack Lee, dated Apr. 26, 2019 (“Lee Decl.”) ¶ 85.
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provided by sharing a voltage dividing element and reference voltage supply
(Appeal Br. 27–28) is unavailing. To be sure, Kitamura’s D/A and A/D
conversion circuits 10 and 13 preferably share a voltage dividing element
and reference voltage supply to make their characteristics uniform.
Kitamura ¶ 11. Our emphasis on the term “preferably” underscores that
sharing these elements to achieve uniformity is merely a preference—not a
requirement—as Dr. Liu indicates. See Supp. Liu Decl. ¶ 32. Accord Ans.
23 (noting this preference). Although Kitamura’s particular shared
arrangement may be preferred to achieve uniformity, ordinarily skilled
artisans would nevertheless infer from Kitamura’s articulation that there may
be other ways to achieve uniformity as the Examiner indicates (Ans. 23)—
albeit less preferred.
For example, Dr. Liu explains that, under the proposed combination,
uniformity between Kitamura’s circuits 10 and 13 can be achieved by
sharing a reference voltage supply, namely by replacing Kitamura’s single
reference voltage supply and voltage dividing element with four separate
reference voltage supply circuits. Supp. Liu Decl. ¶ 33. On this record, we
see no reason why these four reference voltage supplies under the proposed
combination could not be shared to achieve uniformity as Dr. Liu indicates.
See id. Sharing these voltage supplies to achieve uniformity is not only
reasonably consistent with Kitamura’s teachings, there is no persuasive
evidence on this record to rebut this finding.
We reach this conclusion despite Dr. Lee’s view that replacing
Kitamura’s D/A conversion circuit 10 with Noguchi’s Figure 12 would
break uniformity, and that the proposed combination would likely render
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Kitamura inoperable for its intended purpose. See Lee Decl. ¶ 84. Leaving
aside Dr. Lee’s speculative term “likely” in connection with Kitamura’s
alleged inoperability under the proposed combination, Dr. Lee’s averments
are undercut by those of Dr. Liu as noted above.
To the extent that Appellant contends that using shared voltage
supplies under the Kitamura/Noguchi combination as Dr. Liu explains
somehow eliminates shared circuity needed to maintain the operating margin
between verification and testing (see Reply Br. 7–9), there is no persuasive
evidence on this record to substantiate such a contention. Although we
appreciate Mr. Banks’ insights in this regard in paragraphs 8 to 18 of his
declaration, he is nonetheless an interested party, namely the inventor, in this
proceeding—a fact that reduces the probative value of his declaration, at
least with respect to his views regarding patentability of his invention over
the cited prior art. See Ashland Oil, 776 F.2d at 294. Nevertheless, Mr.
Banks’s averments do not squarely address the particular alternative noted
above by Dr. Liu, namely using four shared reference voltage supplies under
the Kitamura/Noguchi combination. To the extent that Appellant contends
that this proposed modification somehow eliminates shared circuity needed
to maintain the operating margin between verification and testing, there is no
persuasive evidence on this record to substantiate such a contention.
Lastly, we note that the propriety of the Examiner’s obviousness
rejection is not based on whether Noguchi’s features can be bodily
incorporated into Kitamura’s structure, but rather what the combined
teachings of the references would have suggested to those of ordinary skill
in the art. See In re Keller, 642 F.2d 413, 425 (CCPA 1981). Nor do
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obviousness determinations based on teachings from multiple references
require an actual, physical substitution of elements. In re Mouttet, 686 F.3d
1322, 1332 (Fed. Cir. 2012) (citations omitted). On this record, Appellant
has not persuasively rebutted the Examiner’s proposed combination given
the cited references’ collective teachings considered in light of the evidence
of record. As noted previously, we find the proposed enhancement to
Kitamura, namely providing both conversion and selection in light of
Noguchi’s circuitry in Figure 12, would provide more versatility by enabling
analog output voltage levels to be set independently to best suit the memory
cell’s characteristics as the Examiner and Dr. Liu indicate. See Ans. 3–5, 8–
9, 21, 40; see also Supp. Liu Decl. ¶ 24. This proposed enhancement uses
prior art elements predictably according to their established functions—an
obvious improvement. See KSR, 550 U.S. at 417.
Therefore, we are not persuaded that the Examiner erred in rejecting
claim 1, and claims 9, 12, 30, 42, and 45 not argued separately with
particularity.

CONCLUSION
The Examiner’s decision to reject claims 1, 9, 12, 30, 42, and 45 is
affirmed.
DECISION SUMMARY
In summary:
Claims
Rejected
35
U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1, 9, 30, 42, 45 103 Kitamura, Noguchi 1, 9, 30, 42, 45
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REQUESTS FOR EXTENSIONS OF TIME
Requests for extensions of time in this ex parte reexamination
proceeding are governed by 37 C.F.R. § 1.550(c). See 37 C.F.R. § 41.50(f).

AFFIRMED

lv

PATENT OWNER:

POLSINELLI PC
(NDQ REEXAMINATION GROUP)
1000 Louisiana Street
Suite 6400
Houston, TX 77002

THIRD PARTY REQUESTER:

SMITH BALUCH LLP
376 Boylston St
Ste. 401
Boston, MA