Micron Technology, Inc.

Patent Trials and Appeals Board

Mar 2, 2022

2020006311 (P.T.A.B. Mar. 2, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/288,077 10/07/2016 Robert M. Walker 09-0153.01 | MICS:0316-1 9446 52142 7590 03/02/2022 FLETCHER YODER (MICRON TECHNOLOGY, INC.) P.O. BOX 692289 HOUSTON, TX 77269-2289 EXAMINER AHMED, ZUBAIR ART UNIT PAPER NUMBER 2132 NOTIFICATION DATE DELIVERY MODE 03/02/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): Yapp@fyiplaw.com docket@fyiplaw.com manware@fyiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte ROBERT M. WALKER, DAN SKINNER, TODD A. MERRITT, and J. THOMAS PAWLOWSKI ____________________ Appeal 2020 -006311 Application No. 15/288,0771 Technology Center 2100 ____________________ Before MAHSHID D. SAADAT, MARC S. HOFF, and ELENI MANTIS MERCADER, Administrative Patent Judges. HOFF, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellant appeals under 35 U.S.C. § 134(a) from a Final Rejection of claims 1-19 and 21.2 We have jurisdiction under 35 U.S.C. § 6(b). We reverse. Appellant’s invention is a memory device having internal processors. A memory array may have first, second, and third internal processors embedded thereon. The first internal processor is configured to execute at 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant states that the real parties in interest are Micron Technology, Inc. and Micron Semiconductor Product, Inc. Appeal Br. 2. 2 Claim 20 has been cancelled. Appeal 2020-006311 Application No. 15/288,077 2 least part of an instruction on data stored in the memory array. Data is transferrable from the memory array, from the second internal processor of the memory. Processing results are transferrable to a third internal processor of the memory array and stored in the memory array. The memory device further comprises a sequencer configured to sequence instructions sent by an external processor to the memory array. Claim 1 is reproduced below: 1. A memory comprising: a memory array; a first internal processor, a second internal processor, and a third internal processor of the memory embedded on the memory array, wherein the first internal processor is configured to execute at least part of an instruction on data stored in the memory array to produce results, wherein the data is transferrable from the memory array and transferrable from the second internal processor of the memory, and wherein the results are transferrable to a third internal processor of the memory and stored in the memory array; and a sequencer configured to sequence instructions sent by an external processor to the memory array. The prior art relied upon by the Examiner as evidence is: Jeff Draper et al., The Architecture of the DIVA Processing-In- Memory Chip, ICS’02, pp. 14-26, June 2002 (Draper). Claims 1, 4-9, and 21 stand rejected under 35 U.S.C. § 102(b) as being anticipated by Draper. Claims 2, 3, and 10-193 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Draper. 3 The Appeal Brief erroneously refers to claim 20 as standing rejected. Appeal Br. 5. Claim 20 was previously cancelled. Appeal 2020-006311 Application No. 15/288,077 3 Throughout this decision, we make reference to the Appeal Brief (“Appeal Br.,” filed June 8, 2020), the Reply Brief (“Reply Br.,” filed September 9, 2020), and the Examiner’s Answer (“Ans.,” mailed July 10, 2020) for their respective details. ISSUES 1. Does Draper teach transferring processing results produced in a first internal processor to a third internal processor, and storing the results in the memory array? 2. Does Draper teach a sequencer configured to sequence instructions sent by an external processor to the memory array? 3. Does Draper teach or suggest transferring the first result from the first internal processor to a second internal processor via a coupling between a first memory component coupled to the first internal processor and a second memory component coupled to the second internal processor? ANALYSIS Claims 1, 4-9, and 21 Independent claim 1 recites, in pertinent part, a first internal processor, second internal processor, and third internal processor all embedded on a memory array. The first internal processor is “configured to execute at least part of an instruction on data stored in the memory array to produce results.” Said results are “transferrable to a third internal processor of the memory and stored in the memory array.” Claim 1 further recites “a sequencer configured to sequence instructions sent by an external processor.” The Examiner finds that the pipelined execution unit of Draper corresponds to the claimed “first internal processor.” Final Act. 5 (emphasis Appeal 2020-006311 Application No. 15/288,077 4 omitted). The Examiner finds that Draper’s scalar datapath corresponds to the claimed “second internal processor.” Final Act. 6 (emphasis omitted). The Examiner then maps Draper’s wide-word datapath to the claimed “third internal processor.” Id. (emphasis omitted). Appellant argues that in Draper, no results from the pipelined execution unit (1st internal processor) are transferred to the wideword data path (3rd internal processor). Appeal Br. 7. Figure 4 of Draper shows the major control and data connections within a Data Intensive Architecture Processing-In-Memory (DIVA PIM) node. Draper p. 16. Appellant argues that Draper does not teach that results of the pipelined execution unit (1st internal processor) are transferrable to the Appeal 2020-006311 Application No. 15/288,077 5 wideword datapath (3rd internal processor). Appeal Br. 7. According to Appellant, Draper Figure 3 “shows that . . . no results from [the pipelined execution unit] are transferred to the wideword data path. Instead, only address information/control information . . . and not data, transfers from the pipelined execution control unit to the wideword datapath.” Id. In the Answer, the Examiner responds to Appellant’s arguments by citing to the Specification in support of the Examiner’s finding of the broadest reasonable interpretation of “internal processor,” as a “processor packaged with a memory device,” and that such an internal processor may comprise one or more ALUs. Ans. 4-5. The Examiner then cites to Draper to support a finding that “the result of an operation carried out in the WideWord datapath is transferred to a register in the scalar datapath.” Ans. 5-6. The Examiner characterizes this finding as Draper teaching the claimed “wherein the results are transferrable to a third internal processor.” Id. We do not agree with the Examiner that this response answers Appellant’s arguments. First, the Examiner has not set forth any clear re- interpretation of Draper with regard to the three internal processors. Consequently, we continue to evaluate the Examiner’s remarks in the context of the mapping expressed in the Final Action. Second, the Examiner’s response in the Answer does not reference any results being transferred to the wideword datapath (mapped by the Examiner to the “third internal processor”). Third, the Examiner’s reference to a result from the wideword datapath (third internal processor) being transferred to a register in the scalar datapath (second internal processor) is not germane to the claim requirement that results produced by the first internal processor are transferrable to the third internal processor. We determine, then, that Draper Appeal 2020-006311 Application No. 15/288,077 6 does not teach that results are transferrable to a third internal processor of the memory, as claim 1 requires. The Examiner finds that the parcel buffer (PBUF) of Draper’s DIVA PIM chip corresponds to the claimed sequencer. Final Act. 6. Appellant contends that Draper does not teach a sequencer configured to sequence instructions sent by an external processor to the memory array. Appeal Br. 10. In the Answer, the Examiner finds that “the claimed sequencer was interpreted to mean logic to sequence load and store instructions sent by an external processor as well as buffer the data of the load and store instructions.” Ans. 6. The Examiner finds that Draper teaches a parcel buffer (PBUF). Id. After finding that “[t]he PBUF has a virtual as well as a physical abstraction. To the application, the PBUF locations appear as regular memory locations that are manipulated through simple loads and stores,” the Examiner finds as a consequence that the PBUF “manages or sequences load and store instructions issued by the external host and ‘parcel activity initiated by the host appear as conventional memory accesses from the host perspective.’” Ans. 6; Draper p. 16. We agree with Appellant, however, that the Examiner has not presented evidence that Draper’s parcel buffer (PBUF) functions as the claim requires, i.e., to “sequence instructions sent by an external processor to the memory array” (emphasis added). We determine that the Examiner erred in finding that Draper teaches all the limitations of independent claim 1. We will not sustain the Examiner’s § 102(b) rejection of claims 1, 4-9, and 21. Appeal 2020-006311 Application No. 15/288,077 7 Claims 2 and 3 As analyzed supra, we find that Draper does not teach all the limitations of independent claim 1, from which claims 2 and 3 depend. As a result, we determine that the Examiner erred in rejecting dependent claims 2 and 3 as unpatentable over Draper, for the same reasons given with respect to claim 1. We do not sustain the Examiner’s § 103(a) rejection of claims 2 and 3. Claims 10-19 Independent claim 10 recites, in pertinent part, “transferring the first result from the first internal processor to a second internal processor of the plurality via a coupling between a first memory component coupled to the first internal processor and a second memory component coupled to the second internal processor.” Appeal Br. 18. Independent claim 15 recites storing a result from the first internal processor in a first buffer communicatively coupled to the first internal processor, and subsequently transferring that result to a second internal processor which is also communicatively coupled to the first buffer. The Examiner finds that Draper teaches the claimed transferring from first internal processor to second internal processor in that Draper discloses two datapaths (scalar and wideword) in a DIVA PIM node, as discussed supra with reference to claim 1. Ans. 9-10. The Examiner finds that Draper further teaches, via an assembly language example, a computation cooperatively performed by the WideWord datapath and the scalar datapath: via the instruction “mwvs sr10, wr3, 0,” the result of an addition operation stored in register WR3 in the WideWord datapath is moved to the scalar register SR10. Draper Fig. 7; Ans. 10. Appeal 2020-006311 Application No. 15/288,077 8 Appellant argues that this segment of Draper does not teach the claim limitation because Draper does not teach transferring a result “via a coupling between a first memory component . . . and a second memory component.” Reply Br. 4. We agree with Appellant that Draper Figure 7 and its associated discussion contains no explicit discussion of components involved in transferring a result. Draper pp. 18-19. Draper states only that such an “mvws sr, wr, i” instruction “copies the contents of sr to immediate i field of wr,” without further explaining the mechanism of copying. Draper p. 18. Draper further teaches that the “scalar datapath is a standard RISC architecture” and that “[t]he WideWord datapath accesses the scalar registers for addressing operations. . . . Special instructions permit direct transfers between register files without going through memory.” Draper p. 16. We agree with Appellant that any such transfer between register files of the scalar datapath and the WideWord datapath necessarily does not involve the claimed “first memory component coupled to the first internal processor and a second memory component coupled to the second internal processor.” Reply Br. 4. The Examiner relies on the same teachings in Draper and the same reasoning with respect to independent claim 15. Appellant similarly argues, and we agree, that Draper does not teach or suggest transferring the first result from a first buffer communicatively coupled to the first internal processor via an internal memory bus to a second internal processor also communicatively coupled to the first buffer. Reply Br. 4. We find that Draper does not teach the claimed first buffer arranged as required by the claim. We further find, as with claim 10, that Draper teaches “direct transfers between register files without going through memory,” which Appeal 2020-006311 Application No. 15/288,077 9 necessarily would not involve any such first buffer coupled to a first internal processor via an internal memory bus. Draper p. 16. Accordingly, we do not sustain the Examiner’s § 103(a) rejection of claims 10-19 over Draper. CONCLUSION 1. Draper does not transfer processing results produced in a first internal processor to a third internal processor, and storing the results in the memory array. 2. Draper does not teach a sequencer configured to sequence instructions sent by an external processor to the memory array. 3. Draper does not teach or suggest transferring the first result from the first internal processor to a second internal processor via a coupling between a first memory component coupled to the first internal processor and a second memory component coupled to the second internal processor. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/ Basis Affirmed Reversed 1, 4-9, 21 102(b) Draper 1, 4-9, 21 2, 3, 10-19 103(a) Draper 2, 3, 10-19 Overall Outcome 1-19, 21 The Examiner’s decision to reject claims 1-19 and 21 is reversed. REVERSED