KONINKLIJKE PHILIPS N.V.

Patent Trials and Appeals Board

Apr 20, 2021

2020000487 (P.T.A.B. Apr. 20, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/316,533 12/06/2016 Marc Anthony Chappo 2013P01901WOUS 1068
24737 7590 04/20/2021
PHILIPS INTELLECTUAL PROPERTY & STANDARDS
465 Columbus Avenue
Suite 340
Valhalla, NY 10595
EXAMINER
MALKOWSKI, KENNETH J
ART UNIT PAPER NUMBER
3667
NOTIFICATION DATE DELIVERY MODE
04/20/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
katelyn.mulroy@philips.com
marianne.fox@philips.com
patti.demichele@Philips.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte MARC ANTHONY CHAPPO and
RAFAEL GOSHEN

____________________

Appeal 2020-000487
Application 15/316,533
Technology Center 3600
____________________

Before JOHNNY A. KUMAR, JUSTIN BUSCH, and
MATTHEW J. McNEILL, Administrative Patent Judges.

KUMAR, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
final rejection of claims 1–3 and 6–13. Claims 4 and 5 have been indicated
as containing allowable subject matter. Final Act. 10, 11. We have
jurisdiction under 35 U.S.C. § 6(b).

We AFFIRM IN PART.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. According to Appellant, Koninklijke Philips N.V. is the
real party in interest. Appeal Br. 2.
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Application 15/316,533

2

Appellants’ Invention
Appellant’s invention relates to an image system detector comprising
a detector tile including a photosensor array, a scintillator array, and an
electronic layer (e.g., an ASIC) with a plurality of individual processing
regions. See Spec.2 ¶¶ 7, 30 and Fig. 2. Each processing region includes its
own electrical reference and bias circuitry. See Spec. ¶ 7 and Fig. 8. In a
disclosed embodiment, one ASIC that has improperly functioning channels
can be diced to produce a reduced channel ASIC with properly functioning
channels. See Spec. ¶32, Fig. 5 and Fig. 14.
Illustrative Claims
Claims 1 and 11, reproduced below, are representative of the subject
matter on appeal.

1. An imaging system detector array comprising:
a detector tile including:
a photosensor array including a plurality of
photosensor pixels
a scintillator array optically coupled to the
photosensor array; and
an electronics layer electrically coupled to the
photosensor array, the electronics layer, including:
a plurality of individual processing regions
each processing region including a predetermined
number of channels corresponding to a sub-set of
the plurality of photosensor pixels, wherein the
processing regions are in electrical communication
with each other, and each processing region
includes its own electrical reference and bias
circuitry.

2 We refer to Appellant’s Published Specification, Application No.
2017/0186807 A1 published on June 29, 2017.
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11. The imaging system detector array of claim 1,
wherein the electronics layer is a sub-portion of a
fabricated die having both functional and non-functional
channels, wherein the electronics layer includes the functional
channels and does not include the non-functional channels of
the fabricated die.

REFERENCES AND REJECTIONS

Claim 11 is rejected under 35 U.S.C. § 112(b) as being indefinite for
failing to particularly point out and distinctly claim the subject matter. Final
Act. 4.
Claim 11 is rejected under 35 U.S.C. § 112(a) as failing to comply
with the enablement requirement. Final Act. 4.
Claims 1, 2, 7–10 and 13 are rejected under 35 U.S.C. § 103 as being
unpatentable over Chappo (US 6,510,195 B1, issued Jan. 21, 2003)
in view of Reitz (US 2014/0185781 A1, published July 3, 2014). Final Act.
5.
Claims 3 and 6 are rejected under 35 U.S.C. § 103 as being
unpatentable over Chappo, Reitz and further in view of Luhta (WO
2013/164717 A1, published Nov. 7, 2013). Final Act. 8.
Claim 12 is rejected under 35 U.S.C. § 103 as being unpatentable over
Chappo, Reitz, and further in view of Vrettos (US 6,671,345 B2, issued Dec.
30, 2003). Final Act. 10.
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Appellant’s Contentions3
1. Appellant contends that the Examiner erred in rejecting claim
11 under 35 U.S.C. § 112(b) because the electronics layer shown in Fig. 2 of
the Specification is a sub-portion of a fabricated die having both functional
and improperly functioning channels. Appeal Br. 4.
2. Appellant contends that the Examiner erred in rejecting claim
11 under 35 U.S.C. § 112(a) because as set forth in the Specification, with
reference to Fig. 2, the Specification describes “the electronics layer is a
sub-portion of a fabricated die having both functional and improperly
functioning channels, wherein the electronics layer includes the functional
channels and does not include the improperly functioning channels of the
fabricated die.” Id. at 3.
3. Appellant contends that the Examiner erred in rejecting claims
1, 2, 7–10 and 13 under 35 U.S.C. § 103(a), because the combination of
Chappo and Reitz fails to establish a prima facie case of obviousness with
respect to the required limitation “each processing region includes its own
electrical reference and bias circuitry” of independent claim 1. Id. at 5–7.

Issues
Did the Examiner err in rejecting claim 11 under 35 U.S.C. § 112(b)
as being indefinite because the Specification does not sufficiently describe
the argued limitations?

3 Throughout this Decision, we refer to the Appeal Brief filed March 8, 2019
(“Appeal Br.”); the Reply Brief filed October 29, 2019 (“Reply Br.”); Final
Office Action mailed October 17, 2018 (“Final Act.”); and the Examiner’s
Answer mailed August 30, 2019 (“Ans.”).
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Did the Examiner err in rejecting claim 11 under 35 U.S.C. § 112(a)
as being not enabled because Appellant fails to prove the argued limitations
could be accomplished by one of ordinary skill in the art without undue
experimentation?
Did the Examiner err in rejecting claim 1 under 35 U.S.C. § 103(a) as
being obvious because the combination of Chappo and Reitz fails to teach or
suggest the argued limitations?
Analysis
35 U.S.C. § 112(b) Rejection of Claim 11

The Examiner rejects claim 11 under 35 U.S.C. § 112(b), as “being
indefinite.” Final Act. 4. The Examiner points to paragraphs 37, 39 and 45 of
the Specification, and finds “‘sub-portions’ exclusively refers to the state of
an electronics layer and fabrication die prior to dicing and prior to being
implemented into a detector tile or imaging array.” Ans. 4.
The Examiner determines “[a]s shown in FIG. 14, a fabricated die
with ‘sub-portions’ must be diced or divided and have improperly
functioning channels removed at step 1404 prior to being implemented into a
detector array of an imaging system at step 1406.” Id. The Examiner
concludes that Fig. 2 shows a detector tile with fully functional reduced
channel ASIC rather than an electronic layer 214 that is a sub-portion of a
fabricated die with improperly functioning channels. Id.
However, Appellant points to Fig. 2 of the Specification, and contends
“the electronics layer 214 shown in Fig. 2 is indeed a sub-portion of a
fabricated die having both functional and improperly functioning channels.”
Appeal Br. 4. Appellant further argues that claim 11 does not require the
sub-portion to include any improperly functioning channels, but rather an
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electrical layer that does not include the improperly functioning channels of
the fabricated die. Id.
Paragraphs 37, 39, and 45, and Figures 4 and 5 of the Specification, as
relied upon by the Examiner (Ans. 4), are reproduced below. Appellant
provides support for the argument with Figure 2, which is also reproduced
below.

FIG. 4 shows the ASIC 218 of FIG. 3 for N=M=2. In FIG. 4,
each of the processing regions 3021, 3022, 3023, and 3024
includes an array of J channels 402 (where J is a positive
integer) and a sub-portion 404 of a common digital region 406
and a sub-portion 408 of a common analog region 410. The
dividing regions 304 are within the common digital region 406
and the common analog region 410.
Spec. ¶ 37.

In FIG. 5, the ASIC 218 is diced within the dividing regions
304. The single modular ASIC 218, prior to dicing, included
four processing regions 302, each with J channels, providing 4J
channels for a 4J photosensor pixel array. The diced processing
region 3021 provides J channels for a J pixel photosensor pixel
array. The remainder of the single modular ASIC 218 can be
used with a 3J pixel photosensor pixel array or further diced to
provide three more J channel ASICs or another J channel ASIC
and a 2J channel ASIC.
Spec. ¶ 39.

FIG. 12 shows a variation of the ASIC 218 of FIG. 4 in which
the processing regions 302 are located between (i.e.,
sandwiched by) first and second sub-portions 12021 and 12022
of the digital region 406, instead of the digital circuitry 406
being between (i.e., sandwich by) the processing regions 302.
Spec. ¶ 45.

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FIG. 2 illustrates an example detector tile that includes the single
modular ASIC 214 as the electronics layer.

FIG. 4 illustrates an example of the single modular ASIC with a sub-
portion 404 of a common digital region 406 and a sub-portion 408 of a
common analog region 410.

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FIG. 5 illustrates an example of dicing a reduced channel ASIC from
the single modular ASIC of FIG. 4.
At the outset, we give pending claims “their broadest reasonable
interpretation consistent with the [S]pecification” and “in light of the
[S]pecification as it would be interpreted by one of ordinary skill in the art.”
See Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). We
note indefiniteness under 35 U.S.C. § 112(b) is an issue of claim
construction and a question of law that our reviewing court reviews de novo.
See Cordis Corp. v. Boston Scientific Corp., 561 F.3d 1319, 1331 (Fed. Cir.
2009) (citing Praxair, Inc. v. ATMI, Inc., 543 F.3d 1306, 1319 (Fed. Cir.
2008)).
Here, the indefiniteness rejection for claim 11 appears to be based
essentially upon the Examiner’s own understanding of the claim term “sub-
portion” (“of a fabricated die having both functional and non-functional
channels”) irrespective of the context provided by Appellant’s Specification
and claims.
We see no language that is indefinite in Appellant’s claim 11
regarding the sub-portion limitations because “[b]readth is not
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indefiniteness.” SmithKline Beecham Corp. v. Apotex Corp., 403 F.3d 1331,
1341 (Fed. Cir. 2005) (citing In re Gardner, 427 F.2d 786, 788 (CCPA
1970). The fact that a claim is broad does not mean that it is indefinite, that
is, undue breadth is not indefiniteness. In re Johnson, 558 F.2d 1008, 1016
n.17 (CCPA 1977); In re Miller, 441 F.2d 689, 693 (CCPA 1971). See
MPEP § 2173.04 (“Breadth Is Not Indefiniteness”).
In the Specification, Appellant describes the sub-portion 408 in Figure
4 without referring to a state prior to dicing. See Spec. ¶ 37. In addition,
when illustrating an embodiment of the disclosed approach, Figure 5 of the
Specification shows that a part of the ASIC 3022 is labeled as the sub-
portion 408 after dicing off the 3021. See Appellant’s Fig. 5.
Next, Appellant describes that the electronics layer with only fully
functional channels is formed after dicing the non-functional channels out of
the fabricated die having both functional and non-functional channels. See
Spec. ¶¶ 47–51. In other words, the combination of claim 1 and claim 11
only requires the electronics layer with only functional channels to be in
the imaging system detector, but not a fabricated die having both functional
and improperly functioning channels to be in the imaging system detector
(emphasis added).
For the above reasons, we agree with Appellant that Figure 2 of the
Specification sufficiently describes claim 11 and discloses “the electronics
layer is a sub-portion of a fabricated die having both functional and
improperly functioning channels, wherein the electronics layer includes the
functional channels and does not include the improperly functioning
channels of the fabricated die.”
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We note the Examiner has not considered the aforementioned portions
of the Specification that provide context, as a matter of claim construction.
Nor has the Examiner fully developed the record to apply a lower threshold
of indefiniteness in accordance with the broadest reasonable interpretation
consistent with the Specification, as applied during patent examination. See
Ex parte Miyazaki, 89 USPQ2d 1207, 1212 (BPAI 2008) (precedential); Ex
parte McAward, Appeal 2015-006416, 2017 WL 3669566, at *5 (PTAB
Aug. 25, 2017) (precedential); see also In re Packard, 751 F.3d 1307, 1310,
1314 (Fed. Cir. 2014). See infra, n.3 (We give the contested claim
limitations the broadest reasonable interpretation consistent with the
Specification.).
Accordingly, for essentially the same reasons argued by Appellant in
the Appeal Brief, as further discussed above, we are constrained on this
record to reverse the Examiner’s Rejection of claims 11 under 35 U.S.C.
§ 112(b).

35 U.S.C. § 112(a) Rejection of Claim 11

The Examiner rejects claim 11 under 35 U.S.C. § 112(a), as
containing “subject matter which was not described in the specification in
such a way as to enable one skilled in the art . . . to make and/or use the
invention.” Final Act. 4–5.
In particular, the Examiner finds that claim 11 does not satisfy the
enablement requirement because:
the combination of claim 1 and 11 require a logical
inconsistency of a diced detector tile in a functional imaging
system which ‘is a sub-portion of a fabricated die,’ that has not
yet been diced since the specification exclusively refers to ‘sub-
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portions’ as the state of an electronics layer and fabricated die
prior to dicing and prior to being implemented into a detector
tile or imaging array.
Ans. 8.
Appellant presents arguments asserting the § 112, first paragraph
enablement rejection should be withdrawn (Appeal Br. 3) similar to the
arguments asserted for the § 112(b) indefiniteness rejection.
For the same reasons as discussed above with respect to the § 112(b)
rejection, we find that the Examiner erred in finding the “sub-portion” as a
state of an electronic layer and fabricated die prior to dicing and prior to
being implemented into a detector tile, and Appellant discloses the electronic
layer with fully functional reduced channel ASIC in Figure 2 of the
Specification.
Accordingly, we agree with Appellant, and we reverse the § 112 first
paragraph enablement rejection for the same reasons discussed supra.

35 U.S.C. § 103(a) Rejection of Exemplary Claim 14

We have reviewed the Examiner’s rejections in light of Appellant’s
arguments that the Examiner has erred. We disagree with Appellant’s
conclusions. The Examiner has provided a comprehensive response,
supported by sufficient evidence, to each of the contentions raised by
Appellant. We adopt as our own the findings and reasons set forth by the
Examiner in the Answer in response to Appellant’s Appeal Brief (see

4 Claims 2, 3, 6–10, 12, and 13 are not argued separately from claim 1 in
either of Appellant’s briefs and will not be separately addressed.
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Ans. 9–12). However, we highlight and address specific findings and
arguments for emphasis as follows.
Appellant contends that the combination of Chappo and Reitz does
not teach “each processing region includes its own electrical reference and
bias circuitry,” (hereinafter disputed limitation) because:
[C]laim 1 requires an indirect conversion
scintillator/photodiode detector. Reitz does not disclose or
suggest that the discriminator threshold of a discriminator that
processes pulses generated by direct conversion material (CdTe
or CZT) of a direct conversion counting detector is capable of
being used as any electrical reference or bias circuitry of an
indirect conversion scintillator/photodiode detector.
Appeal Br. 5, 6 (emphasis added).
The Examiner determines that Chappo in combination with Reitz
teaches the disputed limitation. Final Act. 5–7. In particular, the Examiner
relies on Chappo to teach an indirect conversion scintillator/photodiode
detector with a plurality of processing regions with their own electrical
reference. Ans. 10. The Examiner relies upon Reitz to teach a plurality of
individual processing regions with electrical reference circuitry in electrical
communication with each other. Id. Furthermore, the Examiner determines
that Figure 6 of Reitz teaches a plurality of counting pixel elements, where
each of the counting pixel elements requires a threshold value, which is
equivalent to the electrical reference required in claim 1. Final Act. 6–7.
We note that Reitz teaches the threshold value is used in counting
pixel elements of the direct conversion counting detector. Reitz ¶¶ 6, 7.
Appellant discloses the indirect conversion scintillator/photo diode detector
also requires a pixel count detector. Spec. ¶ 6.
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Thus, because both the direct conversion counting detector in Reitz
and the indirect conversion scintillator/photo diode detector in Appellant’s
Specification require the pixel counting elements, the discriminator
threshold of the discriminator of the direct conversion counting detector in
Reitz is capable of being used in the indirect conversion scintillator/photo
diode detector disclosed by Appellant. Therefore, we are not persuaded by
Appellant’s argument that “Reitz does not disclose or suggest that the
discriminator threshold of a discriminator that processes pulses generated by
direct conversion material (CdTe or CZT) of a direct conversion counting
detector is capable of being used as any electrical reference or bias circuitry
of an indirect conversion scintillator/photodiode detector” Appeal Br. 6
(emphasis added).
We find no error in Examiner’s reliance on Reitz, in combination with
Chappo, for teaching or suggesting “each processing region includes its own
electrical reference and bias circuitry,” as recited in claim 1. Appellant’s
arguments are not persuasive because they do not take into account what the
collective teachings of the prior art would have suggested to one of ordinary
skill in the art and are therefore ineffective to rebut the Examiner’s prima
facie case of obviousness. See In re Keller, 642 F.2d 413, 425 (CCPA 1981)
(“The test for obviousness is not whether the features of a secondary
reference may be bodily incorporated into the structure of the primary
reference; nor is it that the claimed invention must be expressly suggested in
any one or all of the references. Rather, the test is what the combined
teachings of the references would have suggested to those of ordinary skill
in the art.” (Citations omitted)). In this case, Chappo teaches the
scintillator/photodiode detector. Ans. 9.
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Based on this record, we are not persuaded of error in the Examiner’s
rejection of independent claim 1, and claims 2, 7–10 and 13 falling therewith
(Appeal Br. 5) over Chappo and Reitz. Appellant does not provide
arguments for the other pending claims, accordingly, we also affirm the
rejection of claims 3 and 6 over Chappo, Reitz, and Luhta and the rejection
of claim 12 over Chappo, Reitz, and Vrettos.

CONCLUSION

The Examiner erred with respect to the rejection of claim 11 under 35
U.S.C. §§ 112(a) and (b).
The Examiner did not err in rejecting claims 1–3, 6–10, 12, and 13
under 35 U.S.C. § 103 over the combined teachings and suggestions of the
cited references.
DECISION

In summary:
Claims
Rejected
35
U.S.C. §
Reference(s)/Basis Affirmed Reversed
11 112(a)

Enablement 11
11 112(b)

Indefiniteness 11
1, 2, 7–10,
13
103 Chappo, Reitz 1, 2, 7–10,
13

3, 6 103 Chappo, Reitz,
Luhta
3, 6
12 103 Chappo, Reitz,
Vrettos
12
Overall
Outcome
1–3, 6–10,
12, 13
11

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See
37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED IN PART