Infineon Technologies Americas Corp.

Patent Trials and Appeals Board

Aug 28, 2020

15389974 - (D) (P.T.A.B. Aug. 28, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/389,974 12/23/2016 Eung San Cho 1486-091US01/2016P51658US 4773
113771 7590 08/28/2020
Shumaker & Sieffert, P.A.
Infineon Technologies AG
1625 Radio Drive
Suite 100
Woodbury, MN 55125
EXAMINER
GONDARENKO, NATALIA A
ART UNIT PAPER NUMBER
2891
NOTIFICATION DATE DELIVERY MODE
08/28/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
pairdocketing@ssiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte EUNG SAN CHO
Appeal 2019-006198
Application 15/389,974
Technology Center 2800
Before JEFFREY B. ROBERTSON, JAMES C. HOUSEL, and
CHRISTOPHER C. KENNEDY, Administrative Patent Judges.
ROBERTSON, Administrative Patent Judge.
DECISION ON APPEAL1
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the
Examiner’s decision to reject claims 1–4, 6, 7, 9, and 11–17. Appeal Br. 8.
We have jurisdiction under 35 U.S.C. § 6(b).

1 This Decision includes citations to the following documents: Specification
filed December 23, 2016 (“Spec.”); Non-Final Office Action mailed August
30, 2018 (“Non-Final Act.”); Appeal Brief filed April 30, 2019 (“Appeal
Br.”); Examiner’s Answer mailed June 25, 2019 (“Ans.”); and Reply Brief
filed August 21, 2019 (“Reply Br.”).
2 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as Infineon
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Application 15/389,974

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We affirm.
CLAIMED SUBJECT MATTER
Appellant states the invention relates to a common contact
semiconductor device package. Spec. ¶ 2. The Specification explains that
the phrase “common contact” conveys that at least two devices of the same
type are coupled to a portion of a semiconductor device package in the same
orientation such that like contacts on a first side of the devices are coupled to
the portion of the semiconductor device package and like contacts on a
second side of the devices extend exposed and are aligned in a particular
orientation. Id. Claim 1, reproduced below, is illustrative of the claimed
subject matter (Appeal Br., Claims Appendix 21):
1. A semiconductor device package comprising:
a conductive clip that includes a recess and that is configured
to mount to a substrate along a first surface and a second surface
that bound the recess, wherein the first surface and the second
surface are aligned with a long axis of the conductive clip; and
at least two vertical transistors including a first transistor and
a second transistor that are of a same type and structural
configuration, and that are mounted within the recess along a
continuous surface and in a same orientation such that a drain or
source contact is electrically coupled to the conductive clip along
the continuous surface, and such that:
a gate contact and a source or drain contact extend exposed
within the recess and along the same long axis of the conductive
clip;
the exposed source or drain contact of the first transistor is
configured to electrically couple to a first switch node trace of a
first half-bridge circuit of a multi-phase circuit on the substrate,

Technologies Americas Corp., which is a subsidiary of Infineon
Technologies AG. Appeal Br. 3.
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and the exposed source or drain contact of the second transistor
is configured to electrically couple to a second switch node trace
of a second half-bridge circuit of the multi-phase circuit on the
substrate, wherein the long axis of the conductive clip is
configured to be perpendicular to a long axis of the first switch
node trace and the second switch node trace, and
wherein the first transistor and the second transistor are both
configured to function as either high side transistors for the first
half-bridge circuit and the second half-bridge circuit or as a low-
side transistors for the first half-bridge circuit and the second
half-bridge circuit.

Claim 6 is also independent and recites a system including a first
semiconductor package and a second semiconductor package each having
conductive clips and transistors. Id. at 22–24.
REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Kusase et al.
(hereinafter
“Kusase”)
US 5,543,703 August 6, 1996
Nishiura et al.
(hereinafter
“Nishiura”)
US 6,114,826 September 5, 2000
Joshi US 6,489,678 B1 December 3, 2002
Standing US 6,677,669 B2 January 13, 2004
Lu et al.
(hereinafter “Lu”)
US 2011/0101511 A1 May 5, 2011
Li et al.
(hereinafter
“Li’458”)
US 2015/0069458 A1 March 12, 2015
LI et al.
(hereinafter
“LI’324”)
US 2016/0336324 A1 November 17, 2016
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REJECTIONS
1. The Examiner rejected claims 1–4 under 35 U.S.C. § 103 as
unpatentable over Standing and Kusase. Non-Final Act. 2–6.
2. The Examiner rejected claims 6 and 7 under 35 U.S.C. § 103 as
unpatentable over Standing, Lu, and Kusase. Non-Final Act. 6–13.
3. The Examiner rejected claims 6, 7, and 9 under 35 U.S.C. § 103 as
unpatentable over Joshi, Lu, and Kusase. Non-Final Act. 13–19.
4. The Examiner rejected claims 11–14, and 17 under 35 U.S.C.
§ 103 as unpatentable over Joshi, Lu, Kusase, and Nishiura. Non-
Final Act. 19–21.
5. The Examiner rejected claims 15 and 16 under 35 U.S.C. § 103 as
unpatentable over Joshi, Lu, Kusase, Li’458, and LI’324.3 Non-
Final Act. 21–22.

OPINION
Rejection 1
Appellant does not present separate arguments with respect to claims
1–4 subject to Rejection 1. See Appeal Br. 13. We select claim 1 as
representative for disposition of this rejection, with the patentability of the
other claims standing or falling with claim 1. 37 C.F.R. § 41.37(c)(1)(iv).

3 Appellant and the Examiner refer to Li’458 as “Li” and LI’324 as “Li
‘324.” Appeal Br. 19; Non-Final Act. 21.
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The Examiner’s Rejection
In rejecting claim 1 as obvious over Standing and Kusase, the
Examiner found Standing discloses a semiconductor device package
comprising a conductive clip having a recess including a first and second
transistor with a gate contact and a source contact. Non-Final Act. 2–3. The
Examiner found Standing does not disclose the exposed source or drain
contact of the first transistor is configured to electrically couple to a first
switch node trace of a first half-bridge circuit of a multi-phase circuit and the
exposed source or drain contact of the second transistor is configured to
electrically couple to a second switch node trace of a second half-bridge
circuit of the multi-phase circuit, wherein the long axis of the conductive
clip is configured to be perpendicular to a long axis of the first switch node
trace and the second switch node trace. Id. at 3–4.
The Examiner found Kusase discloses a three-phase semiconductor
circuit having the connection arrangement between transistors switch node
traces recited in claim 1. Id. at 4.
The Examiner determined it would have been obvious to have
modified the semiconductor device package of Standing by forming a three-
phase semiconductor circuit comprising a half-bridge circuit as taught by
Kusase using the conductive clip of Standing, where the conductive clip is
configured to be perpendicular to a long axis of the first switch node trace
and the second switch node trace also in order to, inter alia, “provide [a]
common connector for three semiconductor devices to simplify an assembly
with the circuit and to provide protection of the semiconductor devices
against environmental elements.” Id. at 5, citing Standing, col. 1, ll. 8–31,
col. 2, ll. 21–33, col. 4, ll. 30–33.
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Appellant’s Contentions
Appellant argues Kusase does not disclose any physical structure
between common drain and common source transistors, and that Figures 1
and 6 of Kusase are schematic diagrams disclosing electrical connections
that may be implemented in a wide variety of possible structural
arrangements. Appeal Br. 11–12. Therefore, Appellant argues the
Examiner has not shown where the long axis of the conductive clip is
configured to be perpendicular to a long axis of the first switch node trace
and the second switch node trace as recited in claim 1. Id. at 12. Appellant
argues the Examiner has not provided a sufficient reason to modify the
disclosure of Standing with Kusase, because Standing already discloses an
outer clip that serves as a housing and a common connector, such that one
would not have a reason to modify Standing to provide protection against
environmental elements or simplify an assembly. Id. Appellant contends
modifying Standing in view of the teachings in Kusase would not arrive at a
gate contact and a drain contact that extend exposed within the recess and
along the same long axis of the conductive clip as required by the claims.
Id. at 12–13.

Issue
The dispositive issue with respect to this rejection is:
Did the Examiner err in determining the semiconductor device
package having a conductive clip with the structural features recited in
claim 1 would have been obvious over Standing and Kusase?
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Discussion
We are not persuaded by Appellant’s arguments that Kusase fails to
suggest configuring the long axis of the conductive clip disclosed in
Standing to be perpendicular to a long axis of a first switch node trace and a
second switch node trace as recited in claim 1. In responding to a prima
facie case of obviousness, one cannot show nonobviousness by attacking
references individually where the rejections are based on combinations of
references. In re Keller, 642 F.2d 413, 426 (CCPA 1981); In re Merck &
Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986). Appellant fails to
appreciate the Examiner’s rejection as to what the prior art as a whole would
convey to one of ordinary skill in the art as further explained below.
Although Appellant contends Kusase discloses only schematic
diagrams of electrical connections, Appellant acknowledges that the
plurality of electrical connections in Kusase “may be physically
implemented with a wide possibility of possible structural arrangements.”
Appeal Br. 11–12. Appellant acknowledges also that “[t]ransistors 19 may
be stacked on different layers or arranged in any other manner to fit the
needs of the application.” Reply Br. 6. The Examiner’s rationale is
consistent with this understanding as it provides express reasoning why one
of ordinary skill in the art would have applied a perpendicular arrangement
for the switch node traces as recited in claim 1 out of other possible
structural configurations, namely to minimize the length of the traces and
occupy less space on the circuit board. Ans. 5, 7.
Indeed, it appears that the clips disclosed in Standing, by virtue of the
similarity in structure of the semiconductor device packages including
transistors disclosed therein and those in the instant Specification, would be
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“configured to electrically couple” to first switch node trace and a second
node trace as recited in claim 1 as well as being “configured to function” as
high side transistors or low side transistors in a first half-bridge circuit and a
second half-bridge circuit. Standing, col. 4, ll. 15–40, Figs. 5–6; Spec. Figs.
2–4.
Thus, Appellant’s argument that one of ordinary skill in the art would
not have interpreted the disclosure in Kusase to include arrangements where
the long axis of the conductive clip disclosed in Standing is configured to be
perpendicular to a long axis of a first switch node trace and a second switch
node trace is not sufficient to demonstrate reversible error in the Examiner’s
rationale. In this regard, Appellant’s argument that the Examiner is relying
on an inherency theory with respect to the teachings of Kusase (Reply Br. 6),
is misplaced. The Examiner does not rely on inherency, but provides
reasoning as to why one of ordinary skill in the art would have selected the
particular arrangement recited in claim 1 as discussed above. See Ans. 6.
As to Appellant’s second argument that the Examiner has not
provided sufficient reasoning to combine Standing and Kusase, we are of the
view that Appellant unduly focuses on the individual teachings of each
reference rather than the rejection as a whole. In particular Appellant’s
contention that Standing already discloses outer clip 12 is useful as a
housing such that it would not have been obvious to have combined
Standing and Kusase to provide protection against environmental elements
or to simplify an assembly as alleged by the Examiner (Appeal Br. 12) fails
to appreciate the Examiner’s rejection. As explained by the Examiner, it is
Standing’s disclosure that is relied upon for disclosing a compact package
for use in the three-phase semiconductor circuit of Kusase, in order to
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provide for protection against environmental elements. Non-Final Act. 5;
Ans. 7; Standing, col. 1, ll. 28–31; col. 2, ll. 21–32. The Examiner relies on
Standing for the arrangement of the gate contact and drain contact within a
recess and along the same long axis of the conductive clip. Non-Final Act.
3; Ans. 7; Standing, Figs. 5–6, col. 4, ll. 15–20, col. 3, ll. 5–10. The
Examiner’s provided rationale for combining Standing and Kusase is not
inconsistent with the overall disclosure in Kusase, which discloses a multi-
phase semiconductor circuit with high side transistors (19a–19c) and low
side transistors (19d–19f). Kusase, col. 4, ll. 44–60, Fig. 1. Kusase
discloses the transistors (19a–19c) can be fabricated on one chip and the
transistors (19d–19f) can be fabricated on one chip in an integrated half-
bridge circuit. Kusase, col. 9, l. 65 – col. 10, l. 17. Thus, applying the
compact packages of Standing when constructing a half-bridge circuit as in
Kusase is consistent with the objective in Standing to simplify
manufacturing. Standing, col. 1, ll. 25–31.
Therefore, the Examiner has provided sufficient rationale for
combining the co-packaged devices of Standing with the half-bridge circuits
of Kusase in order to arrive at the semiconductor device package recited in
claim 1. Accordingly, we affirm the Examiner’s rejection of claims 1–4 as
obvious over Standing and Kusase.

Rejection 2
Appellant does not present separate arguments with respect to claims
6 and 7 subject to Rejection 2. See Appeal Br. 15–16. We select claim 6 as
representative for disposition of this rejection. 37 C.F.R. § 41.37(c)(1)(iv).

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The Examiner’s Rejection
As discussed above, claim 6 recites a system including a first
semiconductor package and a second semiconductor package each having
conductive clips and transistors with similar structures as recited in claim 1.
In rejecting claim 6 as obvious over Standing, Lu, and Kusase, the
Examiner found Standing discloses a first semiconductor device package,
making similar findings as discussed above with respect to claim 1. Non-
Final Act. 7–8. The Examiner found Standing does not specifically disclose
(1) a system comprising a first semiconductor package with a first transistor
configured to function as a high side transistor and a second semiconductor
package with the limitations recited in claim 6 including a second
conductive clip having a second transistor configured to function as a low
side transistor, and (2) where the first and second conductive clips are
configured to be perpendicular to a long axis of each respective switch node
trace. Id. at 8–9. Regarding (1), the Examiner found Lu discloses a package
including high side FET and low side FET wherein the source contact of one
of the two vertical channel transistors is electrically coupled to the
conductive clip and the gate contact and the drain contact extend within the
recess and along the same long axis of the conductive clip. Id. at 9.
The Examiner determined it would have been obvious to have
modified the package of Standing by forming a first conductive clip
including high-side power transistors and a second conductive clip including
low-side power transistors as disclosed in Lu in order to provide an
improved power semiconductor package using conductive clips for
mechanical protection of the semiconductor device having desired
operational characteristics. Id. at 9–10, citing Lu ¶¶ 1, 6, 7.
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Regarding (2), the Examiner made similar findings with respect to
Kusase as with respect to claim 1. Id. at 10–11, see Non-Final Act. 4. The
Examiner determined it would have been obvious to have modified the
semiconductor device package of Standing and Lu with Kusase to form a
three-phase semiconductor half-bridge circuit as taught by Kusase using
conductive clips of Standing/Lu thus arriving at the system of claim 6. Id. at
11–13.

Appellant’s contentions
Appellant sets forth similar arguments for claim 6 as set forth for
claim 1 with respect to Standing and Kusase (Appeal Br. 14), which we
found unpersuasive as discussed above. Appellant also contends that Lu
discloses different transistors of different types mounted in different
orientations rather than transistors of a same type and structural
configuration, and as a result, one of ordinary skill in the art would not have
applied the teachings of Lu to Standing to arrive at Appellant’s claims.
Appeal Br 14–15. In addition, Appellant contends Lu does not disclose or
suggest a gate contact and a source contact within a recess, and the source
contact of Lu is not exposed nor aligned with a gate contact within the recess
and along the same long axis of the first conductive clip. Id. at 15.

Issue
Did the Examiner err in determining the system recited in claim 6
would have been obvious over Standing, Lu, and Kusase?

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Discussion
We are not persuaded by Appellant’s arguments. As to Appellant’s
argument that Lu fails to disclose transistors of a same type and
configuration, we agree with the Examiner that Appellant is incorrect. Ans.
9. Specifically, as the Examiner explains, Lu discloses two mounting
surfaces (26, 28), where each mounting surface includes one or more
transistors of a same type and structural configuration, e.g., one or more high
side transistors on a first mounting surface (26). Id.; Lu ¶¶ 43, 44, Figs. 1–2.
As to Appellant’s argument that Lu does not disclose or suggest a gate
contact and a source contact extend exposed within a recess and along the
same axis of the first conductive clip, we agree with the Examiner that the
specific embodiment to which Appellant refers (Fig. 11 of Lu) including the
additional die 285 does not have to be incorporated into the structure of the
combined references. Ans. 10. It is well established that the obviousness
inquiry does not ask “whether the references could be physically combined
but whether the claimed inventions are rendered obvious by the teachings of
the prior art as a whole.” In re Etter, 756 F.2d 852, 859 (Fed. Cir. 1985) (en
banc); see also In re Keller, 642 F.2d at 425 (stating “[t]he test for
obviousness is not whether the features of a secondary reference may be
bodily incorporated into the structure of the primary reference”). That is, as
the Examiner correctly explains, Standing and Lu are applied under an
obviousness rationale, with the combination of Standing and Lu disclosing
the recess arrangement recited in claim 6. Ans. 8, 10–11.
In this regard, we are of the view that when the teachings of Standing,
Kusase, and Lu are viewed as whole, one of ordinary skill in the art would
have found it obvious to have applied a first clip having a gate contact and
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source contact exposed within a recess along the same long axis of the first
conductive clip (see Kusase Fig. 1, 19d–19f), as suggested by the
combination of Standing and Lu, and a second clip having a gate contact and
drain contact exposed within a recess along the same long axis of the first
conductive clip (see Kusase Fig. 1, 19a–19c) as suggested by the
combination of Standing and Lu. Standing Figs. 5, 6; col. 4, ll. 15–40, Lu
¶¶ 42, 43; Figs. 2–5, 12–13.
Accordingly, we affirm the Examiner’s rejection of claims 6 and 7 as
obvious over Standing, Lu, and Kusase.

Rejection 3
Appellant does not present separate arguments with respect to claims
6, 7, and 9 subject to Rejection 3. See Appeal Br. 18. We select claim 6 as
representative for disposition of this rejection. 37 C.F.R. 41.37(c)(1)(iv).

The Examiner’s Rejection
In rejecting claim 6 as obvious over Joshi, Lu, and Kusase, the
Examiner found Joshi discloses a system having a first semiconductor
package with a first conductive clip (104, 104-1, 104-2) and a first plurality
of transistors (dies 400-1, 400-24) with drain terminals on the back side of
the MOSFET and source and gate terminals on the front side of the
MOSFET. Non-Final Act. 13, citing Joshi, Figs. 4–6, col. 2, ll. 29–67, cols.

4 The Examiner appears to refer to dies 400-1 and 400-2 as “dies 404-1 and
404-2.” Non-Final Act. 13. As Joshi does not appear to disclose dies
labeled 404-1 and 404-2, we understand that when the Examiner uses the
number “404,” the Examiner is actually referring to dies “400.” See Joshi,
Fig. 4; col. 4, l. 66 – col. 5, l. 2.
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4-5. The Examiner found Joshi discloses a first conductive clip including a
recess formed by the lead frame regions 104-1 and 104-2 and wherein a first
surface and second surface of a first conductive clip are aligned with a long
axis of the first conductive clip. Id. The Examiner found Joshi discloses a
first plurality of transistors including at least two vertical transistors that are
of the same type and structural configuration, which are mounted within the
recess of the first conductive clip in a same orientation such that a drain
contact is electrically coupled to the first conductive clip. Id. at 13–14. The
Examiner found Joshi discloses a top active surface of each die having a
source terminal is co-planar with top surfaces of edges of the lead frame 104
and source terminals are on the top active surfaces of the dies, and solder
balls are provided on top active surfaces of the dies such that a gate contact
and a source contact are exposed within a recess and are along the same long
axis of the first conductive clip. Id. at 14.
The Examiner found that Joshi discloses a second semiconductor
package that includes a second conductive clip, making similar findings with
respect to lead frame 104 and regions 104-3 and 104-4 as well as dies 400-3
and 400-4. Id. at 14–15.
The Examiner found Joshi does not specifically disclose (1) the
second plurality of transistors is mounted such that a source contact is
electrically coupled to the second conductive clip and such that a gate
contact and a drain contact extend exposed within the recess, and (2) the
arrangement of transistors, exposed source contacts of each transistor, and
coupling arrangements between the transistors and switch node traces recited
in claim 6. Id. at 15–16.
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Regarding (1), the Examiner made similar findings with respect to Lu
as discussed above for Rejection 2. Id. at 16, see id. 9. The Examiner
determined it would have been obvious to have modified the package of
Joshi by forming first conductive clip including high-side power transistors
and a second clip including low-side power transistors as taught by Lu to
have a system comprising a second semiconductor package, wherein the
second plurality of transistors is mounted such that a source contact is
electrically coupled to the second conductive clip and such that a gate
contact and a drain contact extend exposed within the recess in order to
provide an improved semiconductor package using conductive clips for
mechanical protection of the semiconductor device having desired
characteristics. Id. at 16.
Regarding (2), the Examiner made similar findings with respect to
Kusase as discussed above with respect to Rejections 1 and 3. Id. at 16–18.
The Examiner determined it would have been obvious to have modified the
semiconductor device package of Joshi and Lu by forming a three-phase
semiconductor circuit comprising a half-bridge circuit as taught by Kusase
using the conductive clips of Joshi/Lu to arrive at the system recited in claim
6 in order to provide an integrated three-phase semiconductor circuit having
excellent efficiency, wherein the power semiconductor transistors of a first
plurality of power transistors and a second plurality of power transistors
have improved breakdown characteristics. Id. at 18–19.

Appellant’s contentions
Appellant contends that Joshi fails to disclose a first conductive clip
with a first plurality of transistors as recited in claim 6, because Joshi
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discloses each lead frame region 104-1, 104-2, 104-3, and 104-4 is an
electrically isolated lead frame region with a single transistor. Appeal Br.
16. Appellant argues also that Joshi does not disclose a plurality of
transistors mounted within a recess of a first conductive clip in a same
orientation as required by claim 6. Id. at 16–17. Appellant also relies on
similar arguments with respect to Lu and Kusase as discussed above with
respect to Rejections 1 and 2, namely that Lu does not disclose at least two
transistors of a same type and structural configuration that is configured to
function as a high side transistor and Kusase does not disclose any physical
structure between common drain and common source transistors in Figures 1
and 6. Id. at 17.

Issue
Did the Examiner err in determining the system recited in claim 6
would have been obvious over Joshi, Lu, and Kusase?

Discussion
We are not persuaded by Appellant’s arguments that Joshi fails to
disclose a first plurality of transistors mounted within a recess of a first
conductive clip. As the Examiner further explains in the Answer, Joshi
teaches that the lead frame regions 104-1 and 104-2 form a first conductive
clip with a first plurality of transistors, dies 400-1 and 400-2, which are
mounted on a continuous surface in the form of base frame 100. Ans. 12.
The Examiner explains that the Specification does not provide a clear
definition of “continuous surface” such that base frame 100 in Joshi (see
Joshi Fig. 1) is interpreted as a continuous surface. Id. In addition, the
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Examiner explained that the claim language “the first conductive clip
includes a recess” does not exclude Joshi’s configuration having two regions
and a recess within each region of the first conductive clip. Id. Appellant
has not sufficiently addressed the Examiner’s rationale, which we find to be
sufficiently supported by the record.5 That is, we agree with the Examiner
that the Specification does not provide an express definition of “continuous
surface,” nor does the Specification exclude situations where a recess may
consist of two regions. Accordingly, we are not persuaded by Appellant’s
argument.
We are also not persuaded by Appellant’s contention that the multi-
chip flip chip package of Joshi does not suggest a plurality of transistors
mounted in a “same orientation” because gate terminals for Q1 and Q2 face
each other and Q3 and Q4 face each other. Appeal Br. 16–17; Joshi Fig. 8.
As the Examiner points out, claim 6 defines “same orientation” of the
mounting arrangement of the transistors in the first conductive clip with
respect to the drain contact of each transistor being electrically coupled to
the first conductive clip and the gate contact and source contact “extend
exposed within the recess and along the same long axis of the first
conductive clip.” Ans. 12. Thus, claim 6 does not exclude arrangements
where gate terminals face each other as disclosed in Joshi, because such gate
terminals are formed on the same side of the transistor and are exposed
along the same axis of the conductive clip, and as result, meet the recitations
of “same orientation” recited in claim 6. Id.; Joshi, Fig. 8.

5 Appellant does not specifically address this position in the Reply Brief.
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In addition, we are not persuaded by Appellant’s arguments regarding
Lu and Kusase largely for similar reasons expressed above with respect to
Rejections 1 and 2. Similar to the discussion above, Appellant’s arguments
do not take into consideration the combination of the prior art as a whole.
See Ans. 13–14.
Accordingly, we affirm the Examiner’s rejection of claims 6, 7, and 9
as obvious over Joshi, Lu, and Kusase.

Rejection 4
Claims 11–14 and 17 all depend from independent claim 6. For the
rejection of claims 11–14, and 17 over Joshi, Lu, Kusase, and Nishiura,
Appellant relies on the arguments made with respect to claim 6 as pertaining
to Rejection 3. Appeal Br. 18–19. Because we did not find these arguments
persuasive as discussed above, we affirm the Examiner’s rejection of claims
11–14 and 17 for similar reasons as discussed above for Rejection 3.

Rejection 5
Claims 15 and 16 depend from claim 6, and recite wherein each one
of the first plurality of transistors or each one of the second plurality of
transistors, respectively “is a vertical fin-based multi-gate transistor.”
Appeal Br. 25.
In rejecting claims 15 and 16 over Joshi, Lu, Kusase, Li’458, and
LI’324, the Examiner found Joshi fails to disclose that the transistors are
vertical fin-based multi-gate transistors. Non-Final Act. 21. The Examiner
found Li’458 discloses packaged semiconductor devices including vertical
field effect fin-based transistors wherein the package includes multiple dies
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on a printed circuit board (Li’458 Figs. 1–9, ¶¶ 23–31, 57, 82–84) and
LI’324 discloses forming optimized vertical fin-type tunnel field effect
transistors (TFET) with a plurality of gate elements (LI’324, Figs. 1–3,
¶¶ 25–68). Id. at 21–22.
The Examiner determined it would have been obvious to further
modify the system of Joshi, Lu, and Kusase by forming a packaged
semiconductor device including vertical field effect fin-based transistors as
taught by Li’458 or LI’324 in order to provide a packaged semiconductor
device having a smaller size using vertical fin-type TFETs that enable
current flow as a result of band-to-band tunneling and to provide a plurality
of gate elements with adjustable width to manage an amount of saturation
current supported by vertical fin-type TFET, and to optimize integration of
vertical fin-type TFETs to increase TFET drivability and increasing the
effective width of the TFET to improve the TFET performance. Id. at 22.
Appellant contends the Examiner has failed to establish Li’458
discloses a “multi-gate transistor” as recited in claims 15 and 16. Appeal Br.
19. Appellant additionally contends the Examiner has not provided a
sufficient reason to modify Joshi with Li’458, because the Examiner did not
provide articulated reasoning with rational underpinning. Id. at 19–20.
We are not persuaded by Appellant’s arguments. Although Appellant
contends Li’458 discloses a vertical TFET device including a first vertical
fin-type TFET 110 and a second vertical fin-type TFET 120 that is separated
by shallow trench isolation 108 as support for the position that Li’458 does
not disclose multi-gate transistors (Appeal Br. 19, see Li’458 ¶ 24, Fig. 1),
the Examiner’s position is that Li’458 discloses multiple dies on a printed
circuit board and LI’324 discloses optimized vertical fin-type TFET with a
Appeal 2019-006198
Application 15/389,974

20
plurality of gate elements. Ans. 15–16. Appellant does not address the
Examiner’s specific findings with respect to Li’458 or sufficiently explain
why the presence of a trench in Li’458 means that the vertical fin-type
TFETs in Li’458 are not multi-gate transistors, nor does Appellant appear to
address the Examiner’s findings with respect to LI’324.
As to Appellant’s arguments that the Examiner has not provided
sufficient rationale to combine Li’458 or LI’324 with Joshi, Appellant
provides only general assertions in this regard and does not address the
Examiner’s specific rationale as discussed above. See Ans. 16.
Accordingly, we are not persuaded by Appellant’s arguments.
As a result, we affirm the Examiner’s rejection of claims 15 and 16.

DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–4 103 Standing, Kusase 1–4
6, 7 103 Standing, Lu,
Kusase
6, 7
6, 7, 9 103 Joshi, Lu, Kusase 6, 7, 9
11–14, 17 103 Joshi, Lu, Kusase,
Nishiura
11–14, 17
15, 16 103 Joshi, Lu, Kusase,
Li’458, LI’324
15, 16
Overall
Outcome
1–4, 6, 7,
9, 11–17

Appeal 2019-006198
Application 15/389,974

21
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED