Imagination Technologies Limited

Patent Trials and Appeals Board

Jan 21, 2022

2021000397 (P.T.A.B. Jan. 21, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/068,899 03/14/2016 Marc Vivet 2645-0257US01 2284 125968 7590 01/21/2022 Potomac Law Group PLLC (IMGTEC) 8229 Boone Boulevard Suite 430 Vienna, VA 22182 EXAMINER DUNPHY, DAVID F ART UNIT PAPER NUMBER 2668 NOTIFICATION DATE DELIVERY MODE 01/21/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): Eofficeaction@appcoll.com Patents@potomaclaw.com vdeluca@potomaclaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte MARC VIVET and PAUL BRASNETT ____________________ Appeal 2021-000397 Application 15/068,899 Technology Center 2600 ____________________ Before ALLEN R. MacDONALD, MICHAEL J. ENGLE, and IFTIKHAR AHMED, Administrative Patent Judges. MacDONALD, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s final rejection of claim 20. Appellant has cancelled claim 7, and claims 1-6 and 8-19 are indicated as allowable. Appeal Br. 1 (Appeal Brief filed June 27, 2020, “Appeal Br.”). We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 Appellant identifies Imagination Technologies Limited as the real party in interest. Appeal Br. 1. Appeal 2021-000397 Application 15/068,899 2 CLAIMED SUBJECT MATTER Claim 20 is the sole claim under appeal and reads as follows (emphasis, formatting, and bracketed material added): 20. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a processing module comprising: [A.] alignment logic configured to: [i.] apply respective transformations to at least some of a set of images to bring them closer to alignment with a reference image from the set of images, [ii.] wherein the transformations are determined using multiple kernel tracking to initialize a Lucas Kanade Inverse algorithm that is used on said at least some of the images to bring them closer to alignment with said reference image; and [B.] combining logic configured to: [i.] combine a plurality of images including said one or more of the transformed images to form a reduced noise image. REJECTION The Examiner rejects claim 20 under 35 U.S.C. § 112(a) as failing to comply with the enablement requirement. Final Act. 10-16 (Final Office Action, mailed January 27, 2020, “Final Act.”). PRINCIPLES OF LAW - WANDS FACTORS Whether undue experimentation is needed is not a single, simple factual determination, but rather is a conclusion reached by weighing many factual considerations. In re Wands, 858 F.2d 731, 737 (Fed. Cir. 1988). Appeal 2021-000397 Application 15/068,899 3 The Wands factors include: (1) the quantity of experimentation necessary, (2) the amount of direction or guidance presented, (3) the presence or absence of working examples, (4) the nature of the invention, (5) the state of the prior art, (6) the relative skill of those in the art, (7) the predictability or unpredictability of the art, and (8) the breadth of the claims. Id. (citations omitted). In reviewing for lack of enablement, the Wands court elected to consider “all of the factors.” Id. at 740. However, it is not necessary to review all the Wands factors to find a disclosure enabling. Rather, the Wands factors “are illustrative, not mandatory” and what is relevant to an enablement determination depends upon the facts of the particular case. See Amgen, Inc. v. Chugai Pharm. Co., 927 F.2d 1200, 1213 (Fed. Cir. 1991); see also Enzo Biochem, Inc. v. Calgene, Inc., 188 F.3d 1362, 1371 (Fed. Cir. 1999); Warner-Lambert Co. v. Teva Pharms. USA, Inc., 418 F.3d 1326, 1337 (Fed. Cir. 2005). PROSECUTION HISTORY Examiner’s Rejection The Examiner rejected claim 20 under 35 U.S.C. § 112(a) by considering the Wands factors. Final Act. 10-16. The Examiner’s analysis corresponds to each of Wands factors (1) through (8). The Examiner determined that all Wands factors, except (8) the breadth of the claim, weighed against enablement. For example, in particular, the Examiner determined: Applicant describes HDL/RTL as, “[m]ethods of determining a circuit layout from an IC definition dataset are known in the art, and for example may involve synthesi[z]ing RTL code to determine a gate level representation of a circuit to be generated, e.g., in terms of logical components (e.g. NAN[D], NOR, AND, Appeal 2021-000397 Application 15/068,899 4 OR, MUX, and FLIP-FLOP components).” (Specification at p. 28, line 10-15)(emphasis added). Indeed, evidence of the state of the prior art indicates that HDL/RTL is limited to such simple logical components as addition, subtraction, AND, OR, and register shifts. See, for example, the HDL operators listed in Table 7.1 of Shiva, “Introduction to Logic Design,” at p. 346. In contrast with the simple logical operations known in the prior art, claim 20 recites complex mathematical operations including “multiple kernel tracking” and the “Lucas Kanade Inverse algorithm.” Multiple kernel tracking requires much more complex operations than mere addition, subtraction, AND, OR, and register shifts, as evidenced by Dewan, “Multiple Kernel Tracking with SSD” at pp. 4-5, sec. 4, which discloses multiple complex convolution operations comprising multiple kernels as well as complex mathematical matrix operations. Lucas Kanade also requires much more complex operations than mere addition, subtraction, AND, OR, and register shifts, as evidenced by Wikipedia, Lucas-Kanade method, which discloses complex mathematical operations including partial derivatives and complex mathematical matrix operations. In summary, multiple kernel tracking and Lucas Kanade include complex mathematical operations that are not supported by the simple addition, subtraction, boolean operations of the RTL/HDL of the prior art. Absent guidance as to how to perform the complex mathematical operations with such simple operands, the evidence of the state of the prior art strongly mitigates against enablement of an actual circuit capable of performing the recited functions. Applicant has provided evidence in the Declaration of Stephen Morphet Under 37 CFR 1.132 of the limited mathematical capabilities of RTL designed circuits. See discussion above for more details. The evidence provided by applicant has been weighed along with all other evidence in making this finding. Final Act. 11-12 (additional emphasis added). Appeal 2021-000397 Application 15/068,899 5 OPINION We have reviewed the Examiner’s rejections in light of Appellant’s Appeal Brief and Reply Brief arguments. 1. First Argument A. Appellant’s First Argument Appellant contends that the Examiner erred in rejecting claim 20 under 35 U.S.C. § 112(a) because “the specification discloses a clear, enabling method of generating a gate-level representation of the IC, which is then used to generate a circuit layout.” Appeal Br. 4. In particular, the specification as filed clearly discloses that “[m]ethods of determining a circuit layout from an IC definition dataset are known in the art, and for example may involve synthesi[z]ing RTL code to determine a gate level representation of a circuit to be generated, e.g., in terms of logical components (e.g. NAND, NOR, AND, OR, MUX, and FLIP- FLOP components).” Specification at p. 28, line 10-15. Thus, the specification discloses a clear, enabling method of generating a gate-level representation of the IC, which is then used to generate a circuit layout. Appeal Br. 4. The rejection . . . appears to contend that “multiple kernel tracking” and the “Lucas Kanade inverse algorithm” of claim 20 cannot be described by RTL/HDL (see Office action at pp.12, 16). This is incorrect. As established by the Declaration and Exhibit 5, Verilog is a rich complex language that enables any mathematical function required of an ASIC to be described. The Declaration further establishes that this contention of the Office action is self-contradictory since it ostensibly requires that the present application provide “a schematic or written description (such as RTL code) of an actual electrical circuit,” (see Office action at para. (b) pages 4 - 5) while simultaneously contending that an ‘actual circuit’ cannot be described using RTL (see Office action at paras. (c) and (d) pages 5 and 6). By contrast, if an ASIC is capable of being described by RTL (as is the present Appeal 2021-000397 Application 15/068,899 6 invention), an ordinarily skilled Hardware Engineer would be able to write such a description using RTL code from a high level functional disclosure such as provided by the present Specification. The Declaration further establishes that this contention does not make logical sense since the claim to the actual integrated circuit (i.e. claim 11) has been accepted by the examiner as being patentable. Since it is undisputed that a person of ordinary skill in the art would be capable of fabricating an actual ASIC from the present application, the same person must also be capable of writing RTL code describing the ASIC, as this is the standard way that ASICs are created in the present day. See Declaration ¶ 8. Appeal Br. 7 (emphasis added). The examiner alleges that multiple kernel tracking and Lucas Kanade include complex mathematical operations, such as partial derivatives and linear algebra matrix operations, that are not supported by the simple addition, subtraction, Boolean operations of the RTL/HDL of the prior art. This is incorrect. The evidence of record shows that an ordinarily skilled hardware engineer, whose job it is to write RTL code when given a high level functional description of a processing module, would be able to write RTL code to implement mathematical operations such as partial derivatives and matrix operations. Indeed, this is confirmed by the multiple prior art patents cited in the main brief, which establish the ability of an ordinarily skilled hardware engineer to write a computer readable description of an integrated circuit from no more than a high level functional description (see in particular prior art U.S. Patent No. 9,886,538, . . .). Reply Br. 5-6. B. Examiner’s Response to Appellant’s First Argument The Examiner responds that Appellant is mistaken: Applicant’s own declarant, Stephen Morphet, has provided evidence in his reference, “Verilog HDL Operators”, that proves that Verilog is only capable of performing very simple and basic arithmetic such as addition, subtraction, multiplication, division. (p. 1, sec. 1, “Arithmetic”). Furthermore, this Appeal 2021-000397 Application 15/068,899 7 declaration was filed in response to an August 2, 2019, office action which found that Verilog was limited to, “such simple logical components as addition, subtraction, AND, OR, and register shifts.” (P. 6, sub. par. c). Applicant was placed on notice that the mathematical limitations of Verilog were at issue, and responded with evidence undermining the enablement of their own invention. This weighs heavily against enablement because in order to practice Applicant’s invention, their module must perform very advanced mathematical operations including, “partial derivatives and linear algebra matrix operations . . . Gaussian function weights, inverse matrices and transposed matrices.” (emphasis added)(Final Rejection dated 27 January 2020, at p. 5, par. 6). Absent undue experimentation, it is not conceivable how the advanced mathematics operations required to implement applicant’s invention could be practiced with the simple addition, subtraction, multiplication and division available on the hardware circuits produced by Verilog. Ans. 12-13. C. Additional Appellant’s First Argument Appellant further argues: The Answer in section 7 states “Applicant’s own declarant, Stephen Morphet, has provided evidence in his reference, ‘Verilog HDL Operators’, that proves that Verilog is only capable of performing very simple and basic arithmetic such as addition, subtraction, multiplication, division.” This is incorrect. As explained above, code written in Verilog is capable of performing much more complicated functions by combining two or more of the Verilog HDL operators. Obviously, RTL code can include more than one operator. The Answer names some functions including “partial derivatives, and linear algebra matrix operations . . . Gaussian function weights, inverse matrices and transposed matrices.” Again, Appellant notes that these functions can be implemented using combinations of Verilog HDL operators (e.g. a matrix multiplication can be performed as a combination of multiplication and addition operations). Reply Br. 11. Appeal 2021-000397 Application 15/068,899 8 2. Second Argument A. Appellant’s Second Argument Also, Appellant contends that the Examiner erred in rejecting claim 20 under 35 U.S.C. § 112(a) because “the specification clearly enables a person skilled in the art to make and use a non-transitory computer readable storage medium, which is the subject matter of claim 20, with no more than routine experimentation at most, if at all.” Appeal Br. 4. [C]laim 20 is not directed to “an electrical circuit.” Claim 20 is drawn to a computer readable storage medium, e.g. a flash drive, DVD, CD, magnetic disk, etc., that has stored on it an IC definition dataset that enables an IC manufacturing system to manufacture an integrated circuit according to the dataset. Appeal Br. 5. As Appellant explained in the prior appeal, claim 20 is thus simply directed to protecting a non-transitory computer readable storage medium product that contains HDL code that causes an IC manufacturing system to manufacture the patentable processing module of claim 11. It is incongruous to assert that a person skilled in the art would not be able to make a computer readable storage medium containing code that enables manufacture of the processing module, when it is acknowledged that such a person is able to make the actual processing module itself, as recited in claim 11 (which stands allowed), from the specification as filed together with the general knowledge in the art. Appeal Br. 6. B. Examiner’s Response to Appellant’s Second Argument The Examiner responds: Claim 11 is irrelevant to claim 20. It is not a circuit produced by the invention of claim 20; prosecution history reveals that claim 11 recites a software embodiment of applicant’s invention unrelated to the hardware embodiment of claim 20. Claim 11 was rejected under 35 U.S.C. § 101 in a 26 June 2017 office action, at par. 8, because it read upon a Appeal 2021-000397 Application 15/068,899 9 computer program per se. In his 26 September 2017 response to that office action, at p. 7, applicant did not deny that claim 11 comprised a computer program. Rather, he added a processor so that the claim no longer read upon a computer program per se. In short, claim 11 is a software embodiment; it comprises a processor programmed to perform the functions of applicant’s invention. Conversely, claim 20 recites the generation of a hardware embodiment to perform the functions of applicant’s invention; i.e., [V]erilog software is used to manufacture hardware circuits and it is the hardware circuits that must be capable of practicing the applicant’s invention. Ans. 13-14. 3. The Third Argument (Declaration Legal Opinions) Appellant contends that the Examiner erred in rejecting claim 20 under 35 U.S.C. § 112(a) because [t]he Declaration establishes that a person of at least ordinary skill in the art would be able to make and use a non- transitory computer readable storage medium as recited in claim 20 from the disclosure provided in the specification and the general knowledge available to those persons who have actual skill in the art, as evidenced by the attached exhibits. Appeal Br. 6. Particularly, Appellant asserts: The Declaration further establishes that a person having ordinary skill in the art would be able to . . . with no more than routine experimentation if at all. See Declaration ¶ 4. Appeal Br. 6-7. [N]ot only is it unnecessary for the specification to provide RTL code to the Hardware Engineer . . . . See Declaration ¶ 6. Appeal Br. 7. Appeal 2021-000397 Application 15/068,899 10 4. The Fourth Argument A. Appellant’s Fourth Argument Appellant contends that the Examiner erred in rejecting claim 20 under 35 U.S.C. § 112(a) because the rejection of claim 20 is contrary to public policy and inconsistent with existing determinations of the office. Appeal Br. 8-12. In particular to this point, Appellant cites co-assigned U.S. Patent No. 9,760,997 (“the ’997 patent”), and claim 18 thereof (which was examined and allowed by the same examiner herein), as evidence that appealed claim 20 is in fact supported by an enabling disclosure: Because the features at issue in the present rejection of claim 20 are the same as the features of claim 18 of the ’997 patent, and the specifications pertaining to such features are the same in the present application and the ’997 patent, the assertions in the final Office action regarding claim 20 of the present application are tantamount to an assertion regarding the validity and/or patentability of claim 18 of the validly issued ’997 patent. Appeal Br. 10. B. Examiner’s Response to Appellant’s Fourth Argument The Examiner responds: This issue was previously addressed by the Patent Trial & Appeal Board on p. 7 of its 22 May 2019 decision. In ruling against the appellant on this issue, the Board cited In re Gyurik, 596 F.2d 1012, 1018 (CCPA 1979), for the proposition that, “we will not consider the allowed claims in other patents when determining whether the present claim is enabled.” Ans. 14. C. Additional Appellant’s Fourth Argument Appellant further argues: Application of Gyurik, 596 F.2d 1012 ([CCPA] 1979) does not stand for the proposition that allowed claims in other patents Appeal 2021-000397 Application 15/068,899 11 cannot be considered when determining issues of enablement under 35 U.S.C. § 112. Reply Br. 12. 5. The Fifth Argument A. Examiner’s Answer - First New Determination In the Answer, as to the level of predictability in the art, the Examiner newly adds to the Answer’s quote of the rejection: The Declarant’s own reference, “Verilog HDL Operators”, proves that Verilog is only capable of performing very simple and basic arithmetic; to wit: addition, subtraction, multiplication, division. (p. 1, sec. 1, “Arithmetic”). The other bitwise operations, such as shift-left, shift-right, AND, XOR, OR, AND, NAND, etc., while suitable for very low-level assembly level programming, do not comprise mathematical operations. In contravention to the basic arithmetic of Verilog, the Lucas- Kanade method requires advanced mathematical operations including partial derivatives and linear algebra matrix operations. See, Wikipedia, Lucas- Kanade method at pp. 1-2. It is implemented with Gaussian function weights, inverse matrices and transposed matrices. Id. Absent undue experimentation, it is not conceivable how the mathematics required to implement applicant’s invention could be practiced with addition, subtraction, multiplication, division, and bitwise[ ]operators. Ans. 6-7. B. Appellant’s Fifth Argument Appellant contends that the Examiner erred in rejecting claim 20 under 35 U.S.C. § 112(a) because: The examiner alleges that multiple kernel tracking and Lucas Kanade include complex mathematical operations, such as partial derivatives and linear algebra matrix operations, that are not supported by the simple addition, subtraction, Boolean operations of the RTL/HDL of the prior art. This is incorrect. The evidence of record shows that an ordinarily skilled hardware Appeal 2021-000397 Application 15/068,899 12 engineer, whose job it is to write RTL code when given a high level functional description of a processing module, would be able to write RTL code to implement mathematical operations such as partial derivatives and matrix operations. Indeed, this is confirmed by the multiple prior art patents cited in the main brief, which establish the ability of an ordinarily skilled hardware engineer to write a computer readable description of an integrated circuit from no more than a high level functional description (see in particular prior art U.S. Patent No. 9,886,538, . . .). Reply Br. 5-6. 6. The Sixth Argument A. Examiner’s Answer - Second New Determination In the Answer, as to the level of predictability in the art, the Examiner newly adds to the Answer’s quote of the rejection: In section 5.2 of the Declaration of Stephen Morphet, in an article entitled, “ASIC Design Flow - an Overview,” Applicant provides evidence that there is unpredictability in art; to wit: “ASIC design flow is not exactly a push button process. To succeed in the ASIC design flow process, one must have: a robust and silicon-proven flow, a good understanding of the chip specifications and constraints, and an absolute domination over the required EDA tools (and their reports!).” (p. 1, par. 1). Moreover, this reference provides evidence that insufficient direction was provided by the inventor, whom provided only a single block in a block diagram in FIG. 10 with a single functional label, “IC definition dataset. ” In contrast to this sparse single block design, declarant’s own reference evidences that a greater deal of complexity is required in the design phase: “In ASIC system design phase, the entire chip functionality is broken down to small pieces with clear understanding about the block implementation. For example: for an encryption block, do you use a CPU or a state machine. Some other large blocks need to be divided into subsystems and the relationship between the various blocks has to be defined. In this phase the working environment is documentation. ” (p. 1, par. 2, “ASIC System Appeal 2021-000397 Application 15/068,899 13 Design”). Overall, the low level of predictability in the art mitigates against enablement. The evidence provided by applicant has been weighed along with all other evidence in making this finding. Ans. 8-9. B. Appellant’s Sixth Argument Appellant contends that the Examiner erred in rejecting claim 20 under 35 U.S.C. § 112(a) because: The Examiner refers to section 5.2 of the Morphet Declaration and suggests that “ASIC Design Flow - an Overview” provides evidence that there is unpredictability in the art. This is incorrect. The steps that are performed for manufacturing an integrated circuit have been fine-tuned over many years of manufacturing integrated circuits, and are very well known in the art. The process of receiving some RTL code defining a processing module and manufacturing the processing module such that it has the functionality defined in the RTL code is so predictable that the Appellant Imagination Technologies Limited has built an entire business on licensing the RTL code to chip manufacturers. If the process involved in manufacturing an integrated circuit when given some RTL code was not predictable, then the Appellant could not have built a business which has been successful for decades. Therefore, it is respectfully submitted that there is an extremely high level of predictability in the art, and that this also mitigates in favor of enablement. Reply Br. 8. ANALYSIS We have reviewed the Examiner’s rejections in light of Appellant’s arguments that the Examiner has erred. We disagree with Appellant’s conclusions. Appeal 2021-000397 Application 15/068,899 14 As a preliminary matter before we address Appellant’s arguments, we note that Appellant states: “the Answer provides particular comment on each of the Wands factors” (Reply Br. 3). This is incorrect. Rather the Answer merely repeats the Wands factor analysis of the Final Action while only adding comments as to two of the factors. Those two new comments and Appellant’s timely arguments thereto are reproduced supra at Sections 5 and 6. However, as to Appellant’s remaining Reply Brief arguments directed to the Wands factors, they present for the first time new arguments against the rejection as presented in the Final Action. These remaining Reply Brief Wands factor arguments are not previously argued in the Appeal Brief, nor are they responsive to findings raised by the Examiner in the Answer. Rather, these are belated arguments that reasonably should have been raised in the original Appeal Brief. In the absence of a showing of good cause by Appellant, we decline to consider an argument raised for the first time in the Reply Brief, as the Examiner has not been provided a chance to respond. See 37 C.F.R. § 41.41(b)(2) (2012); In re Hyatt, 211 F.3d 1367, 1373 (Fed. Cir. 2000) (noting that an argument not first raised in the brief to the Board is waived on appeal); Ex parte Nakashima, 93 USPQ2d 1834, 1837 (BPAI 2010) (informative) (explaining that arguments and evidence not timely presented in the principal brief will not be considered when filed in a reply brief, absent a showing of good cause explaining why the argument could not have been presented in the principal brief); Ex parte Borden, 93 USPQ2d 1473, 1477 (BPAI 2010) (informative) (“Properly interpreted, the Rules do not require the Board to take up a belated argument that has not been addressed Appeal 2021-000397 Application 15/068,899 15 by the Examiner, absent a showing of good cause.”). Appellant has provided no showing of good cause. 1. Analysis of Appellant’s First Argument As to Appellant’s first argument, we disagree. We agree with Appellant to the extent that the record (including the Morphet Declaration) shows (a) the basic Verilog operators (e.g., those shown in “Verilog HDL Operators”) and (b) that they can be combined to perform more complex operations. However, this was not in dispute. Rather, the Examiner’s rejection is premised on lack of enablement of (c) the even more highly complex particular operations required by claim 20 (i.e., complex mathematical operations including “multiple kernel tracking” and the “Lucas Kanade Inverse algorithm”). As the Examiner correctly determines: This weighs heavily against enablement because in order to practice Applicant’s invention, their module must perform very advanced mathematical operations including, “partial derivatives and linear algebra matrix operations . . . Gaussian function weights, inverse matrices and transposed matrices.” . . . (Final Rejection dated 27 January 2020, at p. 5, par. 6). Ans. 13 (emphasis omitted) (quoting Final Act. 5). Our review of the Morphat Declaration finds citation to numerous references (Paragraphs 5.1-5.4) which we agree demonstrate (a) and (b) (which are not in dispute). However, we find those references lacking any demonstration as to the particular highly complex operations of (c). 2. Analysis of Appellant’s Second Argument As to Appellant’s second argument, Appellant argues that: [C]laim 20 is thus simply directed to protecting a non-transitory computer readable storage medium product that contains HDL Appeal 2021-000397 Application 15/068,899 16 code that causes an IC manufacturing system to manufacture the patentable processing module of claim 11. Appeal Br. 6. [C]laim 20 is not directed to “an electrical circuit.” Appeal Br. 5 (emphasis omitted). We are not persuaded of Examiner error. Whereas claim 11 recites a “processing module including a processor and comprising . . . alignment logic configured to” perform various steps (including “a Lucas Kanade Inverse algorithm”), independent claim 20 recites a “computer readable storage medium having stored thereon a computer readable description of an integrated circuit” that can be used “to manufacture [such] a processing module.” Whether a person of ordinary skill in the art would have been enabled to use a “processing module including a processor” to perform a Lucas Kanade Inverse algorithm (as in claim 11) is a different question from whether a person of ordinary skill in the art would have been enabled to create “a computer readable description of an integrated circuit” (e.g., using Verilog or VHDL) for such a processing module. As discussed above, the issue here is that Appellant has not yet shown how the basic HDL operators in Verilog or VHDL enable the claimed complex operations such as a Lucas Kanade Inverse algorithm. 3. Analysis of Appellant’s Third Argument As to Appellant’s third argument covering legal opinions in the Declaration (Paragraphs 4, 6), we disagree. We conclude that paragraphs 4 and 6 of the Declaration are directed to the ultimate legal conclusion at issue and are not entitled to weight. Particularly, we give them no weight as we do not find (for the reasons discussed elsewhere herein) a persuasively supported statement as to the disputed limitations being within the Appeal 2021-000397 Application 15/068,899 17 knowledge of one skilled in the art. Opinion testimony is entitled to consideration and some weight so long as the opinion is not on the ultimate legal conclusion at issue. Although an affiant’s or declarant’s opinion on the ultimate legal issue is not evidence in the case, “some weight ought to be given to a persuasively supported statement of one skilled in the art on what was not obvious to him.” In re Lindell, 385 F.2d 453, 456 (CCPA 1967) (emphasis added). 4. Analysis of Appellant’s Fourth Argument As to Appellant’s fourth argument, we disagree. Appellant asserts that “Application of Gyurik, 596 F.2d 1012 ([CCPA] 1979) does not stand for the proposition that allowed claims in other patents cannot be considered when determining issues of enablement under 35 U.S.C. § 112.” Reply Br. 12. Appellant is mistaken as Gyurik does represent the general rule. In the previous Decision, we determined: The Court of Customs and Patent Appeals, predecessor court to the Court of Appeals for the Federal Circuit, held that “[e]ach case is determined on its own merits. In reviewing specific rejections of specific claims, this court does not consider allowed claims in other applications or patents.” In re Gyurik, 596 F.2d 1012, 1018 n.15 (CCPA 1979) (citations omitted). As our reviewing court directs, we will not consider the allowed claims in other patents when determining whether the present claim is enabled. It follows that this argument does not show the Examiner has erred. Decision 7-8. Among the omitted citations was In re Freedlander, 136 F.2d 759, 760 (CCPA 1943). In Freedlander the court states that this is the general rule: We have many times held that the general rule is that in passing upon the rejection of a claim by the Patent Office we will not consider allowed claims in other applications or patents. Appeal 2021-000397 Application 15/068,899 18 Freedlander, 136 F.2d at 760 (emphasis added). 5. Analysis of Appellant’s Fifth Argument As to Appellant’s fifth argument, we disagree for the reason set forth supra as to Appellant’s first argument. 6. Analysis of Appellant’s Sixth Argument As to Appellant’s sixth argument, again we disagree for the reason set forth supra as to Appellant’s first argument. Again, we agree with Appellant to the extent that the record (including the Morphet Declaration) shows (a) the basic Verilog operator (e.g., those shown in “Verilog HDL Operators”) and (b) that they can be combined to perform more complex operations. We also agree with Appellant that (a) and (b) are very well known in the art, and there is an extremely high level of predictability in the art as to (a) and (b). Appellant’s sixth argument is set forth only at the complexity level of (a) and (b), and does not address the level of predictability in the art for (c) the even more highly complex particular operations required by claim 20 (i.e., complex mathematical operations including “multiple kernel tracking” and the “Lucas Kanade Inverse algorithm”). We agree with the Examiner that as to what is particularly claimed, based on the limited evidence currently before us, there is a low level of predictability in the art which mitigates against enablement. Appeal 2021-000397 Application 15/068,899 19 7. Morphet Declaration We separately summarize our concerns with the Declaration. As to paragraphs 1-3, we have no concerns. As to paragraphs 4 and 6, they are directed to the ultimate legal conclusion at issue and are not entitled to weight. Analysis Section 3 supra. As to paragraphs 5.1-5.4, the paragraphs and the references they discuss lack any demonstration as to the particular highly complex operations of claim 20. Analysis Section 1 supra. As to paragraph 7, it unpersuasively relies on allowed claims to argue rejected claims. Analysis Section 4 supra. As to paragraph 8, it is directed to the teachings of Exhibit 5 and the “teachings of a reference” are a question of fact for which Declarant’s opinion would be appropriate. However, Declarant merely states without further explanation: As shown in Exhibit 5 attached hereto (Verilog HDL Operators), Verilog is a rich complex language that enables any mathematical function required of an ASIC to be described. Declaration ¶ 8. Other than this solitary sentence, we do not find elsewhere in the Declaration where Exhibit 5 is discussed. We have review Exhibit 5 and we do not find that on its face that it necessarily enables the infinite range of “any mathematical function required of an ASIC to be described.” Without more explanation from the Declarant, we do not find his conclusory statement at paragraph 8 to be a persuasively supported statement. Appeal 2021-000397 Application 15/068,899 20 CONCLUSION The Examiner has not erred in rejecting claim 20 under 35 U.S.C. § 112(a) as failing to comply with the enablement requirement. The Examiner’s rejection of claim 20 under 35 U.S.C. § 112(a) is affirmed. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 20 112(a) Enablement 20 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED