HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPDownload PDFPatent Trials and Appeals BoardAug 23, 20212020001882 (P.T.A.B. Aug. 23, 2021) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/114,459 07/27/2016 Gregg B LESARTRE 90232495 1877 56436 7590 08/23/2021 Hewlett Packard Enterprise 3404 E. Harmony Road Mail Stop 79 Fort Collins, CO 80528 EXAMINER WEI, JANE ART UNIT PAPER NUMBER 2139 NOTIFICATION DATE DELIVERY MODE 08/23/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): chris.mania@hpe.com hpe.ip.mail@hpe.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte GREGG B. LESARTRE, MATTHEW B. LOVELL, and NAVEEN MURALIMANOHAR Appeal 2020-001882 Application 15/114,459 Technology Center 2100 ____________ Before ROBERT E. NAPPI, JOHN A. EVANS, and BETH Z. SHAW, Administrative Patent Judges. EVANS, Administrative Patent Judge. DECISION ON APPEAL1 Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s Final decision to reject Claims 1–15. Appeal Br. 1. We have jurisdiction under 35 U.S.C. § 6. We AFFIRM.2 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies Hewlett Packard Enterprise Development LP, as the real party in interest. Appeal Br. 1. 2 Throughout this Decision, we refer to the Appeal Brief filed July 29, 2019 (“Appeal Br.”); the Reply Brief filed January 8, 2020 (“Reply Br.”); the Final Office Action mailed January 31, 2019 (“Final Act.”); the Examiner’s Answer mailed November 18, 2019 (“Ans.”); and the Specification filed July 27, 2016 (“Spec.”). Appeal 2020-001882 Application 15/114,459 2 STATEMENT OF THE CASE CLAIMED SUBJECT MATTER The claims relate to a method for identifying memory regions that contain remapped memory locations. See Abstract. CLAIMS Claims 1, 7, and 14 are independent. Claim 1 is illustrative and reproduced below: 1. A method for identifying memory regions that contain remapped memory locations, comprising: determining, from a number of tracking bits on a memory module controller, at a memory region level of granularity whether any memory location of a memory region has been remapped; responsive to determining at the memory region level of granularity that any memory location of the memory region has been remapped, determining at a memory location level of granularity whether a memory location referenced by a write operation and included within the memory region has been remapped, by reading the memory location; and responsive to determining at the memory location level of granularity that the memory location referenced by the write operation has been remapped, performing the write operation on a new memory location to which the memory location has been remapped, wherein memory within a computing device is divided into a number of memory regions including the memory region. Appeal 2020-001882 Application 15/114,459 3 Prior Art Name3 Reference Date Jeddeloh US 6,035,432 Mar. 7, 2000 Qiu US 2003/0236961 A1 Dec. 25, 2003 Davis US 2012/0110278 A1 May 3, 2012 Murphy US 2015/0270015 A1 Sep. 24, 2015 Doe Hyun Yoon, et al., FREE-p: Protecting Non-Volatile Memory against both Hard and Soft Errors, IEEE (2011). REJECTIONS4 AT ISSUE 1. Claims 1–7, 9, and 12–14 stand rejected under 35 U.S.C. § 103 as being unpatentable over Davis and Jeddeloh. Final Act. 4–14. 2. Claims 2, 8, and 15 stand rejected under 35 U.S.C. § 103 as being unpatentable over Davis, Jeddeloh, and Yoon. Final Act. 14–17. 3. Claim 10 stands rejected under 35 U.S.C. § 103 as being unpatentable over Davis, Jeddeloh, and Qiu. Final Act. 17–18. 4. Claim 11 stands rejected under 35 U.S.C. § 103 as being unpatentable over Davis, Jeddeloh, and Murphy. Final Act. 18– 19. ANALYSIS We have considered in this Decision only those arguments Appellant actually raised in the Brief. Any other arguments that Appellant could have 3 All citations herein to the references are by reference to the first named inventor/author only. 4 The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Final Act. 2. Appeal 2020-001882 Application 15/114,459 4 made but chose not to make in the Briefs are deemed to be forfeit. See 37 C.F.R. § 41.37(c)(1)(iv). We are not persuaded that Appellant identifies reversible error. Upon consideration of the arguments presented in the Appeal Brief and the Reply Brief, we agree with the Examiner that all the pending claims are unpatentable under 35 U.S.C. § 103. We adopt as our own the findings and reasons set forth in the rejections from which this appeal is taken and in the Examiner’s Answer, to the extent consistent with our analysis below. We provide the following explanation to highlight and address specific arguments and findings primarily for emphasis. CLAIMS 1–7, 9, AND 12–14: OBVIOUSNESS OVER DAVIS AND JEDDELOH. Appellant argues the claims, as a group, are patentable in view of the limitations of Claim 1. See Appeal Br. 4. Therefore, we decide the appeal of the § 103 rejections on the basis of Claim 1 and refer to the rejected claims collectively herein as “the claims.” See 37 C.F.R. § 41.37(c)(1)(iv); In re King, 801 F.2d 1324, 1325 (Fed. Cir. 1986). Claim 1 recites, inter alia: “determining, from a number of tracking bits on a memory module controller, at a memory region level of granularity whether any memory location of a memory region has been remapped.” Claim 1. Appeal Br. 10. Appellant contends if it is determined whether any memory location of a memory region has been remapped, then it is determined at a memory location level of granularity whether a specific memory location, within the memory region, has been remapped. Appeal Br. 5. Appellant argues Davis’ processor comprises a translation look aside Appeal 2020-001882 Application 15/114,459 5 buffer which can determine whether a PCM block has been remapped at a memory page level of granularity. Id. Appellant argues a determination at a memory page/PCM block level of granularity fails to teach a memory region level of granularity. Appeal Br. 6. Appellant further contends Jeddeloh associates an error tag with defective memory blocks and thus, fails to teach a determination at a memory region level of granularity. Appeal Br. 7. The Examiner finds that Davis teaches a translation look aside buffer which stores an additional bit termed an “inoperable block bit” for each memory page that indicates whether the virtual memory page is associated with any inoperable PCM blocks. Ans. 4 (citing Davis ¶3). We concur and note that Appellant’s Specification does not define the claimed “memory region level” and thus we concur with the Examiner that Davis’s memory page/PCM block level teaches the limitation. Appellant contends that assuming the Examiner’s reasoning in the Answer is correct, the prior art still fails to teach “determining at a memory location level of granularity whether a memory location referenced by a write operation and included within the memory region has been remapped, by reading the memory location,” as claimed. Reply Br. 2. The Examiner finds maintaining an inoperable block table, as does Jeddeloh, necessitates reading the memory location itself to make a determination as to whether or not the block is operable or inoperable. Final Act. 3 (citing Davis ¶17). The Examiner further finds reading of the memory location happens when the inoperable block table is created, and thus prior to the determining step, as claimed. Id. Appeal 2020-001882 Application 15/114,459 6 We have reviewed the teachings of Davis, concur with the Examiner’s findings and are not persuaded the Examiner erred in rejecting claim 1 or the claims grouped with claim 1. CLAIMS 2, 8, AND 15: OBVIOUSNESS OVER DAVIS, JEDDELOH, AND YOON. Appellant contends Yoon fails to cure the deficiencies of Davis and Jeddeloh. Appeal Br. 8. As discussed above, we are not persuaded the prior art fails to teach the limitations of the independent claims. CLAIM 10: OBVIOUSNESS OVER DAVIS, JEDDELOH, AND QIU. Appellant contends Qiu fails to cure the deficiencies of Davis and Jeddeloh. Appeal Br. 8. As discussed above, we are not persuaded the prior art fails to teach the limitations of the independent claims. CLAIM 11: OBVIOUSNESS OVER DAVIS, JEDDELOH, AND MURPHY. Appellant contends Murphy fails to cure the deficiencies of Davis and Jeddeloh. Appeal Br. 8. As discussed above, we are not persuaded the prior art fails to teach the limitations of the independent claims. Appeal 2020-001882 Application 15/114,459 7 CONCLUSION In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1–7, 9, 12–14 103 Davis, Jeddeloh 1–7, 9, 12–14 2, 8, 15 103 Davis, Jeddeloh, Yoon 2, 8, 15 10 103 Davis, Jeddeloh, Qiu 10 11 103 Davis, Jeddeloh, Murphy 11 Overall Outcome 1–15 TIME PERIOD No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED Copy with citationCopy as parenthetical citation