Goldman, Sachs & Co.

Patent Trials and Appeals Board

Dec 24, 2021

2020005513 (P.T.A.B. Dec. 24, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/481,201 04/06/2017 Paul Burchard CPIP-2017-0125 3557
132787 7590 12/24/2021
Docket Clerk-GOLD
P.O. Drawer 800889
Dallas, TX 75380
EXAMINER
MAMO, ELIAS
ART UNIT PAPER NUMBER
2184
NOTIFICATION DATE DELIVERY MODE
12/24/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents@munckwilson.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte PAUL BURCHARD and ULRICH DREPPER
____________________

Appeal 2020-005513
Application 15/481,201
Technology Center 2100
____________________

Before MARC S. HOFF, CARL L. SILVERMAN, and JOYCE CRAIG,
Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appellant1 appeals under 35 U.S.C. § 134 from a non-final rejection
of claims 1–20. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Appellant’s invention is an apparatus including multiple computing
cores, each computing core configured to perform one or more processing
operations and generate input data. The apparatus further includes multiple
coprocessors associated with each computing core, each coprocessor being

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies the real party in interest as Goldman
Sachs & Co. LLC. Appeal Br. 2.
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configured to receive the input data from at least one of the computing cores,
process the input data, and generate output data. The apparatus further
includes multiple reducer circuits configured to receive the output data from
each of the coprocessors of an associated computing core, apply one or more
functions to the output data, and provide one or more results to the
associated computing core. Abstract.
Claim 1 is exemplary of the claims on appeal:
1. An apparatus comprising:
multiple computing cores, each computing core
configured to perform one or more processing operations and
generate input data;
multiple sets of coprocessors each uniquely associated
with a different one of the computing cores, each coprocessor
configured to receive the input data from at least one of the
computing cores, process the input data, and generate output
data;
multiple reducer circuits each uniquely associated with a
different one of the computing cores, each reducer circuit
configured to receive the output data from the coprocessors in
the set of coprocessors associated with the computing core
uniquely associated with the reducer circuit, apply one or more
functions to the output data, and provide one or more results to
the computing core uniquely associated with the reducer circuit;
and
multiple communication links communicatively coupling
the computing cores and at least some of the coprocessors.

The prior art relied upon by the Examiner as evidence is:
Name Reference Date
Tsujimoto US 5,493,307 February 20, 1996
Davis US 6,829,697 B1 December 7, 2004
Funk US 2012/0066474 A1 March 15, 2012

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Claims 1–20 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Davis, Tsujimoto, and Funk.
Throughout this Decision, we make reference to the Appeal Brief
(“Appeal Br.,” filed February 6, 2020), the Reply Brief (“Reply Br.,” filed
July 16, 2020), and the Examiner’s Answer (“Ans.,” mailed June 1, 2020)
for their respective details.

ISSUES
Appellant’s arguments present us with the following issues:
1. Does the combination of Davis, Tsujimoto, and Funk teach or
suggest multiple sets of coprocessors each uniquely associated with a
different one of the computing cores?
2. Does the combination of Davis, Tsujimoto, and Funk teach or
suggest multiple reducer circuits each uniquely associated with a different
one of the computing cores?

ANALYSIS
Independent claim 1 recites, in pertinent part, “multiple sets of
coprocessors each uniquely associated with a different one of the computing
cores, each coprocessor configured to receive the input data from at least one
of the computing cores.” Claim 1 further recites “multiple reducer circuits
each uniquely associated with a different one of the computing cores, each
reducer circuit configured to receive the output data from the coprocessors
. . . and provide one or more results to the computing core uniquely
associated with the reducer circuit.”
Independent claims 9 and 17 recite analogous limitations concerning
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sets of coprocessors each uniquely associated with a different one of the
computing cores.
Independent claim 9 recites “a subset of the coprocessors” rather than
“multiple reducer circuits.” This subset recited in claim 9 is claimed to
perform the same functions as the reducers recited in claim 1.
Independent claim 17 recites an analogous limitation concerning “N
reducer circuits,” each computing core associated with a distinct one of the
reducer circuits.
Dedicated Coprocessors
Appellant contends that there is no motivation to modify Davis to
limit a particular coprocessor to use with one core language processor. Reply
Br. 3.
The Examiner finds that Davis teaches a pair of core language
processors 34, 36, and several attached coprocessors that “provide hardware
acceleration for specific network processing tasks such as high speed pattern
search, data manipulation, internal chip management functions, frame
parsing, and data fetching.” Davis col. 6:55–61; see Non-Final Act. 2–3.
Davis next explains the specific function that each disclosed coprocessor is
specialized to perform. Davis col. 6:64–col. 11:2.
The Examiner finds that Funk teaches dedicatedly assigning a
coprocessor for each main processor. Funk ¶ 37. The Examiner determines
that the skilled artisan would have modified Davis to employ dedicated
coprocessors as a matter of design choice, “as alternative way to configure
the circuit.” Ans. 4.
Appellant argues, and we agree, that the Examiner has not explained,
nor cited evidence in support, why the ordinarily skilled artisan would have
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found it obvious to modify Davis, which teaches shared special-function,
coprocessors, such that these special-function coprocessors, would instead
be dedicated to a particular computing core, rather than being shared, such
as Davis teaches, so that either processor may take advantage of its special
functions. Appeal Br. 13.
Multiple reducer circuits
Appellant further argues that there is no motivation to modify Davis
to include multiple reducer circuits each uniquely associated with a different
one of the computing cores. Reply Br. 4.
The Examiner finds that Tsujimoto teaches multiple reducer circuits,
citing elements 109 (adaptive matched filter), 110 (combiner), and 111
(adaptive equalizer) of Tsujimoto as corresponding to the claimed “reducer.”
Ans. 5; Tsujimoto col. 4:1–40. The Examiner further finds that Tsujimoto
teaches that each reducer circuit provides one or more results to the
associated computing core. Ans. 5, citing Tsujimoto col. 3:52–54, 60–66.
The Examiner further finds that Funk discloses a system comprised of
multiple processors and co-processors configured to perform auxiliary
functions, each co-processor being dedicated to a specific processor. Non-
Final Act. 4, citing Funk ¶¶ 35, 37. The Examiner determines that Funk
suggests multiple reducer circuits, each uniquely associated with a different
one of multiple computing cores. Ans. 6.
We do not agree with the Examiner’s finding. We agree with
Appellant that Tsujimoto teaches only a single instance of such “reducer
circuit, elements 109-110-111. Tsujimoto col. 4:1–40. We observe that the
Examiner does not rely on Funk for any explicit teaching of multiple reducer
circuits, or any explicit teaching of plural reducer circuits each uniquely
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associated with a different one of the computing cores, as claim 1 requires.
Thus, no reference teaches or suggests either (a) the use of multiple reducer
circuits or (b) the association of respective reducer circuits with a different
one of the computing cores.
In the Examiner’s Answer, the Examiner determines that the unique
association of different reducer circuits with different computing cores is
“simply a design choice, in which a skilled artisan in the art would
implement as [an] alternative way to configure the circuit.” Ans. 6
(alteration in original). The Examiner finds that this design choice argument
is supported by Funk’s teaching of co-processors being dedicated to a
specific processor.
We do not agree with the Examiner that Funk teaches the dedication
of reducer circuits with a specific computing core, as Funk contains no
teachings directed to reducer circuits.
Because we find, on this record, that the combination of Davis,
Tsujimoto, and Funk does not suggest multiple sets of coprocessors, each
uniquely associated with a different one of the computing cores, and because
we find that the combination of Davis, Tsujimoto, and Funk does not
suggest multiple reducer circuits, each uniquely associated with a different
one of the computing cores, we are constrained to not sustain the Examiner’s
§ 103 rejection of independent claims 1, 9, and 17.
Because we do not sustain the Examiner’s rejection of independent
claims 1, 9, and 17, we need not reach Appellant’s separate arguments
concerning the dependent claims under appeal.
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We are thus similarly constrained to not sustain the Examiner’s
rejection of dependent claims 2–8, 10–16, and 18–20, for the reasons given
with respect to independent claims 1, 9, and 17.
CONCLUSIONS
1. The combination of Davis, Tsujimoto, and Funk fails to teach or
suggest multiple sets of coprocessors each uniquely associated with a
different one of the computing cores.
2. The combination of Davis, Tsujimoto, and Funk fails to teach or
suggest multiple reducer circuits each uniquely associated with a different
one of the computing cores.

DECISION SUMMARY
In summary:
Claim(s)
Rejected
35 U.S.C.
§
Reference(s)/
Basis
Affirmed Reversed
1–20 103 Davis, Tsujimoto,
Funk
1–20

CONCLUSION
The Examiner’s decision to reject claims 1–20 is reversed.

REVERSED