Godo Kaisha IP Bridge 1

Patent Trials and Appeals Board

Dec 6, 2021

IPR2020-01008 (P.T.A.B. Dec. 6, 2021)

Trials@uspto.gov Paper 31
571-272-7822 Entered: December 6, 2021

UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

MICRON TECHNOLOGY, INC.,
Petitioner,
v.
GODO KAISHA IP BRIDGE 1,
Patent Owner.

IPR2020-01008
Patent 6,445,047 B1

Before JUSTIN T. ARBES, DAVID C. McKONE, and AMBER L. HAGY,
Administrative Patent Judges.
ARBES, Administrative Patent Judge.
JUDGMENT
Final Written Decision
Determining All Challenged Claims Unpatentable
35 U.S.C. § 318(a)
I. INTRODUCTION
A. Background and Summary
Petitioner Micron Technology, Inc. (“Petitioner”), filed a Petition
(Paper 7, “Pet.”) requesting inter partes review of claims 1–4 of U.S. Patent
No. 6,445,047 B1 (Ex. 1001, “the ’047 patent”) pursuant to 35 U.S.C.
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§ 311(a). On December 7, 2020, we instituted an inter partes review as to
all challenged claims on all grounds of unpatentability asserted in the
Petition. Paper 10 (“Decision on Institution” or “Dec. on Inst.”). Patent
Owner Godo Kaisha IP Bridge 1 (“Patent Owner”) subsequently filed a
Patent Owner Response (Paper 15, “PO Resp.”), Petitioner filed a Reply
(Paper 18, “Reply”), and Patent Owner filed a Sur-Reply (Paper 22,
“Sur-Reply”). An oral hearing was held on September 15, 2021, and a
transcript of the hearing is included in the record (Paper 30, “Tr.”).
We have jurisdiction under 35 U.S.C. § 6. This Final Written
Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons that
follow, we determine that Petitioner has shown by a preponderance of the
evidence that claims 1–4 are unpatentable.

B. Related Matters
The parties indicate that the ’047 patent is the subject of the following
pending district court case: Godo Kaisha IP Bridge 1 v. Micron Technology,
Inc., Case No. 20-cv-00178 (W.D. Tex.) (“the district court case”).
See Pet. 5; Paper 5, 1. Petitioner also filed petitions challenging claims of
other patents asserted in the district court case in Cases IPR2020-01007 and
IPR2020-01009.

C. The ’047 Patent
The ’047 patent discloses a semiconductor device including two
different surface-channel-type metal-oxide-semiconductor field-effect
transistors (MOSFETs) with different threshold voltages. Ex. 1001, col. 1,
ll. 5–10. According to the ’047 patent, “it is very important to form
surface-channel-type MOSFETs of multiple types on a semiconductor chip”
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to enhance performance in a large-scale integration (LSI) system. Id. at
col. 1, ll. 11–17. The ’047 patent states that it was known to use, in the same
semiconductor device, MOSFETs in a “logic circuit block” that “enhance
their driving power by lowering the threshold voltage and increasing the
saturated current value” and MOSFETs in a “memory cell block” that
“increase a data retention time by raising the threshold voltage value and
minimizing the leakage current.” Id. at col. 1, ll. 18–27. Further, to form
multiple types of surface-channel-type MOSFETs with different threshold
voltages, it was known to “mak[e] the dopant concentrations in the channel
regions different by implanting dopant ions at mutually different doses into
the channel regions.” Id. at col. 1, ll. 47–52. Setting a higher implant dose
for the memory cell block MOSFET results in a higher threshold voltage.
Id. at col. 1, ll. 52–57. Also, as gate insulating films become thinner due to
the need for miniaturization, the dopant concentration needed to realize a
certain threshold voltage increases. Id. at col. 1, ll. 58–62. The ’047 patent
discloses that “performance degrades . . . as the dopant concentration in the
channel region gets higher” due to, for example, increased “leakage current
flowing through the pn junction.” Id. at col. 1, l. 63–col. 2, l. 12.
The ’047 patent seeks to solve these problems using a first-surface-
channel-type MOSFET in a “logic circuit block” “with a threshold voltage
of a relatively small absolute value” and a second-surface-channel-type
MOSFET that “controls power to be supplied to the logic circuit block”
“with a threshold voltage of a relatively large absolute value.” Id. at col. 2,
ll. 20–24, 58–62. To increase the threshold voltage “without raising the
dopant concentration,” the second-surface-channel-type MOSFET includes a
gate electrode “formed out of a refractory metal film made of a refractory
metal or a compound thereof” (e.g., titanium nitride, tungsten, molybdenum,
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tantalum). Id. at col. 2, ll. 28–48, col. 3, ll. 61–63, col. 6, ll. 46–51. The
second-surface-channel-type MOSFET also has a thicker gate insulating
film to “enhance its OFF-state leakage current characteristics” and improve
storage ability. Id. at col. 3, ll. 4–16.
Figures 4(a)–4(c) of the ’047 patent are reproduced below.

Figures 4(a)–4(c) depict the later steps of a fabrication process for a
semiconductor device with “a first [n-type metal-oxide-semiconductor
(NMOS)] transistor . . . formed in a peripheral circuit region on the left side,
while second NMOS transistors are formed in a memory cell region on the
right side.” Id. at col. 6, ll. 60–67. The first-surface-channel-type NMOS
transistor has first gate electrode 207A, which is “made of an n-type
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polysilicon film” and has “a threshold voltage with a relatively small
absolute value,” formed on first gate insulating film 206A “with a relatively
small thickness of 2.5 nm.” Id. at col. 8, ll. 15–20, 26–30. The second-
surface-channel-type NMOS transistors each have second gate electrode
218, which is made of a refractory metal (tungsten) and has “a threshold
voltage with a relatively large absolute value,” formed on second gate
insulating film 206B “with a relatively large thickness of 5 nm.” Id. at
col. 8, ll. 20–25, 30–35. P-type doped region 205 in the channel region of
the second-surface-channel-type NMOS transistors has a “relatively low
dopant concentration” as compared to p-type doped region 203 of the
channel region of the first-surface-channel-type NMOS transistor, which has
a “relatively high dopant concentration.” Id. at col. 7, ll. 6–22, col. 8,
ll. 36–40.

D. Illustrative Claim
Challenged claim 1 of the ’047 patent is independent. Claims 2–4
depend from claim 1. Claim 1 recites:
1. A semiconductor device comprising:
a first-surface-channel-type MOSFET with a first
threshold voltage; and
a second-surface-channel-type MOSFET with a second
threshold voltage having an absolute value greater than an
absolute value of said first threshold voltage,
wherein the first-surface-channel-type MOSFET includes:
a first gate insulating film formed on a
semiconductor substrate; and
a first gate electrode, which has been formed out of
a poly-silicon film formed directly on the first gate
insulating film, and
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wherein the second-surface-channel-type MOSFET
includes:
a second gate insulating film formed on the
semiconductor substrate; and
a second gate electrode, which has been formed out
of a refractory metal film formed directly on the second
gate insulating film, the refractory metal film being made
of a refractory metal or a compound thereof.

E. Evidence
The pending grounds of unpatentability in the instant inter partes
review are based on the following prior art:
U.S. Patent No. 6,424,016 B1, filed May 23, 1997, issued
July 23, 2002 (Ex. 1006, “Houston”);
U.S. Patent No. 6,165,849, filed Dec. 4, 1998, issued
Dec. 26, 2000 (Ex. 1007, “An”); and
Fumihiko Yanagawa et al., A 1-µm Mo-Poly 64-kbit MOS
RAM, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27,
NO. 8 (Aug. 1980) (Ex. 1004, “Yanagawa”).1
Petitioner filed a declaration from John C. Bravman, Ph.D. (Ex. 1003) with
its Petition and a reply declaration from Dr. Bravman (Ex. 1042) with its
Reply. Patent Owner filed a declaration from Kelin Kuhn, Ph.D. (Ex. 2004)
with its Response. Also submitted as evidence are transcripts of the
depositions of Dr. Bravman (Exs. 2043, 2048) and Dr. Kuhn (Ex. 1041).

1 When citing non-patent references filed by Petitioner, such as Yanagawa,
we refer to the page numbers in the bottom-right corner added by Petitioner.
See 37 C.F.R. § 42.63(d)(2).
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F. Asserted Grounds
The instant inter partes review involves the following grounds of
unpatentability:
Claim(s)
Challenged 35 U.S.C. § Reference(s)/Basis
1, 2, 4 102(b)2 Yanagawa
1, 2, 4 103(a) Yanagawa3

2 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
(2011) (“AIA”), amended 35 U.S.C. §§ 102 and 103. Because the
challenged claims of the ’047 patent have an effective filing date before the
effective date of the applicable AIA amendments, we refer to the pre-AIA
versions of 35 U.S.C. §§ 102 and 103.
3 Petitioner asserts for some of its obviousness grounds that the challenged
claims would have been obvious over the cited references and the
“knowledge” or “ordinary knowledge” of a person of ordinary skill in the
art. See Pet. 9 n.3, 12, 47, 53, 59, 76. As explained in the Decision on
Institution, we do not include the general knowledge of a person of ordinary
skill in the art in listing the grounds themselves, recognizing that such
knowledge is considered in every obviousness analysis. See Dec. on Inst. 7
n.5; 35 U.S.C. § 311(b) (inter partes review “only on the basis of prior art
consisting of patents or printed publications”); Koninklijke Philips N.V. v.
Google LLC, 948 F.3d 1330, 1337 (Fed. Cir. 2020) (“Although the prior art
that can be considered in inter partes reviews is limited to patents and
printed publications, it does not follow that we ignore the skilled artisan’s
knowledge when determining whether it would have been obvious to modify
the prior art. . . . Regardless of the tribunal, the inquiry into whether any
‘differences’ between the invention and the prior art would have rendered
the invention obvious to a skilled artisan necessarily depends on such
artisan’s knowledge.”); Randall Mfg. v. Rea, 733 F.3d 1355, 1362–63
(Fed. Cir. 2013) (“[T]he knowledge of [an ordinarily skilled] artisan is part
of the store of public knowledge that must be consulted when considering
whether a claimed invention would have been obvious.”); Dow Jones & Co.
v. Ablaise Ltd., 606 F.3d 1338, 1349 (Fed. Cir. 2010) (“[The obviousness]
analysis requires an assessment of the . . . ‘background knowledge possessed
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Claim(s)
Challenged 35 U.S.C. § Reference(s)/Basis
3 103(a) Yanagawa, An4
1, 2, 4 103(a) Houston
3 103(a) Houston, An

II. ANALYSIS
A. Level of Ordinary Skill in the Art
In determining the level of ordinary skill in the art for a challenged
patent, we look to “1) the types of problems encountered in the art; 2) the
prior art solutions to those problems; 3) the rapidity with which innovations
are made; 4) the sophistication of the technology; and 5) the educational
level of active workers in the field.” Ruiz v. A.B. Chance Co., 234 F.3d 654,
666–667 (Fed. Cir. 2000). “Not all such factors may be present in every
case, and one or more of them may predominate.” Id.
Petitioner states that it treats the ’047 patent as having an effective
filing date of October 26, 1999, and argues that a person of ordinary skill in
the art at that time would have had “a degree in electrical engineering,

by a person having ordinary skill in the art.’” (citing KSR Int’l Co. v.
Teleflex Inc., 550 U.S. 398, 401 (2007))).
4 Petitioner includes two sections of its Petition for this ground, asserting
that claim 3 would have been obvious over Yanagawa, An, and the
“knowledge of a [person of ordinary skill in the art],” relying on its previous
arguments that Yanagawa anticipates parent claim 1, Pet. 47–53, and over
Yanagawa and An, relying on its previous arguments that Yanagawa renders
obvious parent claim 1, id. at 58–59. As explained in the Decision on
Institution, we consider these to be a single asserted ground of obviousness
based on Yanagawa and An, with alternative theories as to how the prior art
teaches the limitations of parent claim 1. Dec. on Inst. 8 n.6.
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physics, materials science, or a similar discipline, along with [two] years of
experience in the development, design, or implementation of semiconductor
devices,” and would have been “aware of and generally knowledgeable
about the structure and operation of [dynamic random-access memory
(DRAM)].” Pet. 9, 29 (citing Ex. 1003 ¶¶ 34–37). Patent Owner does not
address the level of ordinary skill in the art in its Response or Sur-Reply.
Based on the full record developed during trial, including our review of the
’047 patent and the types of problems and solutions described in the
’047 patent and cited prior art, we agree with Petitioner’s assessment of the
level of ordinary skill in the art and apply it for purposes of this Decision.

B. Claim Interpretation
We interpret the claims of the challenged patent
using the same claim construction standard that would be used to
construe the [claims] in a civil action under 35 U.S.C. 282(b),
including construing the [claims] in accordance with the ordinary
and customary meaning of such [claims] as understood by one of
ordinary skill in the art and the prosecution history pertaining to
the patent.
37 C.F.R. § 42.100(b) (2019). “In determining the meaning of [a] disputed
claim limitation, we look principally to the intrinsic evidence of record,
examining the claim language itself, the written description, and the
prosecution history, if in evidence.” DePuy Spine, Inc. v. Medtronic
Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006). Claim terms
are given their plain and ordinary meaning as would be understood by a
person of ordinary skill in the art at the time of the invention and in the
context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d
1303, 1313 (Fed. Cir. 2005) (en banc). “There are only two exceptions to
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this general rule: 1) when a patentee sets out a definition and acts as his own
lexicographer, or 2) when the patentee disavows the full scope of a claim
term either in the specification or during prosecution.” Thorner v. Sony
Comput. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012).
In its Petition, Petitioner proposed the following interpretation for the
claim term “surface-channel-type MOSFET”: “a MOSFET (metal-oxide-
semiconductor field-effect transistor) in which the channel forms near the
top surface of the semiconductor substrate.” Pet. 15, 18–21. Petitioner also
stated that the terms “logic circuit block” and “memory cell block” do not
require express interpretation, but argued that certain structures fall “within
[the] scope” of each term. Id. at 21–22. Patent Owner disagreed with
Petitioner’s proposed interpretation of “surface-channel-type MOSFET” in
its Preliminary Response, but did not propose an alternative interpretation.
Paper 9, 12–22. Both parties argued that “surface-channel-type MOSFET”
is a “known term of art.” See Pet. 19; Paper 9, 14.
In the Decision on Institution, we preliminarily interpreted
“surface-channel-type MOSFET” to mean “a MOSFET in which the channel
forms at the surface of the semiconductor substrate, rather than slightly
under the surface,” and concluded that no other claim terms required express
interpretation. Dec. on Inst. 24–30. We found that the claims and written
description of the ’047 patent do not define or otherwise shed light on what
is meant by the term “surface-channel-type,” and based our interpretation
primarily on the description of surface-channel and buried-channel
MOSFETs in a textbook, John Y. Chen, CMOS Devices and Technology for
VLSI (1990) (Ex. 1014, “Chen”), on which Petitioner relied for its analysis
in the Petition. See Dec. on Inst. 26–30; Pet. 18–20.
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Subsequent to that Decision, the district court in the district court case
construed “surface-channel-type MOSFET” to have its “[p]lain-and-ordinary
meaning” and stated: “Note for the jury: The channel in a surface-channel-
type MOSFET is immediately below the MOSFET gate oxide / insulator.”
Ex. 3004, 2; see Ex. 2027, 61:19–66:10 (Petitioner arguing that the district
court should adopt the Board’s preliminary interpretation “because it
precisely tracks what all the parties agree is the proper meaning of the
surface-channel transistor”).
Patent Owner in its Response argues that Petitioner’s asserted grounds
based on Yanagawa fail under either the interpretation Petitioner proposed in
the Petition or the Board’s preliminary interpretation, but insists “Petitioner
should be held to demonstrating unpatentability under the Board’s
construction.” PO Resp. 18–19. Petitioner applies our preliminary
interpretation. Reply 3 n.1, 11. The parties disagree as to whether
Yanagawa discloses a “surface-channel-type MOSFET” under our
preliminary interpretation and as to how Yanagawa should be analyzed to
determine whether it discloses a “surface-channel-type MOSFET,” but do
not otherwise dispute our preliminary interpretation or offer any different
interpretation. See PO Resp. 16–55; Reply 3–20; Sur-Reply 1–23;
Tr. 47:11–18 (Patent Owner arguing that our preliminary interpretation is
“correct”); infra Section II.D.2.(b).
Based on the full record developed during trial, we see no reason to
deviate from the preliminary interpretation adopted in the Decision on
Institution, and incorporate our previous analysis herein. See Dec. on Inst.
24–30. We also note that the district court’s note for the jury is generally
consistent with our preliminary interpretation, but has a different focus. The
district court’s note focuses on where the channel forms relative to the gate
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oxide/insulator (i.e., immediately “below” the gate oxide/insulator), whereas
our interpretation focuses on where the channel forms relative to the
semiconductor substrate (i.e., “at the surface” of the semiconductor
substrate). Claim 1 recites that each of the two surface-channel-type
MOSFETs has a gate insulating film formed “on” the semiconductor
substrate; thus, a channel that forms at the surface of the semiconductor
substrate would be immediately below the gate insulating film. Further,
dependent claim 2 recites relative dopant concentrations “in the channel
region” of each surface-channel-type MOSFET. Given the pertinent
extrinsic evidence cited in the Decision on Institution, particularly the Chen
textbook, we are persuaded that the focus on where the channel forms
relative to the recited semiconductor substrate is correct.
We interpret “surface-channel-type MOSFET” to mean “a MOSFET
in which the channel forms at the surface of the semiconductor substrate,
rather than slightly under the surface,” and conclude that no other terms
require express interpretation to determine whether Petitioner has met its
burden to prove unpatentability of the challenged claims. See Nidec Motor
Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed.
Cir. 2017) (“Because we need only construe terms ‘that are in controversy,
and only to the extent necessary to resolve the controversy,’ we need not
construe [a particular claim limitation] where the construction is not
‘material to the . . . dispute.’” (citations omitted)).

C. Legal Standards
“Anticipation requires that every limitation of the claim in issue be
disclosed, either expressly or under principles of inherency, in a single prior
art reference,” Corning Glass Works v. Sumitomo Elec. U.S.A., Inc.,
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868 F.2d 1251, 1255–56 (Fed. Cir. 1989), and that the claim limitations be
“arranged or combined in the same way as recited in the claim,”
Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008).
However, “the reference need not satisfy an ipsissimis verbis test,” meaning
identity of terminology between the prior art reference and the claim is not
required. In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond,
910 F.2d 831, 832–833 (Fed. Cir. 1990). “In an anticipation analysis, the
dispositive question is whether a skilled artisan would ‘reasonably
understand or infer’ from a prior art reference that every claim limitation is
disclosed in that single reference.” Acoustic Tech., Inc. v. Itron Networked
Solutions, Inc., 949 F.3d 1366, 1373 (Fed. Cir. 2020) (citation omitted).
Whether a reference anticipates is assessed from the perspective of an
ordinarily skilled artisan. Finisar Corp. v. DirecTV Group, Inc., 523 F.3d
1323, 1336 (Fed. Cir. 2008) (“[T]he meaning of a prior art reference requires
analysis of the understanding of an artisan of ordinary skill.”). “Expert
testimony may shed light on what a skilled artisan would reasonably
understand or infer from a prior art reference.” Acoustic, 949 F.3d at 1373;
accord Dayco Prods., Inc. v. Total Containment, Inc., 329 F.3d 1358,
1368–69 (Fed. Cir. 2003) (“Typically, testimony concerning anticipation
must be testimony from one skilled in the art and must identify each claim
element, state the witnesses’ interpretation of the claim element, and explain
in detail how each claim element is disclosed in the prior art reference.”
(citation omitted)).
A claim is unpatentable for obviousness if, to one of ordinary skill in
the pertinent art, “the differences between the subject matter sought to be
patented and the prior art are such that the subject matter as a whole would
have been obvious at the time the invention was made.” KSR, 550 U.S. at
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406 (quoting 35 U.S.C. § 103(a) (2006)). The question of obviousness is
resolved on the basis of underlying factual determinations, including “the
scope and content of the prior art”; “differences between the prior art and the
claims at issue”; and “the level of ordinary skill in the pertinent art.”
Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966). Additionally,
secondary considerations, such as “commercial success, long felt but
unsolved needs, failure of others, etc., might be utilized to give light to the
circumstances surrounding the origin of the subject matter sought to be
patented. As indicia of obviousness or nonobviousness, these inquiries may
have relevancy.”5 Id. When conducting an obviousness analysis, we
consider a prior art reference “not only for what it expressly teaches, but also
for what it fairly suggests.” Bradium Techs. LLC v. Iancu, 923 F.3d 1032,
1049 (Fed. Cir. 2019) (citation omitted).
A patent claim “is not proved obvious merely by demonstrating that
each of its elements was, independently, known in the prior art.” KSR,
550 U.S. at 418. An obviousness determination requires finding “both ‘that
a skilled artisan would have been motivated to combine the teachings of the
prior art references to achieve the claimed invention, and that the skilled
artisan would have had a reasonable expectation of success in doing so.’”
Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd., 821 F.3d 1359,
1367–68 (Fed. Cir. 2016); see KSR, 550 U.S. at 418 (for an obviousness
analysis, “it can be important to identify a reason that would have prompted
a person of ordinary skill in the relevant field to combine the elements in the
way the claimed new invention does”).

5 Patent Owner has not presented any evidence of secondary considerations
of nonobviousness in this proceeding.
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“Although the KSR test is flexible, the Board ‘must still be careful not
to allow hindsight reconstruction of references . . . without any explanation
as to how or why the references would be combined to produce the claimed
invention.’” TriVascular, Inc. v. Samuels, 812 F.3d 1056, 1066 (Fed. Cir.
2016) (alteration in original). Further, an assertion of obviousness “cannot
be sustained by mere conclusory statements; instead, there must be some
articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness.” KSR, 550 U.S. at 418 (quoting In re Kahn,
441 F.3d 977, 988 (Fed. Cir. 2006)); accord In re NuVasive, Inc., 842 F.3d
1376, 1383 (Fed. Cir. 2016) (stating that “conclusory statements” amount to
an “insufficient articulation[] of motivation to combine”; “instead, the
finding must be supported by a ‘reasoned explanation’”); In re Magnum Oil
Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed. Cir. 2016) (“To satisfy its
burden of proving obviousness, a petitioner cannot employ mere conclusory
statements. The petitioner must instead articulate specific reasoning, based
on evidence of record, to support the legal conclusion of obviousness.”).

D. Anticipation Ground Based on Yanagawa (Claims 1, 2, and 4)
1. Yanagawa
Yanagawa is an IEEE article describing “a new 1-µm double-gate
technology using molybdenum and polysilicon (Mo-poly technology).”
Ex. 1004, 1. “In this technology, molybdenum is used for word lines and
gate electrodes for MOSFET’s in memory cells. Polysilicon is used for gate
electrodes for MOSFET’s in peripheral circuitry and storage capacitor
electrodes.” Id. “Therefore, a high packing density and high-speed MOS
[random-access memory (RAM)] is realized due to reduction in memory-cell
size and in word-line propagation delay.” Id.
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Yanagawa describes a design using “[s]hort-channel Si-gate and
Mo-gate [field-effect transistors (FETs)].” Id. at 2. “Device parameters for
1-µm Si-gate FET’s are optimized for peripheral circuitry where high
performance is required.” Id. “Si-gate FET’s were used [for peripheral
circuitry] because they have low threshold voltage due to their
work-function values.” Id. Table I of Yanagawa is reproduced below.

Table I lists various parameters and characteristics of the Si-gate and
Mo-gate transistors, such as B+ dose, gate oxide thickness, and threshold
voltage.6 Id. at 3. Yanagawa discloses that
[i]n designing Mo-gate FET’s in memory cell[s], gate
oxide thickness and effective channel length are important.
Maximum gate voltage, applied to Mo-gate FET’s in memory
cells, is 7 V to obtain higher signal level. Therefore, it was
necessary to increase Mo-gate FET gate oxide thickness to

6 “A voltage greater than the threshold voltage (typically abbreviated [as] Vt)
inverts the region underneath the gate insulating film (e.g., . . . from p-type
to n-type) to form a channel region between the source and drain that is
conductive to allow current to flow between the source and drain regions.”
Ex. 1003 ¶ 44; see Ex. 1014, 18–19.
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40 nm. To avoid short-channel effect in Mo-gate FET’s, the
effective channel length was increased to 1.5 µm. . . . Mo-gate
FET characteristics [shown in Table I] are good enough for
memory operation, because Mo-gate FET’s are used only in
memory cells.
Id. Figure 2 of Yanagawa is reproduced below.

Figure 2 depicts “memory-cell structures” using the disclosed
“molybdenum-polysilicon (Mo-poly) technology.” Id. at 1. A “[f]irst-level
gate of polysilicon is used as the storage capacitor electrode, which does not
significantly affect word-line delay or speed performance. The word line is
made of molybdenum, that is, second-level gate.” Id. “These structures also
provide[] . . . good intermediate insulating layers between two gate
electrodes and [an] aluminum-molybdenum multilevel interconnection
system.” Id. at 1–2.

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2. Claim 1
Petitioner argues that claim 1 is anticipated by Yanagawa7 under
35 U.S.C. § 102(b), relying on the testimony of Dr. Bravman as support.
Pet. 29–42 (citing Ex. 1003). Patent Owner makes various arguments in
response, relying on the testimony of Dr. Kuhn. PO Resp. 16–55 (citing
Ex. 2004); Sur-Reply 1–23.

a) Undisputed Issues
Petitioner contends that Yanagawa discloses a “semiconductor
device” (i.e., MOS RAM) comprising a “first-surface-channel-type
MOSFET” (i.e., Si-gate transistor) with a “first threshold voltage” (0.5 V)
and a “second-surface-channel-type MOSFET” (i.e., Mo-gate transistor)
with a “second threshold voltage” (i.e., 1.3 V) “having an absolute value
greater than an absolute value of said first threshold voltage,” as recited in
claim 1. Pet. 29–34. Petitioner provides an explanation as to why the
Si-gate and Mo-gate transistors are “surface-channel-type MOSFET[s].” Id.
at 18–21, 23–24, 31–32, 34.

7 The three prior art references at issue in this proceeding (Yanagawa, An,
and Houston) were not of record during prosecution of the ’047 patent. See
Ex. 1001, code (56); Pet. 12. Petitioner also provides evidence supporting
its contention that Yanagawa is a prior art printed publication under
35 U.S.C. § 102(b). See Pet. 9–11 (citing Exs. 1004, 1005, 1008,
1025–1037). Patent Owner does not assert otherwise in its Response, and
we agree that Yanagawa is prior art for the reasons stated by Petitioner.
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To illustrate how Yanagawa allegedly discloses the various MOSFET
properties recited in claim 1, Petitioner provides the following annotated
version of Table I of Yanagawa (id. at 23).

Annotated Table I above lists various properties of the Si-gate transistor
(shown in red) and Mo-gate transistor (shown in green), as argued by
Petitioner. Petitioner argues that the Si-gate transistor includes a “first gate
insulating film” (i.e., gate oxide film with 30 nm thickness) formed on the
semiconductor substrate and a “first gate electrode” formed out of a
“poly-silicon film” directly on top of the first gate insulating film, given that
the polysilicon gate is formed immediately after forming the gate oxide
layer. Id. at 35–37. Petitioner further contends that the Mo-gate transistor
includes a “second gate insulating film” (i.e., gate oxide film with 40 nm
thickness) formed on the semiconductor substrate and a “second gate
electrode” formed out of a “refractory metal film” made of a “refractory
metal” (i.e., molybdenum) directly on top of the second gate insulating film,
as shown in Figure 2 of Yanagawa. Id. at 37–42.
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Other than the issue of whether Yanagawa’s Si-gate transistor
constitutes a “first-surface-channel-type MOSFET,” which we address
below, Patent Owner does not dispute that Yanagawa discloses the
remaining limitations of claim 1; therefore, any such arguments are waived.
See Novartis AG v. Torrent Pharms. Ltd., 853 F.3d 1316, 1330 (Fed. Cir.
2017); NuVasive, 842 F.3d at 1380–81; Paper 12, 8 (“Patent Owner is
cautioned that any arguments not raised in the response may be deemed
waived.”). Petitioner’s analysis for each of the limitations discussed above,
supported by the testimony of Dr. Bravman, which we credit, is persuasive.
See Pet. 29–42; Ex. 1003 ¶¶ 88–90, 94–106.

b) Disputed Issue: Whether Yanagawa’s Si-Gate Transistor is a
“Surface-Channel-Type MOSFET”
The sole issue disputed by Patent Owner pertains to the limitation of
claim 1 that the semiconductor device have a “first-surface-channel-type
MOSFET.” Petitioner identifies Yanagawa’s Si-gate transistor as a
“first-surface-channel-type MOSFET” and Yanagawa’s Mo-gate transistor
as a “second-surface-channel-type MOSFET,” and explains why the
transistors are “surface-channel-type.” Pet. 18–21, 23–24, 30–32, 34.
Petitioner contends that both transistors “are N-MOSFETs, i.e., the
source/drain regions are n-type and the substrate is p-type,” with the Si-gate
transistor having a shallow boron (p-type) channel implant and the Mo-gate
transistor having no channel implant. Id. at 23–24, 31–32 & n.11, 34 & n.12
(citing Ex. 1004, 2 (discussing “source and drain n+ junction depth” for the
transistors), 3–4, Table I).
We interpret “surface-channel-type MOSFET” to mean “a MOSFET
in which the channel forms at the surface of the semiconductor substrate,
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rather than slightly under the surface.” See supra Section II.B. Yanagawa
does not include an express statement as to where the Si-gate transistor’s
channel forms. Thus, what we must determine is how a person of ordinary
skill in the art would understand Yanagawa’s Si-gate transistor.8 The parties
and their respective experts have different views. Petitioner contends that a
person of ordinary skill in the art would understand the transistor to have a
channel that forms at the surface of the semiconductor substrate, whereas
Patent Owner contends that such an individual would understand that a
channel also forms below the semiconductor substrate. See Pet. 18–21,
23–24, 31–32, 34; PO Resp. 16–55; Reply 3–20; Sur-Reply 1–23.
As explained in detail below, we understand “surface-channel-type”
and “buried-channel-type” to refer to the location where a channel forms in a
MOSFET when it is ON, based on how the channel region of the MOSFET
is doped, in normal or typical operating conditions. Patent Owner argues
that it is possible to bias Yanagawa’s Si-gate transistor such that a channel
forms below the surface, thus, putting it at odds with our claim interpretation
in some operating conditions. PO Resp. 35–55. For the reasons given
below, we find that Yanagawa’s Si-gate transistor is “surface-channel-type”
because it is doped in such a way that a surface channel, rather than a buried
channel, will form when the transistor is turned ON in normal or typical
operation.
Petitioner provides a detailed explanation, with supporting testimony
from Dr. Bravman, as to why Yanagawa’s transistors are “surface-channel-
type” rather than “buried-channel-type.” Pet. 18–21, 23–24, 31–32, 34

8 Patent Owner does not dispute that Yanagawa’s Mo-gate transistor
constitutes a “second-surface-channel-type MOSFET,” as recited in claim 1.
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(citing Ex. 1003 ¶¶ 61–65, 73, 93, 96). Petitioner argues that “forming a
buried-channel transistor (as opposed to a surface-channel transistor)
involves doping the area underneath the gate oxide with the same type of
dopant as the source/drain regions,” relying on the Chen textbook’s
description of such devices.9 Id. at 32 (citing Ex. 1014, 29–35). For
example, “[f]or n-type MOSFETs [with a p-type semiconductor substrate],
buried-channel transistors . . . are formed by doping the channel with n-type
dopant to create a layer of n-type material that connects the source/drains
regions.” Id. at 19. Petitioner cites evidence in the record supporting that
proposition. Id. at 19–20 & n.8. Chen states that
[a] depletion-mode device is commonly made by forming a thin
n-type surface layer in the p-substrate for n-channel cases or a
thin p-type surface layer in the n-substrate for p-channel cases.
Thus, source and drain are connected with the same type of
semiconductor layer unless this layer is fully depleted by
applying the appropriate gate voltage. The presence of this
surface layer however changes normal MOSFET operation from
surface-channel conduction to buried-channel conduction.
Ex. 1014, 29 (emphasis added).

9 The parties use “surface-channel” and “surface-channel-type,” and
“buried-channel” and “buried-channel-type,” interchangeably. See, e.g.,
Pet. 15, 19–21, 23–24, 26, 30–34; PO Resp. 1–3, 17–25, 33, 35–36, 38,
54–55; Reply 1, 3, 6–9, 12–13, 19; Sur-Reply 1–14. We also understand the
two sets of phrases to each mean the same thing.
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Portions of Figures 2.17(a) and 2.17(b) of Chen are reproduced below.

Figures 2.17(a) and 2.17(b) depict, respectively, buried-channel
enhancement-mode and depletion-mode n-MOSFETs, each with a layer of
n-doped material labeled “n-CHANNEL” connecting the n-type source and
drain. Id. at 29, 31; see also id. at 32, Fig. 2.18 (depicting “[a] typical
buried-channel nMOS” with a channel below the surface of the
semiconductor substrate).
An IEEE article, Michael J. Van der Tol & Savvas D. Chamberlain,
Potential and Electron Distribution Model for the Buried-Channel
MOSFET, IEEE TRANSACTIONS ON ELECTRICAL DEVICES, VOL. 36, NO. 4
(Apr. 1989) (Ex. 1016, “Van der Tol”), states that “[t]he buried-channel
MOSFET is typically realized by implanting a surface layer of impurities
into a substrate of opposite doping.” Id. at 1–4. Figure 1(a) of Van der Tol
is reproduced below.

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Figure 1(a) depicts a “[c]ross section of a typical buried-channel MOSFET
device” with an n-type layer connecting the n-type source and drain regions,
where “[i]n practice the buried-channel device is formed by ion implanting a
donor impurity in to a p-type substrate.” Id. at 2. Dr. Bravman explains that
“[t]his implantation step causes the channel to form further underneath the
surface of [the] semiconductor substrate.” Ex. 1003 ¶ 64 n.5. Petitioner also
points out that all embodiments of surface-channel-type MOSFETs
described in the ’047 patent are N-MOSFETs with p-type channel dopant.
Pet. 21 (citing Ex. 1001, col. 4, l. 57–col. 5, l. 12, col. 7, ll. 1–22);
see Paper 9, 9 (Patent Owner acknowledging that “[a]ll embodiments” have
“source/drain regions doped with n-type dopant, and a channel region doped
with the opposite p-type dopant”). Dr. Bravman opines that the exemplary
embodiments in the ’047 patent “are surface-channel transistors because no
thin layer of n-type material was created that connects the n-type
source/drain regions.” Ex. 1003 ¶ 65.
With respect to Yanagawa’s Si-gate transistor, which has a boron
channel implant, Petitioner reasons as follows:
[F]orming a buried-channel transistor involves doping an N-FET
channel with an N-type dopant (e.g., arsenic or phosphorous), not
boron (which is a P-type dopant). Here, the boron implant
merely increases the threshold voltage of the device by
increasing the concentration of P-type dopant in the channel
region immediately underneath the gate oxide (which resides on
the substrate surface), thereby requiring a larger positive voltage
to induce a channel in the depletion region near the substrate top
surface underneath the gate oxide. The N-FET first transistors
are therefore surface-channel transistors.
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Pet. 32 (citations omitted);10 see Ex. 1003 ¶ 93. Petitioner provides similar
reasoning with respect to Yanagawa’s Mo-gate transistor, which has no
channel implant. Pet. 34; see Ex. 1003 ¶ 96.
Patent Owner responds that Petitioner has not proven that Yanagawa’s
Si-gate transistor is a “surface-channel-type MOSFET,” relying on
supporting testimony from Dr. Kuhn. PO Resp. 19–36. Patent Owner
disputes Petitioner’s position that “the same or different doping type in the
channel region as the source/drain regions is determinative of where channel
formation occurs in a MOSFET.” Id. at 22–24. According to Patent Owner,
Petitioner’s theory that the Si-gate transistor is not a buried-channel
transistor (and, therefore, must be a surface-channel transistor) because
Yanagawa does not disclose doping the channel region with the same type of
dopant as the source and drain regions fails because that type of doping is

10 For purposes of assessing Petitioner’s asserted ground of unpatentability,
we see little practical difference between Petitioner’s proposed interpretation
in the Petition (where a channel forms “near” the top surface of the
semiconductor surface) versus our interpretation (where a channel forms
“at” the surface). Petitioner relies heavily on Chen’s description of the
difference between surface-channel and buried-channel transistors in its
analysis, as do we. See Pet. 18–21; Reply 3 n.1 (“The Board’s modification
of Petitioner’s construction to replace ‘near’ with ‘at’ changes nothing.”);
Dec. on Inst. 25–30; supra Section II.B. Further, the channel formed
between the source and drain naturally will have a width within the
semiconductor substrate. Dr. Bravman explains that “the Board’s
construction is not substantively different than” the proposed interpretation
in the Petition and the word “near” was used merely “to clarify that the
channel does not need to form exclusively at the gate oxide interface. In
other words, with a surface-channel transistor, there will be a channel that
starts at the interface and extends downward such that the channel has a
width.” Ex. 1042 ¶ 27; see also PO Resp. 30 (diagrams showing a “surface
channel” in blue that has a width, such that the entire current flow would not
be precisely at the surface); Ex. 2004 ¶ 70 (same).
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not completely determinative. Id. at 35–36. Rather, “other specific
properties and operating characteristics of the transistor” also can impact
whether a transistor is surface-channel or buried-channel. Id. at 32.
Patent Owner contends that Chen and Van der Tol, cited extensively
in the Petition, do not support Petitioner’s theory and instead demonstrate
that “in a MOSFET with a channel dopant the same as the source/drain
regions (which may be called a buried-channel or ‘BC’ MOSFET), channel
formation can occur at the substrate surface or below it depending on biasing
conditions.” Id. at 22–24 (citing Ex. 1014, 33–35; Ex. 1016, 3, Fig. 2;
Ex. 2004 ¶¶ 83–87).
Patent Owner also makes a number of arguments regarding
“punchthrough.” Id. at 24–33 (citing Ex. 2004 ¶¶ 65–75, 88–93). Patent
Owner asserts that punchthrough “occurs when depletion regions formed by
electric fields produced by the pn-junctions of the source/drain regions
electrostatically couple, allowing carriers to flow between source/drain
regions via merging depletion regions.” Id. at 27. Electric fields produced
from the pn-junctions “cause depletion regions to penetrate into
semiconductor material such that a punchthrough channel forms below the
semiconductor surface.” Id. at 28–29 (citing Exs. 2029, 2038–2040). Patent
Owner argues that
[p]unchthrough current first forms in the absence of gate bias and
is largely independent of increases in gate voltage. . . . Thus,
when punchthrough occurs, the punchthrough channel forms
when the transistor is “off” (below the threshold voltage) and
persists after the transistor is turned “on” (when the gate voltage
exceeds the threshold voltage), so the punchthrough channel
forms throughout the transistor’s entire operating range . . . .
Id. at 30 (citing Exs. 2029, 2039, 2041).

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Patent Owner provides the following illustrative figures (id.).

Figure (A) depicts when a punchthrough channel (shown in red) “forms
below the substrate surface at zero gate bias,” Figure (B) depicts when the
gate voltage Vg has been increased to the threshold voltage Vth, “caus[ing] a
surface channel to form” (shown in blue), and Figure (C) depicts when the
gate voltage Vg is much greater than the threshold voltage Vth and the
channels “combine,” according to Patent Owner and Dr. Kuhn. Id. at 30–31.
Patent Owner argues that punchthrough degrades transistor performance and
must be “remediat[ed]” in various ways, such as “increasing doping
concentration and depth in the channel region.” Id. at 31–32. Other
parameters, such as channel length and drain voltage, however, are fixed and
cannot be changed to reduce punchthrough. Id. Patent Owner’s position is
that “whether channel formation occurs in a short-channel MOSFET at or
below the semiconductor substrate depends on other specific properties and
operating characteristics of the transistor beyond the doping type in the
channel region relative to the source/drain regions”; channel doping is not
“determinative.” Id. at 32–33.
Patent Owner cites Chen as supporting its position regarding
punchthrough. Id. at 25–26. Specifically, Figure 2.21 of Chen depicts a
short-channel MOSFET “that does not include a same-type dopant layer, but
that has a channel that forms below the semiconductor surface when
designed with the transistor properties shown for” the particular MOSFET of
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Figure 2.22. Id. Patent Owner provides the following versions of Figures
2.21 and 2.22(b) of Chen, with annotations in red (id. at 26).

The annotated figures depict a 1.5 µm short-channel MOSFET that “will
have significant punchthrough current flowing through a subthreshold
channel” according to Patent Owner. Id.; see Ex. 1014, 36–37 (“Figure 2.22
shows current-voltage characteristics in the subthreshold region for devices
with various channel lengths.” (emphasis added)).
Finally, Patent Owner clarifies in its Sur-Reply that it is not arguing
that “leakage current (e.g., punchthrough current) defines whether a
transistor is [surface-channel] or [buried-channel]” and instead takes no
position on “what ‘defines’ surface-channel-type or buried-channel-type”
MOSFETs. Sur-Reply 7–8 (emphasis omitted). Patent Owner’s contention
is simply that Petitioner’s evidence does not establish that Yanagawa’s
Si-gate transistor is a “surface-channel-type MOSFET” under either the
interpretation Petitioner proposed in the Petition or our interpretation. Id.
at 7.

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(1)
Having reviewed all of the parties’ arguments and cited evidence,
we agree with Petitioner. First, whether a transistor is surface-channel or
buried-channel depends on the structure of the transistor rather than the
mode or conditions under which it may operate at different times.
Consistent with our interpretation based on Chen and other evidence,
a transistor’s structure (e.g., the structure and doping of its channel region)
defines where the channel between the source and drain regions will form
when the transistor is ON. A buried-channel transistor is typically formed
by doping the channel region with the same type of dopant as the source and
drain regions, such that when ON, a channel forms below the surface of the
semiconductor substrate, rather than at the surface.
Chen explicitly states that it is “[t]he presence of [the] surface layer”
with dopant of the same type as the source and drain regions that “changes
normal MOSFET operation from surface-channel conduction to
buried-channel conduction.” Ex. 1014, 29 (emphasis added), Figs. 2.17(a),
2.17(b). Chen states that the source and drain regions are connected “unless
[the] layer is fully depleted by applying the appropriate gate voltage.” Id.
at 29. But Chen never states that operating conditions of the MOSFET
impact whether the device is surface-channel or buried-channel; rather, it is
the “presence” of the surface layer in “normal” conditions that makes it
buried-channel. Van der Tol similarly states that a “buried-channel
MOSFET is typically realized” by implanting a surface layer of dopant of
the same type as the source and drain regions. Ex. 1016, 1. And two
textbooks include similar disclosures as well. BiCMOS Technology and
Applications (A.R. Alvarez ed.) (1993) (Ex. 1043, “Alvarez”), describes
“surface-channel” MOSFETs as “the case when the polysilicon gates are
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N-doped and P-doped for the NMOS and PMOS devices respectively.” Id.
at 8. Alvarez then describes an alternative where “the PMOS channel [is]
counterdoped to achieve [a] desired threshold . . . . This produces a
buried-channel device.” Id. (emphasis added). Neil H. E. Weste & Kamran
Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective
(1993) (Ex. 1045, “Weste”), similarly explains that adjusting the threshold
voltage of a p-device “is done by introducing an additional negatively
charged layer at the silicon/oxide interface. This moves the channel from
the silicon/oxide interface further into the silicon, creating a ‘buried
channel’ device.” Id. at 20 (emphasis added). Thus, the “normal,” or
“typical[],” understanding of a person of ordinary skill in the art is that a
transistor may be “change[d]” into a buried-channel transistor by doping the
channel region to create a thin surface layer of the same type of dopant as
the source and drain regions. See Ex. 1014, 29; Ex. 1016, 1. Doping in that
manner causes the channel to form below the surface; absent such a change
to the normal conditions, the transistor’s structure will cause channel
formation at the surface. Yanagawa has no such doping that would make it
a buried-channel transistor. See Pet. 19–20, 31–32; Ex. 1003 ¶¶ 63–64, 73,
91–93.
Petitioner acknowledges, and the record reflects, that it is also
possible for “some other exotic structural changes [to] bury the channel in
the ON state.” See Reply 7 n.3; Tr. 6:12–7:7 (Petitioner acknowledging that
doping the channel region with the same type of dopant as the source and
drain is not “100 percent determinative” of whether a transistor is
surface-channel or buried-channel). For example, one reference (filed more
than three decades after Yanagawa was published) describes a method for
forming a buried-channel FET including “forming a doped shielding layer
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on the substrate in a channel region . . . to displace a conducting channel
away from a gate-interface region.” See Ex. 1004, 1; Ex. 2003, codes (22),
(63), ¶ 6. The buried-channel FET includes, above the surface of the
semiconductor substrate, gate 802, dielectric layer 804, and doped layer 702
“of a type opposite that in the drain and source regions” between spacers
406. Ex. 2003 ¶¶ 41–42, Figs. 7, 8. But, again, it is the structure of the
transistor that causes the channel to form below the surface in such cases.
The general rule is that reflected in Chen, Van der Tol, Alvarez, and Weste.
And there is no contention that Yanagawa possesses such “exotic” structures
that would bury the channel of its Si-gate transistor.
The evidence is uniform that the structure of a transistor dictates
whether it is surface-channel or buried-channel, not the mode or conditions
under which it may operate at different times.11 Van der Tol describes
buried-channel transistors as follows:

11 Patent Owner contends that Petitioner’s arguments in the Reply regarding
transistor structure are improper new arguments that cannot be considered.
Sur-Reply 3–6. We disagree. Petitioner’s arguments in the Petition
regarding interpretation of “surface-channel-type MOSFET” and whether
Yanagawa’s Si-gate transistor is a “surface-channel-type MOSFET” pertain
to transistor structure—namely, the transistor’s channel region and how it is
doped. See Pet. 18–21, 30–32. Moreover, those arguments rely heavily on
Chen’s descriptions of transistor structure, as we recognized in the Decision
on Institution. See id. at 18–21; Dec. on Inst. 27–30, 35–36 (citing, among
other things, Van der Tol’s statement that “the buried-channel MOSFET
refers to a device structure and not a device designed to operate in a
particular mode” and Chen’s descriptions of transistor structure (emphasis
added)). We conclude that Petitioner’s arguments in the Reply are proper
and should be considered. See 37 C.F.R. § 42.23(b); Apple Inc. v. Andrea
Elecs. Corp., 949 F.3d 697, 706–707 (Fed. Cir. 2020) (concluding that the
petitioner’s reply arguments did not change the asserted “legal ground” and
were not “the types of arguments that [the court had] previously found to
raise a ‘new theory of unpatentability’”); Chamberlain Group, Inc. v. One
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The terms depletion-mode MOSFET and buried-channel
MOSFET have been used synonymously in the literature. This,
however, is not entirely valid and a clear distinction between the
two is necessary. The depletion-mode MOSFET refers to a
device that under zero gate bias exhibits a significant channel
conductance. The threshold voltage of such an n-channel device
is less than zero volts and a gate voltage, less than the threshold
voltage, is required to reduce the channel conductance to zero.
On the other hand, the buried-channel MOSFET refers to a
device structure and not a device designed to operate in a
particular mode. Strictly speaking, the buried-channe1
MOSFET can be fabricated to operate as a normally-on
(depletion-type) device or a normally-off (enhancement-type)
device, both of which are considered to be buried-channel
MOSFET’s.
Ex. 1016, 2 (emphasis added; citation omitted). Thus, what makes a
MOSFET buried-channel is its structure, not its operating mode. Van der
Tol further states that “the BC-MOSFET can operate as a surface-channel
MOSFET or a buried-channel MOSFET depending upon the applied
biasing. These modes of operation can be directly inferred from the
potential distribution in the x direction within the channel of the device.” Id.
at 3. Thus, a buried-channel transistor can be operated in various modes of

World Techs., Inc., 944 F.3d 919, 924–925 (Fed. Cir. 2019) (“Parties are not
barred from elaborating on their arguments on issues previously raised.”);
see also Dec. on Inst. 30 (“The parties are encouraged to address the
interpretation of the term [‘surface-channel-type MOSFET’] in their papers
during trial.”); Patent Trial and Appeal Board Consolidated Trial Practice
Guide (Nov. 2019) (“TPG”), 73, available at https://www.uspto.gov/
TrialPracticeGuideConsolidated (“[T]he Board will permit the petitioner, in
its reply brief, to address issues discussed in the institution decision. The
patent owner will similarly be allowed to address the institution decision in
its sur-reply, if necessary to respond to petitioner’s reply.”).
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operation (e.g., different bias conditions), but that does not change what type
of transistor it is.12
Chen similarly indicates that the mode of operation of a
buried-channel transistor can depend on the applied biasing. Chen states
that “[t]he behavior of an enhancement-mode buried-channel device is a
strong function of gate voltage. At high Vg, i.e., Vg >> Vt, the energy bands
at the Si surface are lowered sufficiently to cause the device to operate in a
surface-channel mode.” Ex. 1014, 33–35; see also id. at 32 (“A
buried-channel MOSFET can be an enhancement-mode or a depletion-mode
device, depending on the doping level and the depth of the thin surface
layer.”). In other words, at very high gate voltage (greater than the threshold
voltage at which the transistor is ON), the disclosed buried-channel
transistor can operate in a surface-channel mode, but that does not mean that
it is no longer a buried-channel transistor.

12 Dr. Kuhn points to Figure 10(b) of Van der Tol as showing “the operation
mode changing in the same device as a function of bias conditions,”
annotating the figure twice to show the alleged “surface channel and its
operating bias conditions” and “buried channel and its operating bias
conditions.” Ex. 2004 ¶ 84; see Sur-Reply 8–9. Figure 10(b) of Van der
Tol, however, is labeled “Normally-Off Buried-Channel MOSFET” and
described as a “[b]uried-channel MOSFET device.” Ex. 1016, 13–14. Van
der Tol does not call it a “Buried-Channel MOSFET” under some operating
conditions and a “Surface-Channel MOSFET” under others. Thus,
regardless of the transistor’s operation mode and bias conditions applied, it
is still a buried-channel transistor. See Reply 8–9. Further, Dr. Kuhn
testifies that the two annotated versions of Figure 10(b) show that “the same
device in different modes of operation can operate as a surface channel . . .
or as a buried channel.” Ex. 1041, 322:6–323:18. It is unclear, however,
how a person of ordinary skill in the art would ever determine whether a
device is a surface-channel transistor or buried-channel transistor if it could
be either depending on mode of operation as Dr. Kuhn opines.
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We credit Dr. Bravman’s explanations, which are consistent with the
evidence of record. See Ex. 1042 ¶¶ 17–23. In particular, “the structure of
the transistor (in particular, its channel structure and its doping) determines
where a transistor’s channel forms during normal operating conditions and
in the ON state, and thus a [person of ordinary skill in the art] looks to the
structure of a transistor to determine whether it is a surface-channel
transistor.” Id. ¶ 21. Further, a person of ordinary skill in the art would
have known that “it was possible to operate a surface-channel or
buried-channel transistor in particular regimes that will result in various
types of current flow, but that is irrelevant to whether that transistor is a
surface-channel or buried-channel transistor.” Id. ¶¶ 12, 23. Patent Owner
does not point to, and we do not find, any reference stating that a transistor’s
operating mode dictates whether it is deemed a surface-channel or
buried-channel transistor.

(2)
Next, we find that the record also does not support Patent Owner’s
position that how a transistor operates in the subthreshold regime (i.e., the
applied gate voltage is below the threshold voltage, such that the transistor is
OFF as shown in Figure (A) above) impacts whether it is surface-channel or
buried-channel. The evidence is to the contrary.
Chen describes MOSFETs as follows. An N-MOSFET consists of
“a MOS capacitor and two n+ regions in a p-type Si substrate.” Ex. 1014,
18, Fig. 2.9. “The two n+ regions are isolated by the p-type substrate and no
current can flow unless the surface of p-substrate is inverted by an adequate
voltage being applied on the gate. At this point, an n-type inversion layer is
formed, called an n-channel, connecting source and drain . . . .” Id. at
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18–19. Chen expressly states that “[w]hen a voltage greater than Vt is
applied to a gate, the semiconductor surface is inverted to n-type and
a MOSFET channel is formed.” Id. at 21 (emphasis added). Then, when
describing buried-channel MOSFETs, Chen states that the surface layer of
the same type of dopant as the source and drain regions, which changes the
MOSFET to “buried-channel conduction,” connects the source and drain
regions “unless this layer is fully depleted by applying the appropriate gate
voltage.” Id. at 29. Chen refers to “carriers propagat[ing]” either “at” or
“under” the semiconductor surface as defining whether a MOSFET is
surface-channel or buried-channel. Id.; see also Ex. 1043, 8 (referring to the
“channel” that makes a transistor buried-channel); Ex. 1045, 20 (same).
Given these disclosures, we agree with Dr. Bravman that “[a]
‘channel’ refers to a conductive path between the source and drains regions
when a transistor transitions from an OFF state to an ON state, i.e., the gate
voltage exceeds the threshold voltage,” and “the channel” for purposes of
determining whether a transistor is a “surface-channel-type MOSFET” under
our interpretation (premised on Chen’s definition) is “the current flow
between the source and drain regions when the transistor is in the ON
condition.” See Ex. 1003 ¶ 44; Ex. 1042 ¶¶ 14, 17–20, 28; Reply 11–12;13
supra Section II.B.

13 Patent Owner contends that Petitioner’s arguments in the Reply regarding
transistor operation when OFF and ON are improper new arguments that
cannot be considered. Sur-Reply 10–11. We disagree. Petitioner’s
arguments regarding claim interpretation and our analysis in the Decision on
Institution, both relying on Chen, addressed where “the channel” of a
transistor forms. See Pet. 18–21, 30–32; Dec. on Inst. 27–30. Patent Owner
argues in its Response that formation of a “channel” at any point must be
considered. PO Resp. 27–33, 35–55. Petitioner disagrees and responds that
the appropriate consideration is formation of a channel from turning the
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Thus, we disagree with Patent Owner that the Si-gate transistor’s
subthreshold operation impacts whether the transistor is surface-channel or
buried-channel. See PO Resp. 30–31 (arguing that all three conditions
shown in Figures (A)–(C) above (subthreshold, at the threshold voltage, and
above the threshold voltage) must be considered); Tr. 57:24–59:20 (arguing
that the propagation of carriers in the semiconductor substrate “at any point”
is relevant). What we must determine is where the channel created in the
semiconductor substrate between the source and drain as a result of turning
the transistor ON (i.e., increasing the gate voltage to the threshold voltage)
forms—at the surface or under the surface. See supra Section II.B.

transistor ON. Reply 9–13. Our rules countenance such rebuttal. See
37 C.F.R. § 42.23(b) (“A reply may only respond to arguments raised in the
corresponding . . . patent owner response.”); TPG 73–74 (“Petitioner may
not submit new evidence or argument in reply that it could have presented
earlier, e.g. to make out a prima facie case of unpatentability. . . . Generally,
a reply or sur-reply may only respond to arguments raised in the preceding
brief. . . . ‘Respond,’ in the context of 37 C.F.R. § 42.23(b), does not mean
proceed in a new direction with a new approach as compared to the positions
taken in a prior filing. While replies and sur-replies can help crystalize
issues for decision, a reply or sur-reply that raises a new issue or belatedly
presents evidence may not be considered.”); Anacor Pharms., Inc. v. Iancu,
889 F.3d 1372, 1380–81 (Fed. Cir. 2018) (noting that “the petitioner in an
inter partes review proceeding may introduce new evidence after the petition
stage if the evidence is a legitimate reply to evidence introduced by the
patent owner,” and determining that it was proper for the Board to rely on
two references not cited in the petition but discussed at length in the “patent
owner’s response and related submissions”); Idemitsu Kosan Co., Ltd. v.
SFC Co. Ltd., 870 F.3d 1376, 1380–81 (Fed. Cir. 2017) (permitting rebuttal
argument from a petitioner in response to a patent owner’s teaching away
argument, as such argument was “simply the by-product of one party
necessarily getting the last word”).
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Importantly, it is undisputed that Yanagawa’s Si-gate transistor has
a channel form at the semiconductor surface when it is ON. See Pet. 32;
PO Resp. 30 (surface channel shown in blue in Figure (B) above); Ex. 1041,
276:5–14 (Dr. Kuhn testifying that “the Yanagawa silicon gate transistor has
a surface channel” when above “roughly the vicinity of Vt”); Ex. 1042 ¶ 16
(Dr. Bravman testifying that “Yanagawa’s Si-gate transistor has a
surface-channel when it is ON (above threshold)”); Ex. 2004 ¶ 71 (Dr. Kuhn
testifying that “[i]ncreasing the gate voltage causes a surface channel to form
as the gate voltage reaches the threshold voltage (Vg-Vth) as shown in [Figure
(B)]”). That alone makes the Si-gate transistor a “surface-channel-type
MOSFET” under our interpretation.

(3)
Patent Owner argues that a “punchthrough channel” (shown in red in
Figure (B) of page 30 of Patent Owner’s Response, reproduced above) exists
(in addition to the surface channel, shown in blue in Figure (B) above) when
the threshold voltage is reached, and the presence of that “punchthrough
channel” means that the Si-gate transistor is not surface-channel.
See PO Resp. 30; Sur-Reply 7–8 (clarifying that Patent Owner is not arguing
that punchthrough current “defines” whether a transistor is surface-channel
or buried-channel). We find that the evidence does not support a finding
that punchthrough current impacts whether a transistor is surface-channel or
buried-channel.
The parties’ experts agree that all short-channel transistors have some
amount of punchthrough current, even if very small. See Ex. 1041,
28:9–29:8, 32:4–20; Ex. 1042 ¶ 25. Yanagawa, for instance, refers to
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“subthreshold leakage”14 of the disclosed Si-gate and Mo-gate transistors.
Ex. 1004, 2–3. However, Patent Owner does not point to, and we do not
find, any reference stating that the presence of punchthrough current can
make a transistor buried-channel, or that a person of ordinary skill in the art
would need to determine the level of punchthrough current for a transistor
and determine whether it is “significant” enough that the transistor should be
deemed buried-channel. See PO Resp. 27–31, 39–46 (citing Exs. 2029,
2038–2041).
The evidence of record discusses surface-channel and buried-channel
transistors at length, but never states that punchthrough current has any
effect on the distinction between them. Chen discusses short-channel
effects, “punchthrough current per unit channel width,” and “subthreshold
swing,” but identifies the distinction between surface-channel and
buried-channel transistors as solely being where carriers propagate when the
transistor is ON, without mentioning punchthrough current. See Ex. 1014,
29, 35–36; see Tr. 34:10–15 (Patent Owner acknowledging that Chen does
not state that punchthrough current can cause a transistor to be
buried-channel). Alvarez also mentions “short-channel effects” and
“punchthrough” in “surface-channel devices” and “buried-channel
device[s],” but never indicates that punchthrough current impacts whether
the transistor is surface-channel or buried-channel. See Ex. 1043, 6–11.
Another IEEE article, Genda J. Hu & Richard H. Bruce, Design Tradeoffs
Between Surface and Buried-Channel FET’s, IEEE TRANSACTIONS ON
ELECTRON DEVICES, VOL. ED-32, NO. 3 (Mar. 1985) (Ex. 1046, “Hu”),

14 Punchthrough current is a component of subthreshold leakage.
See Ex. 1042 ¶ 38; Ex. 1041, 172:15–174:14.
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describes a study of various surface-channel and buried-channel FETs and
mentions “short-channel effects” and “punchthrough,” but never suggests
that punchthrough current impacts a transistor’s classification. Id. at 2–4.
For example, Hu discloses:
Because the compensating VT adjustment implant is very
shallow, this lightly doped region, and hence the punchthrough,
occurs close to the surface for buried-channel devices. For
surface-channel devices, the n-type implant creates a higher
surface doping causing the drain-induced barrier lowering to
occur away from the surface. With punchthrough closer to the
surface in the buried-channel devices, the gate has more control;
consequently, the dependence of the gate swing on the channel
length is less abrupt.
Id. at 4. Also, the Specification of the ’047 patent does not mention
punchthrough current, even though its exemplary surface-channel-type
MOSFETs would have some amount of punchthrough current.
See Ex. 1041, 250:3–20.
Given the evidence discussed above, we credit Dr. Bravman’s
testimony regarding punchthrough current. See Ex. 1042 ¶¶ 21, 24–26, 29.
In particular, we agree that when discussing surface-channel and
buried-channel transistors, “the literature does not discuss whether these
transistors have leakage, how much leakage they have in particular
conditions (e.g., the subthreshold region), or how leakage affects the
surface-channel versus buried-channel transistor classification, because such
conditions are irrelevant to the classification.” Id. ¶ 21. A person of
ordinary skill in the art “would not consider the amount of punchthrough to
be relevant to whether a transistor is a surface-channel transistor.” Id. ¶ 26.

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(4)
Even if punchthrough current were relevant to whether a transistor is
surface-channel or buried-channel and could be considered the relevant
“channel” under our interpretation (it cannot), we would not agree with
Patent Owner’s arguments regarding the alleged punchthrough current for
Yanagawa’s Si-gate transistor. Patent Owner contends, with supporting
testimony from Dr. Kuhn, that Petitioner “improperly ignored disclosures in
Yanagawa that would have given a [person of ordinary skill in the art]
reasons to conclude Yanagawa’s Si-gate MOSFETs have a channel that
forms below the semiconductor surface,” in particular disclosures that show
the Si-gate transistor has a punchthrough channel that could not be
remediated. PO Resp. 36–53; see Ex. 2004 ¶¶ 95–139.
Patent Owner argues that “Yanagawa’s Si-gate MOSFETs were
optimized for high-speed performance required for peripheral circuitry by
having: (1) a low threshold voltage (0.5 V) it achieved by reducing channel
length to 1 µm; and (2) a 5-V power supply to bias the drain.” PO Resp. 39
(citing Ex. 1004, 2). According to Patent Owner, both features result in
significant punchthrough. Id.
First, Patent Owner points to Figure 5 of Yanagawa (captioned
Figure 3), providing the annotated version reproduced below (id. at 40).

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The annotated figure plots threshold voltage (Vth) versus effective channel
length (Leff), where “[t]he point where the curve begins to slope (in the
direction of decreasing channel length)” is called the “Vth roll-off” and “[t]he
further the voltage threshold is below the Vth roll-off, the more extensive the
short-channel effects.” Id. at 40–41. According to Patent Owner, the
disclosed curve “indicates the Si-gate MOSFET has substantial
short-channel effects because the channel had to be reduced by 1-µm from
the point where the Vth roll-off begins (~ 2-µm) to obtain the 0.5-V threshold
voltage Yanagawa reported was needed to meet speed requirements for the
64-kbit RAM.” Id. at 41.
Second, Patent Owner argues that a person of ordinary skill in the art
would understand that Yanagawa’s “high 5-V supply voltage needed to meet
high-speed requirements of the 64-kbit RAM to bias the drain of the Si-gate
MOSFETs . . . would have needed far more significant punchthrough
remediation than disclosed in Yanagawa to avoid formation of a substantial
punchthrough channel below the semiconductor surface.” Id. at 41–42.
Patent Owner next analogizes Yanagawa’s Si-gate transistor to those
disclosed in Chen and another reference, John J. Barnes, Katsuhiro
Shimohigashi, & Robert W. Dutton, Short-Channel MOSFET’s in the
Punchthrough Current Mode, IEEE TRANSACTIONS ON ELECTRON DEVICES,
VOL. ED-26, NO. 4 (Apr. 1979) (Ex. 2029, “Barnes”). PO Resp. 43–46.
Patent Owner contends that Barnes describes a Si-gate transistor with
properties similar to those of Yanagawa’s Si-gate transistor (e.g., effective
channel length, drain voltage, gate oxide thickness, source/drain junction
depth, channel dose, and substrate doping concentration) and “prohibitively
high” punchthrough current. Id. at 43–44 (emphasis omitted). Patent Owner
argues that Chen discloses MOSFETs with similar properties and better
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punchthrough remediation than Yanagawa, but the MOSFETs still “exhibit
short-channel effects.” Id. at 44–46.
Patent Owner further contends that Yanagawa’s “design constraints,”
such as its fixed channel length, fixed drain voltage, and maximum 0.5-V
threshold voltage, “precluded the use of a host of punchthrough remediation
techniques,” and Yanagawa does not disclose any other “punchthrough
mitigation techniques,” such as lightly-doped drain (LDD) regions or halos,
that “would have prevented the substantial punchthrough channel.” Id. at
46–48.
Finally, Patent Owner acknowledges that Yanagawa “provides a table
that identifies ‘subthreshold leakage’ of Yanagawa’s Si-gate MOSFET as
75 mV/dec,” which is “a value not characteristic of a significant
punchthrough channel,” but asserts that “this subthreshold leakage value is
inconsistent with: (1) other data Yanagawa discloses about the Si-gate
MOSFET that a [person of ordinary skill in the art] would have understood
results in a substantial punchthrough channel, corroborated by Barnes and
Chen; and (2) the leakage value provided for Yanagawa’s Mo-gate
transistor” (i.e., 85 mV/dec).15 Id. at 48–53. Regarding the latter, Patent
Owner argues that given “Yanagawa’s disclosure that short-channel effects
were avoided for the Mo-gate MOSFETs but only minimized for the Si-gate
MOSFETs,” a person of ordinary skill in the art “would have expected that
Yanagawa’s Mo-gate MOSFETs would have exhibited better ‘subthreshold
leakage’ than the Si-gate MOSFETs, not worse as reported in Yanagawa’s

15 The parties’ experts explain that Yanagawa’s subthreshold leakage values,
expressed as millivolts per decade (mV/dec), are known as “subthreshold
swing” (SS). See Ex. 1042 ¶ 37; Ex. 2004 ¶¶ 126–127; Ex. 1014, 36–37.
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table.” Id. at 50 (citing Ex. 1004, 3 (Table I reproduced in Section II.D.1
above)).
Petitioner disputes Patent Owner’s view of how a person of ordinary
skill in the art would understand Yanagawa, relying on the testimony of
Dr. Bravman. Reply 13–20. Having reviewed all of the parties’ arguments
and cited evidence, we agree with Petitioner and credit Dr. Bravman’s
supporting testimony, which is consistent with the evidence of record.
See Ex. 1042 ¶¶ 30–42.
As an initial matter, the point at which punchthrough current allegedly
becomes a “punchthrough channel” (such that a transistor would be
buried-channel rather than surface-channel in Patent Owner’s view) is not
clear from Patent Owner’s arguments and Dr. Kuhn’s testimony. See
PO Resp. 39–46 (arguing that the properties of Yanagawa’s Si-gate
transistor result in “significant” punchthrough, such that the transistor has a
“substantial” punchthrough channel); Sur-Reply 13 (arguing that “[t]he
evidence establishes a [person of ordinary skill in the art] considered
punchthrough current to be a channel,” but not quantifying the amount at
which it is considered a punchthrough “channel”), 14–18 (arguing that a
“non-negligible” punchthrough channel below the semiconductor substrate
surface cannot “be ignored when determining whether a MOSFET is
surface-channel-type,” and Yanagawa has a “significant” or “substantial”
punchthrough channel); Ex. 1041, 56:5–23 (Dr. Kuhn opining that
“[a] surface-channel transistor is a device that operates with a surface
channel throughout its operating regime and has no significant buried
channel,” “[a] buried-channel device is a device that has a buried channel
throughout its operating range and no significant surface channel,” and other
transistors are “neither”), 57:10–58:7, 145:16–148:25 (Dr. Kuhn testifying
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that 62 mV/dec of subthreshold swing is associated with “an ideal
MOSFET” and at 100 mV/dec, “the device would be recognized, in general,
to have significant punchthrough,” but “between 100 and 62 there’s a gray
area” where “you need more data to see if it’s significant enough”),
153:19–154:12 (Dr. Kuhn acknowledging that she is not aware of “any
literature describing providing a measure of what subthreshold swing value
determines a surface-channel versus a buried-channel transistor”).16 Thus,
under Patent Owner’s reasoning, there does not appear to be a clear line on
which a person of ordinary skill in the art could determine if the amount of
punchthrough current for a transistor is “significant” enough to constitute a
channel below the surface of the semiconductor substrate.
Regardless, we find Petitioner’s contentions regarding how a person
of ordinary skill in the art would understand Yanagawa to be persuasive.
First, Yanagawa expressly states that its Si-gate transistor has three
properties that would reduce punchthrough current. Yanagawa states that
(1) the “[s]hallow” 0.25-µm depth of the source/drain junctions is “sufficient
to minimize short-channel effects,” (2) the gate oxide layer is “thin” to
“minimize subthreshold leakage,” and (3) the “substrate concentration” was

16 Dr. Kuhn testifies that transistors exist that are neither surface-channel nor
buried-channel, but is not aware of any document describing such transistors
or specifying what those in the art would call them. Ex. 1041, 56:24–57:9;
Tr. 61:7–23; see also Tr. 49:13–23 (Patent Owner acknowledging that there
is no reference in the record describing the situation shown in Figure (B)
above where a surface channel and alleged sub-surface punchthrough
channel both exist when the transistor is ON). We likewise do not find
anything in the record describing a category of transistors that is neither
surface-channel nor buried-channel, or anything in Yanagawa indicating that
a person of ordinary skill in the art would understand its Si-gate transistor to
be in such a category.
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“determined to suppress the . . . subthreshold leakage.” Ex. 1004, 2–3.
Yanagawa further states that the disclosed device was “experimentally
fabricated” and tested to obtain various data (e.g., output data signal, access
time, word-line delay). See Reply 14; Ex. 1042 ¶¶ 32–33; Ex. 1004, 1, 4–5.
Patent Owner responds that Yanagawa “does not quantify what it
means to ‘minimize’ short-channel effects” or explain that the disclosed
remediation techniques are sufficient to prevent significant punchthrough.
See PO Resp. 54; Sur-Reply 17–20. We find such disclosure unnecessary
for a person of ordinary skill in the art to understand Yanagawa, however.
Yanagawa plainly intended for the three properties to minimize
short-channel effects, and subthreshold leakage in particular, and,
importantly, the record reflects that each of those properties was known in
the art to reduce punchthrough current. See Reply 15; Ex. 1042 ¶ 34;
Ex. 1043, 7 (“Short-channel effects can be minimized by increasing the
background concentration . . . . Another possibility is to decrease the gate
oxide thickness; the thinning of the gate places the gate electrode closer to
the channel and therefore gives it greater control of the channel.”), 12
(“By minimizing the junction depth of the source/drains, better
short-channel effects . . . is achieved.”); Ex. 1048, 8 (describing a type of
contact for the source and drain where “the junction depth can effectively be
made zero to minimize the short-channel effects”). Given the clear
disclosures that Yanagawa took steps to reduce short-channel effects, and
subthreshold leakage in particular, it is difficult to see how a person of
ordinary skill in the art reading Yanagawa would reach the opposite
conclusion—namely, that the Si-gate transistor in fact exhibits short-channel
effects and its punchthrough current would be so high as to cause a channel
below the semiconductor surface, as Patent Owner contends.
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Moreover, Yanagawa expressly discloses a value of subthreshold
leakage (75 mV/dec) for the Si-gate transistor that the evidence indicates is
insignificant.17 See Ex. 1004, 3; Ex. 1042 ¶ 37 (Dr. Bravman agreeing that
75 mV/dec is not characteristic of significant punchthrough current and
stating that “[a]t the time of Yanagawa’s device, a number less than []
approximately 95 mV/dec was generally considered acceptable”); Ex. 1043,
7–8 (“[T]he swing S is used to quantify the amount that the gate voltage
must be reduced to decrease the current by one decade. . . . Acceptable
values for S are 95mV/decade or less.”); Ex. 2004 ¶ 125 (Dr. Kuhn
acknowledging that 75 mV/dec is “not characteristic of [a] significant
punchthrough channel”).
We find unavailing Patent Owner’s arguments that Yanagawa’s
disclosed value of 75 mV/dec is incorrect. See PO Resp. 48–53. We do not
agree that the disclosed value is inconsistent with the rest of Yanagawa,
given the statements discussed above that subthreshold leakage was
minimized. Further, regarding Yanagawa’s disclosure that short-channel
effects are “avoid[ed]” for the Mo-gate transistor (with 85 mV/dec
subthreshold leakage) but “minimiz[ed]” for the Si-gate transistor (with
lower 75 mV/dec subthreshold leakage), we see little difference between the
terminology “avoid” and “minimize,” and certainly not enough to conclude
that the reference to 75 mV/dec is in error. See Ex. 1004, 2–3. And
Dr. Bravman points to at least one critical factor that explains the difference

17 75 mV/dec is below 100 mV/dec where a device would be recognized to
have “significant punchthrough” in Dr. Kuhn’s opinion, and within the
62–100 mV/dec “gray area” she described where punchthrough may be
“significant enough” for the transistor to be buried-channel. See Ex. 1041,
145:16–148:25.
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in values for the Mo-gate and Si-gate transistors, which we find persuasive:
“[T]he SS value defines the entire range of subthreshold leakage, but
short-channel effects (e.g., punchthrough current) are only one component of
this leakage. Thus, statements regarding short-channel effects are not
directly comparable to SS values because SS value[s] measure more than
just leakage from short-channel effects.” Ex. 1042 ¶ 38 (citation omitted);
see Ex. 1041, 172:15–23 (Dr. Kuhn acknowledging that leakage current
broadly relates to “the channel from source to drain,” “from the gate to the
body,” etc.).
Second, with respect to Patent Owner’s comparisons of Yanagawa’s
Si-gate transistor to the transistors of Barnes and Chen: although the
transistors share certain properties, Yanagawa’s Si-gate transistor differs
from those disclosed in Barnes and Chen in numerous ways that would
impact the level of punchthrough current. See Ex. 1042 ¶¶ 41–42. Barnes,
for example, “has source/drain junctions that are not as shallow as
Yanagawa,” “has a lower substrate doping concentration, “is silent on its
channel implant depth,” and “has a higher drain voltage.” Id. ¶ 41; see
Ex. 1004, 2–3; Ex. 2029, 4–6. And “Yanagawa employs a substrate doping
concentration that is an entire order of magnitude higher than Chen’s
substrate doping for its 2.5-V transistor.” Ex. 1042 ¶ 42; see Ex. 1004, 3;
Ex. 1014, 131. Neither reference mentions a “punchthrough channel.”
Thus, we do not agree that a comparison to Barnes or Chen indicates that
Yanagawa’s Si-gate transistor has a substantial punchthrough channel, as
Patent Owner contends.18

18 Dr. Kuhn also testifies that based on the comparison to the Barnes
transistor, Yanagawa’s Si-gate transistor “would have current leakage at
zero gate bias on the same order of magnitude as the current flowing through
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Third, with respect to Patent Owner’s argument regarding
Yanagawa’s Vth-Leff curve shown above: Patent Owner’s position is that
Yanagawa “had to” reduce its channel length (from approximately 2-µm to
1-µm) to set its threshold voltage at 0.5 V. PO Resp. 40–41. Although
Yanagawa discloses that “[t]o make 0.5 ± 0.1-V threshold voltage, it is
necessary to make 1 ± 0.1-µm effective channel length,” Yanagawa
discloses at least three other properties that would alter the transistor’s
threshold voltage: the channel implant, thin gate oxide, and relatively high
substrate dopant concentration. See Ex. 1042 ¶ 39; Ex. 1004, 3 (“Shallow
B+ implantation was made for threshold-voltage adjustment.”) (gate oxide
thickness of “30 nm” for the Si-gate transistor, less than that for the Mo-gate
transistor); Ex. 1049, 4 (disclosing that threshold voltage depends on, among
other things, “channel length,” “substrate doping,” and “oxide thickness”).
Accordingly, we do not agree with the premise of Patent Owner’s argument,
and find that Yanagawa’s channel length and threshold voltage do not show
that the Si-gate transistor has a substantial punchthrough channel, as Patent
Owner contends.

the transistor resulting from applying the 0.5-V threshold voltage to the
gate,” but acknowledges that such a device in which current flow in the
OFF state (shown in Figure (A) above) is on the same order of magnitude as
current flow in the ON state (shown in Figure (B) above) is “just not
something people do” and “the circuit fails for a variety of reasons.” See
Ex. 2004 ¶ 137; Ex. 1041, 197:21–199:10. This further indicates that the
comparison to Barnes is inapposite. See Ex. 1042 ¶¶ 15 (“If Yanagawa’s
Si-gate transistor truly had about the same current in the subthreshold regime
as the ON state, i.e., a channel in both regimes, the device may not turn off
properly. Among other issues, if the device does not turn off properly, the
logic operation of the circuit would fail.”), 31.
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In sum, the full trial record indicates that a person of ordinary skill in
the art would understand Yanagawa’s Si-gate transistor to be a
“surface-channel-type MOSFET” (i.e., a MOSFET in which the channel
forms at the surface of the semiconductor substrate, rather than slightly
under the surface). The Si-gate transistor is an N-FET device with a shallow
boron channel implant (i.e., a p-type dopant, the same as the p-type
substrate). There is no doping of the same type as the source and drain
regions that would normally indicate a buried-channel transistor, nor is there
any other structure disclosed that would bury the channel. Thus, when the
Si-gate transistor is ON, a channel forms at the surface of the semiconductor
substrate. Petitioner has shown sufficiently that Yanagawa discloses a
“first-surface-channel-type MOSFET,” as recited in claim 1. All other
limitations of claim 1 are undisputed.

c) Conclusion
For the reasons set forth by Petitioner and explained above, we are
persuaded that Yanagawa discloses all of the limitations of claim 1.
Petitioner has proven, by a preponderance of the evidence, that claim 1 is
anticipated by Yanagawa under 35 U.S.C. § 102(b).

3. Claims 2 and 4
Claim 2 depends from claim 1 and recites that “a dopant concentration
in the channel region of the second-surface-channel-type MOSFET is lower
than a dopant concentration in the channel region of the first-surface-
channel-type MOSFET.” Petitioner argues that in Yanagawa, the alleged
“second-surface-channel-type MOSFET” (i.e., Mo-gate transistor) has no
channel dopant, whereas the alleged “first-surface-channel-type MOSFET”
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(i.e., Si-gate transistor) has a channel dopant concentration of 5.9 x 1011/cm2,
as shown in Table I above. See Pet. 42–43; Ex. 1004, 3.
Claim 4 depends from claim 1 and recites that “the first-surface-
channel-type MOSFET is formed in a logic circuit block of the
semiconductor substrate,” “the second-surface-channel-type MOSFET is
formed in a memory cell block of the semiconductor substrate,” and “the
second gate insulating film is thicker than the first gate insulating film.”
Petitioner argues that in Yanagawa, the alleged “first-surface-channel-type
MOSFET” (i.e., Si-gate transistor) is formed in “the peripheral logic portion
of the chip,” the alleged “second-surface-channel-type MOSFET” (i.e.,
Mo-gate transistor) is an “access transistor[] in the memory array,” and the
alleged “second gate insulating film” (for the MO-gate transistor) has a
thickness of 40 nm, which is more than the alleged “first gate insulating
film” (for the Si-gate transistor), which has a thickness of 30 nm, as shown
in Table I above. See Pet. 43–46; Ex. 1004, 1–4.
Patent Owner does not argue separately dependent claims 2 and 4.
See PO Resp. 16–55; Sur-Reply 1–23. We disagree with Patent Owner’s
arguments regarding parent claim 1 for the reasons explained above.
See supra Section II.D.2. We have reviewed Petitioner’s contentions and
supporting evidence, including the testimony of Dr. Bravman, and are
persuaded that Petitioner has proven, by a preponderance of the evidence,
that claims 2 and 4 are anticipated by Yanagawa under 35 U.S.C. § 102(b),
for the reasons stated by Petitioner. See Pet. 42–46; Ex. 1003 ¶¶ 107–113.

E. Obviousness Ground Based on Yanagawa (Claims 1, 2, and 4)
Petitioner argues, in the alternative to its anticipation ground, that
claims 1, 2, and 4 would have been obvious over Yanagawa under 35 U.S.C.
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§ 103(a). Pet. 53–58. The only difference between Petitioner’s obviousness
ground and its anticipation ground based on Yanagawa is with respect to the
claim 1 limitation of a “first gate electrode . . . formed out of a poly-silicon
film formed directly on the first gate insulating film.” Id. at 53. Petitioner
argues that “[t]o the extent there is any doubt that Yanagawa” discloses the
limitation, it would have been obvious based on the knowledge of a person
of ordinary skill in the art. Id. For example, Petitioner explains that
Yanagawa’s alleged “first-surface-channel-type MOSFET” (i.e., Si-gate
transistor) has a poly-silicon gate and is a MOSFET with “a gate that sits on
the oxide layer, which sits on top of the substrate—hence metal
(gate)-oxide-semiconductor.” Id. at 54–55. According to Petitioner, a
person of ordinary skill in the art would understand that Yanagawa’s “first
gate electrode (Si-gate) sits directly on top of the first insulating film,”
which was the “convention[al] approach.” Id. at 55–56. Also, “because
Yanagawa does not describe any layer between the gate oxide and gate
electrode, it would have been obvious that the gate electrode sits directly on
the gate oxide.” Id. at 57.
Patent Owner does not dispute that Yanagawa teaches a “first gate
electrode . . . formed out of a poly-silicon film formed directly on the first
gate insulating film.” We disagree with Patent Owner’s other arguments
regarding claim 1 for the reasons explained above, and find that Yanagawa
teaches all limitations of claims 1, 2, and 4. See supra Section II.D.
Accordingly, we need not address Petitioner’s alternative obviousness
arguments regarding the “first gate electrode” of claim 1, and conclude that
the claims also would have been obvious based on Yanagawa. See Realtime
Data, LLC v. Iancu, 912 F.3d 1368, 1373 (Fed. Cir. 2019) (“[I]t is well
settled that a disclosure that anticipates under § 102 also renders the claim
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invalid under § 103, for anticipation is the epitome of obviousness.”
(citations and internal quotation marks omitted)).

F. Obviousness Ground Based on Yanagawa and An (Claim 3)
Claim 3 depends from claim 1 and recites that “the first-surface-
channel-type MOSFET is formed in a logic circuit block of the
semiconductor substrate” and “the second-surface-channel-type MOSFET
controls power to be supplied to the logic circuit block.” Petitioner argues
that claim 3 would have been obvious based on Yanagawa and An, relying
on its earlier arguments regarding anticipation and obviousness of parent
claim 1. See Pet. 47–53, 58–59; CRFD Research, Inc. v. Matal, 876 F.3d
1330, 1345–46 (Fed. Cir. 2017) (agreeing with the petitioner that it
“incorporated [an] argument into other grounds of unpatentability . . . by
direct citation to [the] argument in the petition”).
Petitioner argues that Yanagawa’s Si-gate transistors are formed in a
logic circuit block (i.e., a peripheral region including row and column
decoders), and it would have been obvious in view of An to “employ
Yanagawa’s Mo-based transistors . . . for its I/O circuitry that receives the
external power supply, given that Yanagawa’s second type transistors use a
thicker gate oxide” than the Si-gate transistors. Id. at 47–49. Petitioner
provides multiple reasons why a person of ordinary skill in the art would
have combined the references’ teachings in that manner, including, for
example, that it was “well-known that the I/O interface must be designed to
withstand high voltages associated with electrostatic discharge (ESD)” and
An expressly teaches the use of “transistors with a thicker gate oxide relative
to other transistors in the device for the I/O circuitry” to do so. Id. at 28,
49–54 (citing Ex. 1007, col. 1, ll. 34–46).
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Patent Owner does not argue separately dependent claim 3.
See PO Resp. 16–55; Sur-Reply 1–23. We disagree with Patent Owner’s
arguments regarding parent claim 1 for the reasons explained above.
See supra Section II.D.2. We have reviewed Petitioner’s contentions and
supporting evidence, including the testimony of Dr. Bravman, and find it
persuasive. See Pet. 47–53; Ex. 1003 ¶¶ 114–130. For the reasons set forth
by Petitioner, we are persuaded that Yanagawa and An collectively teach all
of the limitations of claim 3. We also are persuaded that a person of
ordinary skill in the art would have been motivated to use Yanagawa’s
Mo-gate transistor (based on the teachings of An) to control power to a logic
circuit block, achieving the semiconductor device recited in the claim, and
would have had a reasonable expectation of success in doing so. Petitioner
has proven, by a preponderance of the evidence, that claim 3 would have
been obvious based on Yanagawa and An under 35 U.S.C. § 103(a).

G. Obviousness Grounds Based on Houston (Claims 1, 2, and 4),
and Houston and An (Claim 3)
Petitioner contends that claims 1, 2, and 4 are unpatentable over
Houston, and claim 3 is unpatentable over Houston and An, under 35 U.S.C.
§ 103(a). Pet. 59–81. Petitioner’s analysis of the Houston-based asserted
grounds is similar to its analysis for the Yanagawa-based grounds. Compare
id. at 29–59, with id. at 59–81. As explained above, we conclude that
claims 1–4 are unpatentable under the Yanagawa-based grounds. See supra
Sections II.D–F. As such, we need not address Petitioner’s alternative
Houston-based grounds. See Boston Sci. Scimed, Inc. v. Cook Grp. Inc.,
809 F. App’x 984, 990 (Fed. Cir. 2020) (non-precedential) (recognizing that
“the Board need not address issues that are not necessary to the resolution of
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54
the proceeding” and, thus, agreeing that the Board has “discretion to decline
to decide additional instituted grounds once the petitioner has prevailed on
all its challenged claims”).

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III. CONCLUSION19
Petitioner has demonstrated, by a preponderance of the evidence, that
claims 1–4 of the ’047 patent are unpatentable. In summary:

19 Should Patent Owner wish to pursue amendment of the challenged claims
in a reissue or reexamination proceeding subsequent to the issuance of this
Decision, we draw Patent Owner’s attention to the April 2019 Notice
Regarding Options for Amendments by Patent Owner Through Reissue or
Reexamination During a Pending AIA Trial Proceeding. See 84 Fed. Reg.
16,654 (Apr. 22, 2019). If Patent Owner chooses to file a reissue application
or a request for reexamination of the challenged patent, we remind Patent
Owner of its continuing obligation to notify the Board of any such related
matters in updated mandatory notices. See 37 C.F.R. §§ 42.8(a)(3),
42.8(b)(2).
20 As explained above, given our disposition of the grounds based on
Yanagawa, we do not reach Petitioner’s alternative ground based on
Houston. See supra Section II.G.
21 As explained above, given our disposition of the ground based on
Yanagawa and An, we do not reach Petitioner’s alternative ground based on
Houston and An. See supra Section II.G.
Claims

35 U.S.C. § References/
Basis
Claims
Shown
Unpatentable

Claims
Not Shown
Unpatentable
1, 2, 4 102(b) Yanagawa 1, 2, 4
1, 2, 4 103(a) Yanagawa 1, 2, 4
3 103(a) Yanagawa, An 3
1, 2, 4 103(a) Houston20
3 103(a) Houston, An21
Overall
Outcome
1–4
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IV. ORDER
In consideration of the foregoing, it is hereby:
ORDERED that claims 1–4 of the ’047 patent have been shown to be
unpatentable.
This is a final decision. Parties to the proceeding seeking judicial
review of the decision must comply with the notice and service requirements
of 37 C.F.R. § 90.2.

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FOR PETITIONER:
Jeremy Jason Lang
K. Patrick Herman
ORRICK, HERRINGTON & SUTCLIFFE LLP
ptabdocketjjl2@orrick.com
p52ptabdocket@orrick.com

FOR PATENT OWNER:
Gerald B. Hrycyszyn
Marc S. Johannes
Richard F. Giunta
Elisabeth Hunt
Gregory S. Nieberg
Robert A. Jensen
WOLF GREENFIELD & SACKS, P.C.
ghrycyszyn-ptab@wolfgreenfield.com
mjohannes-ptab@wolfgreenfield.com
rgiunta-ptab@wolfgreenfield.com
ehunt-ptab@wolfgreenfield.com
gnieberg-ptab@wolfgreenfield.com
rjensen-ptab@wolfgreenfield.com