GILBERT HYATT

Patent Trials and Appeals Board

Aug 20, 2021

2020005348 (P.T.A.B. Aug. 20, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
08/285,669 08/03/1994 GILBERT P. HYATT 352 6133
142679 7590 08/20/2021
Hoffman Patent Firm/Hyatt
7689 East Paradise Lane, Suite 2
Scottsdale, AZ 85260
EXAMINER
TRYDER, GREGORY J
ART UNIT PAPER NUMBER
2615
NOTIFICATION DATE DELIVERY MODE
08/20/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
donald@valuablepatents.com
hyatt@valuablepatents.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GILBERT P. HYATT
Appeal 2020-005348
Application 08/285,669
Technology Center 2600
Before JAMES T. MOORE, DENISE M. POTHIER, and
JENNIFER S. BISK, Administrative Patent Judges.
POTHIER, Administrative Patent Judge.
DECISION ON APPEAL

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STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1,2 appeals from the
Examiner’s decision to reject claims 95–103, 105, 108–111, 113, 114,
118–126, 129–134, 136–151, 153–175, 178, 179, 181, 183, 186–189, 192,
193, 196–221, 223, 226–230, 234–245, 247, 249, 251, 252, 255–273, 275,
277–286, 288, 291, 295–352, 361–363, 365–368, 370, 372–399, 402–405,
408–411, and 414–448 (“the pending claims”). Appeal Br., App. L1–176;
see also Ans. 16 (indicating “[C]laims Appendix L is correct for the
purposes of this appeal”).3 The remaining claims have been canceled.
Appeal Br., App. L1–176.
We have jurisdiction under 35 U.S.C. § 6(b). Oral hearing was
scheduled for October 8, 2020. September 1, 2020 Notice of Hearing
(“Notice”) 1. Appellant waived the hearing. September 3, 2020 Appellant
Response to Notice of Hearing 1.

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as Gilbert P. Hyatt.
Appeal Br. 1.
2 Throughout this opinion, we refer to the Final Action (“Final Act.”) mailed
April 17, 2018, the Advisory Actions mailed April 24, 2019 (“First
Advisory”) and July 15, 2020 (“Second Advisory”), the Appeal Brief
(Appeal Br.) filed March 22, 2019, the Examiner’s Answer (“Ans.”) mailed
January 2, 2020, the Reply Brief (“Reply Br.”) filed July 8, 2020, and the
Specification submitted August 3, 1994.
3 The Amendment to the claims after the Final Office Action submitted
March 18, 2019 was entered. First Advisory 1 (boxes 3–4). Appellant
indicates the claims that existed after the Amendment filed March 18, 2019
are found in Appendix L. See Appeal Br. 125. Appellant submitted yet
another amendment to the claims after the Final Office Action on July 2,
2020, which was not entered. See Second Advisory 1 (box 4) (stating “See
attached”); see also Response to Amendment 2 (stating “[t]he claim
cancellations proposed . . . are not entered”).
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We have reviewed the Examiner’s rejection in light of Appellant’s
arguments presented in this appeal. Arguments which Appellant could have
made, but were not made in the Appeal Brief, will be refused consideration.
See 37 C.F.R. § 41.37(c)(1)(iv) (stating “any arguments or authorities not
included in the appeal brief will be refused consideration by the Board for
purposes of the present appeal”).
We AFFIRM. Except to the extent indicated below, we adopt as our
own the findings and reasons set forth in the rejections from which the
appeal is taken and in the Examiner’s Answer.

BACKGROUND
The Office issued requirements on October 23, 2013 in this
application (“the Requirement”), including requiring Applicant to select a
reasonable number of claims for examination in this application. See
Requirement 2 (first),4 4 (first), 35; see also Appeal Br. 2 (indicating that the
claim selection was made “under protest”).5 At present, Appellant has
selected claims 95, 101, 109, 113, 118, 121, 125, 130, 136, 139, 141, 145,
151, 153, 157, 163, 167, 171, 174, 181, 187, 188, 193, 198, 203, 208, 209,
213, 217, 226, 230, 235, 240, 241, 247, 251, 256, 260, 266, 269, 275, 284,
288, 291, 296, 316, 328, 330, 336, 340, 365, 388, 399, and 421 (“the

4 The Requirement’s first three pages are unnumbered. We refer to these
pages of the Requirement as pages 2 (first), 3 (first), and 4 (first). We refer
to second occurrence of pages 2–4 as pages 2–4 (second) respectively.
5 Appellant challenged the Office’s authority to issue the Requirement. The
Federal Circuit found “[i]n light of the nature of Mr. Hyatt’s applications,
longstanding PTO rules justify the issuance of the Requirements.” Hyatt v.
USPTO, 797 F.3d 1374, 1384 (Fed. Cir. 2015).
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selected claims”). See Ans. 16 (noting “a total of 54 claims”). The non-
selected claims remain pending in the case, but were not fully considered by
the Examiner, as indicated in the Requirement. See Requirement 37. As
such, our discussion is limited to the selected claims, except for those
rejections applied across all pending claims.
The following rejections have been appealed6:
(1) The selected claims are rejected provisionally on the grounds of
nonstatutory obviousness-type double patenting as unpatentable over claim
215 of U.S. Application No. 08/470,879 (“the ’879 application”) in view of
Levine (U.S. Patent No. 3,958,210, patented May 18, 1976) and Rawlings
(U.S. Patent No. 4,156,907, patented May 29, 1979). Final Act. 15–19.
(2) The selected claims are rejected under 35 U.S.C. § 112, first
paragraph,7 as failing to comply with the written description requirement.
Final Act. 19–23.
(3) The pending claims are rejected under 35 U.S.C. § 112, second
paragraph, as being indefinite (undue multiplicity). Final Act. 23–104.

6 The Examiner has stated the rejections based on the following statutes have
been withdrawn: (1) 35 U.S.C. § 112, second paragraph for claims 130, 157,
171, 181, 188, 208, and 231 (Final Act. 104) and (2) 35 U.S.C. § 101 for the
selected claims (Final Act. 105). Ans. 10. However, the Examiner indicates
the rejection based on 35 U.S.C. § 112, second paragraph for claims 130,
157, 171, 181, 188, 208, and 231 (as well as the remaining pending claims)
beginning on page 23 of the Final Office Action (undue multiplicity) is
maintained. Id.
7 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
(2011) (“AIA”), amended 35 U.S.C. §§ 112 and 103. Changes to §§ 112
and 103 apply to applications filed on or after September 16, 2012 and
March 16, 2013 respectively. Because this application has an effective filing
date before these dates, we refer to the pre-AIA versions of §§ 112 and 103
in this decision.
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(4) Claims 95, 101, 109, 113, 118, 121, 125, 136, 139, 141, 145, 151,
153, 163, 167, 174, 187, 193, 198, 203, 209, 213, 217, 226, 230, 235, 240,
241, 247, 251, 256, 260, 266, 269, 275, 284, 288, 291, 296, 316, 328, 336,
340, 365, 388, 399, and 4218 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Levine, Morley (U.S. Patent No. 4,162,536, patented July
24, 1979), and Gilbert (U.S. Patent No. 3,753,234, patented Aug. 14, 1973).
Final Act. 108–257.
(5) Claims 130, 157, 171, 181, 188, and 208 are rejected under 35
U.S.C. § 103(a) as being unpatentable over Levine, Morley, Gilbert, and
Lester (U.S. Patent No. 4,129,125, patented Dec. 12, 1978). Final Act. 257–
284.
(6) Claim 330 is rejected under 35 U.S.C. § 103(a) as being
unpatentable over Levine, Morley, Gilbert, Ewanus (U.S. Patent No.
4,185,241, patented Jan. 22, 1980), and Berg (U.S. Patent No. 3,824,597,
patented July 16, 1974). Final Act. 285–287.
(7) The pending claims are rejected on the grounds of prosecution
laches. Final Act. 287–341.
CLAIMED SUBJECT MATTER
According to Appellant, “[t]he present invention is related to
electronic memories such as may be used for data processors and signal
processors.” Spec. 5:2–3. Appellant summarizes his invention’s objective
to include “provid[ing] a low-cost electronic memory” and “improved signal
processing arrangements.” Id. at 9:10–11, 9:27.

8 Some of the claims listed in the rejection have been canceled by the
amendment entered by the Examiner. See First Advisory 1 (box 4). We
omit the canceled claims here and in other rejections.
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According to Appellant, there are 131 independent claims and a total
of 297 claims in this application. Appeal Br. 2. Each claim in this
application has its own combination of various elements. Claim 95
generally illustrates the subject matter found in the selected claims.
95. A process comprising the acts of:
storing analog information in charge storage elements
included in an integrated circuit charge storage memory, the
analog information stored in the charge storage elements
including at least some computer instructions;
generating digital information including at least some
computer instructions with a converter based at least in part on
analog information stored in the charge storage elements;
storing information in a scratch pad memory, the scratch
pad memory implemented as part of an integrated circuit stored
program computer;
storing information in an integrated circuit random access
memory, the integrated circuit random access memory
implemented as part of the integrated circuit stored program
computer;
loading computer instructions into the integrated circuit
random access memory with a direct memory access circuit
based at least in part on computer instructions generated with
the converter, the integrated circuit random access memory
storing computer instructions loaded therein with the direct
memory access circuit, the direct memory access circuit
implemented as part of the integrated circuit stored program
computer;
generating processed information with a data processor
based at least in part on information stored in the scratch pad
memory and based at least in part on computer instructions
stored in the integrated circuit random access memory, the data
processor implemented as part of the integrated circuit stored
program computer; and
generating computer output information with a computer
output circuit based at least in part on computer instructions
stored in the integrated circuit random access memory, the
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computer output circuit implemented as part of the integrated
circuit stored program computer.

Appeal Br., App. L1 (emphases added).

I. THE DOUBLE PATENTING REJECTION
The selected claims are rejected provisionally on the grounds of
nonstatutory obviousness-type double patenting as unpatentable over
reference claim 215 of the ’879 application in view of Levine and Rawlings.
Final Act. 15–19; see also Ans. 101–102 (comparing claim 95 with
reference claim 215 of the ’879 application). In the Answer, the Examiner
acknowledges that claim 95 and reference claim 215 “are not identical.
However, the claim limitations significantly overlap in scope such that
broadly claimed limitations from the instant application are disclosed by the
more specific claim limitations of the ’879 application, and elements missing
from the limitations of the ’879 application are disclosed in relevant prior
art.” Ans. 103.
Appellant first argues that the Examiner fails to follow the guidelines
set forth in the Manual of Patent Examining Procedure (MPEP)
§ 804(II)(B)(2) and thus fails to establish a prima facie case of double
patenting. Appeal Br. 75–76; see also Reply Br. 19–20. This dispute is a
petitionable matter and is not within the jurisdiction of the Board and will
not be addressed. See MPEP §§ 1002 and 1201, 9th ed., Rev. 10.2019 (June
2020); see also In re Hengehold, 440 F.2d 1395, 1403 (CCPA 1971) (stating
that there are many kinds of decisions made by examiners, “which have not
been and are not now appealable to the board or to this court when they are
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not directly connected with the merits of issues involving rejections of
claims, but traditionally have been settled by petition to the Commissioner”).
Appellant next argues that the comparison chart in the Final Office
Action has problems and that the double patenting rejection should be
reversed. Appeal Br. 76. First, Appellant asserts pending claims and
reference claim 215 differ as evidenced by the blanks in the chart and the
differences provide evidence of nonobviousness. Id. at 76–77 (citing Appeal
Br., App. D). Second, Appellant argues reference claim 215 has limitations
that, although having a similar appearance, differ from the pending claims.
As an example and without discussing pending or reference claims,
Appellant states “charge storage elements included in an integrated circuit
charge storage memory” is not “a monolithic integrated circuit read only
memory.” Id. at 76. Third, Appellant contends that Levine and Rawlings
“do not cure the deficiencies.” Id. at 77 (referring to “the rebuttal to the ’103
prior art rejections”); see also id. at 77–79, 94–95 (discussing Levine).
We are not persuaded. When discussing the double patenting
rejection in the Appeal Brief, Appellant addresses the selected claims
collectively (see Appeal Br. 75 (discussing “the selected claims”
collectively)) and claim 95 in particular (see id. at 77–78 (addressing claim
95)). We select claim 95 as representative. See 37 C.F.R. § 41.37(c)(1)(iv).
The charts produced in the Final Office Action (Final Act. 15–18) and
the Answer (Ans. 101–102) demonstrate that various limitations in claim 95
are disclosed in reference claim 215 of the ’879 application, and the blanks
are intended to indicate limitations of claim 95 that are not found in
reference claim 215 of the ’879 application. See Final Act. 18 (indicating
limitations in claim 95 that reference claim 215 fails to teach). As proposed,
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those identified, missing limitations are taught or suggested by Levine (e.g.,
storing analog information in charge storage elements and generating digital
information with a converter based on the analog information) and Rawlings
(e.g., storing information in a scratch pad memory) when combined with
reference claim 215 of the ’879 application. Final Act. 18–19 (citing Levine
4:27–29; Rawlings 18:26–31, 22:40–45); see also Ans. 103 (citing Final
Act. 18–19) (discussing Levine teaches, the recitations “storing analog
information in charge storage elements included in an integrated circuit
charge storage memory, the analog information stored in the charge storage
elements including at least some computer instructions” and “generating
digital information including at least some computer instructions with a
converter based at least in part on analog information stored in the charge
storage elements” and Rawlings teaches the “limitations directed towards a
‘scratch pad memory’” when combined with reference claim 215).
Additionally, we disagree that Levine and Rawlings fail to teach the
identified, missing limitations as asserted. Concerning Appellant’s
argument, Appellant refers to “the rebuttal to the ’103 prior art rejections.”
Appeal Br. 77. But, Appellant does not dispute the teaching in Rawlings in
its rebuttal to the obviousness rejections. See id. at 93–110. We thus are not
persuaded of error concerning Rawlings’s teachings. See also Rawlings
18:26–30, 22:40–45 (discussing a processor (e.g., 20) that “is an elementary
store-to-program computer” that obtains program instructions and contains a
scratch pad memory (e.g., 24sp)).
As for the arguments related to Levine (see Appeal Br. 94–95; Reply
Br. 22), the rejection does not rely on Levine to teach the entire recitation of
“storing analog information in charge storage elements included in an
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integrated circuit charge storage memory, the analog information stored in
the charge storage elements including at least some computer instructions”
in claim 95 but rather relies on reference claim 215 for some its features.
Final Act. 16 (mapping reference claim 215’s “storing computer instructions
in a monolithic integrated circuit read only memory, the monolithic
integrated circuit read only memory implemented in a monolithic circuit
computer” to claim 95’s “storing . . . information in charge storage elements
included in an integrated circuit charge storage memory, the . . . information
stored in the charge storage elements including at least some computer
instructions”) (emphases added); see also Ans. 101 (same); see also id. at
103 (indicating “storing ‘information’ (computer operands are inherently
‘information’)”).
And as for Levine, Appellant argues that storing “computer
instructions in the Levine memory would not be appropriate.” Appeal Br.
95. Yet, as noted above, reference claim 215 teaches storing computer
instructions in memory and Levine is not being relied upon to teach this
feature in claim 95. Levine, when combined with reference claim 215,
reasonably teaches or suggests the recited “generating digital information
including at least some computer instructions with a converter based at least
in part on analog information stored in the charge storage elements” found in
claim 95. See Levine 4:27–29, cited in Final Act. 18.
We also are not persuaded by Appellant’s contention that reference
claim 215 has limitations that, although having a similar appearance, differ
from the pending claims. Appeal Br. 76. Notably, Appellant only discusses
the “charge storage elements included in an integrated circuit charge storage
memory” in claim 95 and argues that reference claim 215’s recitation to “a
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monolithic integrated circuit read only memory” does not teach the noted
limitation in claim 95. Id. As for any other alleged differences (see id. at
77–78), Appellant provides no further explanation related to the differences,
and this mere assertion is insufficient to demonstrate error.
Also, “a monolithic integrated circuit read only memory” in reference
claim 215 teaches or suggests the specifically disputed limitation of “charge
storage elements included in an integrated circuit charge storage memory” in
claim 95. Final Act. 16. Although not using the exact same words,
reference claim 215 teaches an “integrated circuit . . . storage memory” as
claim 95 recites. See In re Bond, 910 F.2d 831, 832 (Fed. Cir. 1990)
(indicating that identity of terminology is not required to teach claim
limitations). Furthermore, Appellant does not provide us with an ordinary
understanding of the phrase “charge storage elements.” See Appeal Br. 76.
As such, an ordinarily skilled artisan would have recognized at the time of
the invention, that storing information, including computer instructions, in
an integrated circuit memory as taught by reference claim 215 (see Final
Act. 16) at least suggests using a charge and charge elements and thus,
suggests using “charge storage elements” as claim 95 broadly recites that are
part of its integrated circuit storage memory. Also, in contrast with
Appellant’s assertion (Reply Br. 23), the term “monolithic” in front of the
recited “integrated circuit read only memory” in reference claim 215 does
not lessen its teaching or suggestion that the specifically recited “integrated
circuit read only memory” suggests “an integrated circuit charge storage
memory” recited in claim 95.
In the Reply Brief, Appellant argues that the Examiner only provides
a chart for selected claim 95, this claim is no longer selected, and thus, this
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rejection is moot. Reply Br. 19. Although the March 18, 2019 Amendment
was entered (First Advisory 1), we disagree with Appellant that claim 95 is
canceled because the amendment to cancel claim 95 submitted on July 2,
2020, has not been entered. Second Advisory 1 (box 4) (stating “See
attached”); see also Response to Amendment 2 (stating “[t]he claim
cancellations proposed . . . are not entered”).
Appellant further identifies alleged elements of claim 95 (e.g.,
“loading computer instructions into the integrated circuit random access
memory with a direct memory access circuit . . . the integrated circuit
random access memory storing computer instructions loaded therein with the
direct memory access circuit,” “the direct memory access circuit
implemented as part of the integrated circuit stored program computer,”
“generating processed information with a data processor,” “the data
processor implemented as part of the integrated circuit stored program
computer,” “generating computer output information with a computer output
circuit,” and “the computer output circuit implemented as part of the
integrated circuit stored program computer”) as absent from reference claim
215 and that the Examiner failed to address. Reply Br. 21 (citing Appeal Br.
77–78).
This argument is unavailing as the rejection maps the asserted
limitations to those in reference claim 215. See Final Act. 16–17 (mapping
the “loading computer instructions” step and “the direct memory access
circuit implemented as part of the integrated circuit stored program
computer” limitation to recitations in reference claim 215), 17 (mapping the
“generating processed information” step and “the data processor
implemented as part of the integrated circuit stored program computer” to a
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recitations in reference claim 215), 18 (mapping the “generating computer
output information with a computer output circuit” step and “the computer
output circuit implemented as part of the integrated circuit stored program
computer” limitation to recitations in reference claim 215); see also Ans.
101–02 (containing similar mappings). Also, as previously discussed,
Appellant fails to provide any further explanation why the Examiner’s
mapping to reference claim 215’s limitations is deficient.
As previously indicated, the Appeal Brief only addressed claim 95 in
particular when discussing the double patenting rejection. See Appeal Br.
75–79. For the first time in the Reply Brief, Appellant contends, as for the
claims other than claim 95, there is no articulated reasoning for the rejection,
and the rejection should be reversed. Reply Br. 19. Appellant further
contends a difference between the remaining selected claims “addresses . . .
at least three memories, namely an IC charge storage memory with analog
charge storage elements [and] a computer main memory (which is part of an
IC stored program computer and which stores computer instructions)” (id.),
and claim 215 fails to recite. Id. at 20. Appellant contends the rejection
should be reversed because it fails to perform “the Graham analysis.” Id. at
20–21. Appellant additionally asserts the rejection does not discuss “the
combination of Rawlings with the reference claim” (id. at 22) or provide “a
sufficiently ‘articulated reason’ for why a person having ordinary skill in the
art would” have combined Levine with reference claim 215 (id. at 23).
Appellant presents even further arguments. See id. at 23–24.
These arguments are untimely and will not be considered. See 37
C.F.R. § 41.41(b)(2) (stating “[a]ny argument raised in the reply brief which
was not raised in the appeal brief, or is not responsive to an argument raised
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in the examiner’s answer . . . will not be considered by the Board for
purposes of the present appeal, unless good cause is shown”).
Conclusion
Based on the current record, we are not persuaded the Examiner erred
in provisionally rejecting the selected claims on the grounds of nonstatutory
obviousness-type double patenting as unpatentable over reference claim 215
of the ’879 application in view of Levine, and Rawlings.

II. THE LACK OF WRITTEN DESCRIPTION REJECTION
The selected claims are rejected under 35 U.S.C. § 112, first
paragraph, as failing to comply with the written description requirement.
Final Act. 19–23; see also Ans. 104–106. The rejection stated “the
specification fails to disclose all of the recited elements related in a single
embodiment, let alone on a single integrated circuit, as claimed.” Final Act.
22–23. The rejection further stated:
the disclosure appears to fail to show interconnections,
interrelations and/or linkage of the components such that the
claimed invention would have been immediately discernible to
one skilled in the currently claimed embodiments. While the
specification appears to disclose certain functional aspects of
these limitations within scattered parts of the specification, the
actual combination of the elements is not disclosed in a
sufficient detail in order to demonstrate that the Applicant had
possession of the claimed invention at the time of filing.

Id. at 21. The rejection contended “that the written description fails to
provide any immediately discernible disclosure regarding these elements
independently or in combination with any other embodiment so as to
demonstrate possession of these limitations.” Id.
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Appellant disagrees. Appeal Br. 79–91.
LEGAL AUTHORITY
To satisfy the written description requirement, a patent specification
must describe the claimed invention in sufficient detail that one skilled in the
art can reasonably conclude that the inventor had possession of the claimed
invention. See Ariad Pharm., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1351
(Fed. Cir. 2010) (en banc).
Adequate written description means that, in the specification,
the applicant must “convey with reasonable clarity to those
skilled in the art that, as of the filing date sought, he or she was
in possession of the [claimed] invention.” When no such
description can be found in the specification, the only thing the
PTO can reasonably be expected to do is to point out its
nonexistence.

Hyatt v. Dudas, 492 F.3d 1365, 1370 (Fed. Cir. 2007) (alteration in original)
(citations omitted).
ANALYSIS
“[I]ntegrated circuit stored program computer” and “single
integrated circuit chip stored program computer”
The rejection stated the term “stored program computer” is found in
the disclosure but not “integrated circuit stored program computer” or
“single integrated circuit chip stored program computer” as the selected
claims recite. Final Act. 21–22; see also Ans. 106 (stating “no explicit
disclosure of a cohesive embodiment pertaining to an ‘integrated circuit
stored program computer’ and ‘single integrated circuit chip stored program
computer’ could be found”).
Appellant responds by asserting the Examiner fails to establish a
prima facie case of lack of written description support because the Examiner
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required verbatim support in the disclosure for the claim terms, including the
phrase “integrated circuit stored program computer.” Appeal Br. 80 (stating
“FOA incorrectly required verbatim support for the claim terminology all in
one string of words in the disclosure”); see also id. at 81 (stating
“complaints about lack of verbatim statements in the disclosure”). Appellant
also contends the Specification provides antecedent basis for the phrase
“integrated circuit” (see id. at 88 (stating that there are “more than 20
occurrences of this [‘integrated circuit’] term” in the Specification); see also
id. at 89–90 (citing Spec. 40:5–10, 92:11–21; U.S. Application No.
05/101,881, pp. 6:7–10, 10:13–19, 34:17–25)) and “single integrated circuit
chip” (id. at 90–91 (citing Spec. 184:7–9, 221M:1–6, 226:20–27; U.S.
Application No. 05/849,812, pp. 7:1–8, 21:1–8, 16:1–16)). See also Reply
Br. 33–37.
Appellant’s arguments are unavailing. Although we agree that the
Specification need not use the exact phrase “integrated circuit stored
program computer” or “single integrated circuit chip stored program
computer” recited in the selected claims, the Specification still needs to
convey with reasonable clarity to an ordinarily skilled artisan that Appellant
was in possession of these claimed terms. Turning to the portions of the
Specification cited by Appellant (see Appeal Br. 89–91), the Specification
describes a data processor can have “integrated circuit ROM and an
integrated circuit alterable memory.” Spec. 40:5–7. This, however, does not
convey that the ROM and/or the alterable memory are a “stored program
computer” (see id.), such that the Specification supports the phrase
“integrated circuit stored program computer” or “single integrated circuit
chip stored program computer.” Similarly, page 92 describes main memory
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130R “may be an integrated circuit read only memory” and scratchpad
memory 131R “may be integrated circuit RAMs” (Spec. 92:16–21) but this
does not convey that either the ROM or RAMs is a “stored program
computer.”
Other passages of the Specification cited in the Appeal Brief (Appeal
Br. 82) address a “stored program computer.” For example, the
Specification states the “stored program computer is disclosed in application
S/N 101,881.” Spec. 221D:11–12. However, Appellant has not sufficiently
demonstrated that Figure 1 of U.S. Application No. 05/101,881 (reproduced
in Appeal Br. 84) is the “stored program computer” or for that matter, an
“integrated circuit stored program computer” as the selected claims recite.
Moreover, even if Figure 1 of U.S. Application No. 05/101,881 is a “stored
program computer,” this figure does not demonstrate the “scratch pad
memory,” the “random access memory,” the “direct access circuit,” and the
“computer output circuit” are all implemented as part of the “integrated
circuit stored program computer” as claim 95 further recites (or the
identified variations as the selected claims recite).
For the first time in the Reply Brief, Appellant further cites other
portions of the disclosure for written description support and argues that
Figure 8 is the “integrated circuit stored program computer” recited in
claims 174, 235, and 399. Reply Br. 36; see id. at 35–37 (citing Spec.
17:19–23, 80:9–15, 92:25–31, 192, 224:24–26, Figs. 5A–B, 6 11N). Some
of these arguments are untimely and will not be considered. See 37 C.F.R.
§ 41.41(b)(2). In any event, Figure 8 and its accompanying description and
the newly cited passages from the Specification describe Figure 8 as “a
combination memory arrangement” (Spec. 92:3) and do not disclose a
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scratch pad memory, a random access memory, a direct memory access
circuit, a data processor, and a computer output circuit (or the noted
variations) are all “implemented as part of the integrated circuit stored
program computer” as these selected claims require.
And even assuming, without agreeing, the “disclosure shows an
integrated circuit stored program computer with ‘the computer main
memory,’ ‘the integrated circuit random access memory,’ and ‘the data
processor’ as part of it” as Appellant states (Reply Br. 36), this does not
demonstrate all the identified elements are part of the integrated circuit
stored program computer as recited in the selected claims as explained in
more detail below. Similarly, the Specification discusses generally “a
hybrid stored program computer” (Spec. 221G:13) or “a stored program
computer” (id. at 221H:27) with no more details.
To the extent computer 112R (id. at 92:11) is considered to be a
“stored program computer” found in the selected claims (see Reply Br. 35
(citing Spec. 80:9–15)), this passage only discusses computer 112R can be a
data processor arrangement (id. at 92:11–15) but does not convey to an
ordinarily skilled artisan that the computer/data processor is an “integrated
circuit stored program computer” as the selected claims recite and moreover,
that the “scratch pad memory,” the “random access memory,” the “direct
access circuit,” and the “computer output circuit” are all implemented as part
of the “integrated circuit stored program computer” as claim 95 recites (or as
the variations of the selected claims recite).
Additionally, the rejection indicates and we agree that, although the
Specification discloses elements individually, the disclosure does not
“disclose all of the recited elements . . . on a single integrated circuit, as
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claimed.” Final Act. 23; see id. at 22–23. For example, cited passages
support “multiple micro-processors can be put a [sic] on a single chip”
(Spec. 221M:2–3), but this does not convey with clarity to an ordinarily
skilled artisan that the noted memories, data processor, and circuits are all
part of the same “integrated circuit stored program computer” as recited,
such as in claim 95.
Even other cited passages discuss generally “circuits on the same
integrated circuit chip” (id. at 184:8–9) without clearly conveying to an
ordinarily skilled artisan that the specifically recited circuits (e.g., “direct
memory access circuit” and “the computer output circuit” recited in claim
95) and the specifically recited memories (e.g., those noted above) are all
implemented on the recited “integrated circuit stored program computer” as
recited in the selected claims. See Ans. 106 (stating “Appellant’s reply . . .
illustrate that various portions of a stored program computer ‘can be’ or
‘may be’ implemented as part of an integrated circuit, and fail to show all of
the elements of the claimed embodiment all disposed in a relevant citation
from the specification”).
As for quoted portions of U.S. Application Nos. 05/101,881 and
05/849,812 (Appeal Br. 89–91), the cited portions from other Specifications
of other applications provide no more support than that discussed above
(U.S. Application No. 05/101,881, pp. 6:7–10, 10:13–19, 34:17–25; U.S.
Application No. 05/849,812, pp. 7:1–8, 21:1–8, 16:1–16), which does not
convey sufficiently and clearly to an ordinarily skilled artisan possession of
the recited “integrated circuit stored program computer” in the selected
claims. See also Ans. 105 (stating “Appellant cites to three distinct
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specifications . . . ; and cites to distinct individual elements as opposed to
entire claimed embodiments”).
Lastly, the selected claims, such as claim 95, require “the scratch pad
memory,” “the integrated random access memory,” and “the data processor”
(as well as “the direct memory access circuit” and “the computer output
circuit”) are all “implemented as part of the integrated circuit stored program
computer” (Appeal Br., App. A1), which these passages do not convey to
those skilled in the art with reasonable clarity. We thus disagree with
Appellant that the rejection related to the recited “integrated circuit stored
program computer” (see Final Act. 22–23) “is not an interconnections
argument” (Reply Br. 27) as addressed below in more detail.
Interconnections of the recited memories, data processor, and circuits
The Examiner identified claim 95 as reciting a scratch pad memory,
random access memory, a direct memory access circuit, a data processor,
and a computer output circuit. Final Act. 22. As for other selected claims,
the Examiner additionally states that“[v]ariations on the claimed invention
include a ‘computer main memory’ and ‘load circuit’, often in place of the
‘random access memory’ and ‘direct memory access circuit’.” Id. The
rejection further stated “the disclosure appears to fail to show
interconnections, interrelations and/or linkage of the components such that
the claimed invention would have been immediately discernible to one
skilled in the currently claimed embodiments.” Id. at 21; see also id. at 22–
23 (citing Spec. 5, 7A, 14, 17, 40–42, 44–45, 47–49, 53, 60, 92–93, 166,
188–89, 200, 202–03, 206, 208, 221A–B, 221E–H, 224, 226, 232).
Appellant responds, arguing that he filed “an extensive compilation of
written description evidence in the Attachment 2 to the Reply dated
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February 9, 2018,” that the Examiner allegedly disregarded. Appeal Br. 81;
see also id. at 87 (referring to “Said Attachment 2 supra”); Reply Br. 25.
However, Attachment 2 is not part of the briefing. See Appeal Br. 125
(noting Appendices A–L, which do not include “Attachment 2”). Because
this evidence is not included in the Appeal Brief, we will not consider it.
See 37 C.F.R. § 41.37(c)(1)(iv).
In any event, Appellant provides no citation to the attachment in an
effort to demonstrate written description support for the claimed
interconnections in claim 95 (e.g., interconnections among the scratch pad
memory, random access memory, a direct memory access circuit, a data
processor, and a computer output circuit) and variations of the
interconnections (e.g., computer main memory and load circuit “in place of
the ‘random access memory’ and ‘direct memory access circuit” (Final Act.
22)) in the other selected claims. See Appeal Br. 81–87. In essence,
Appellant’s contentions regarding Attachment 29 amount to counsel’s
arguments that cannot take the place of factually supported objective
evidence. See In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997); see also
In re Pearson, 494 F.2d 1399, 1405 (CCPA 1974) (indicating attorney
argument is not evidence).
Appellant further contends there is no “authority for this ‘single
embodiment’ requirement to satisfy a written description requirement” but
that the Specification “provide[s] a clear ‘single embodiment.’” Appeal Br.

9 The Examiner states “the elements of selected claim 95 are generally found
within Attachment 2” but do not provide the requisite written description
support for the selected claims. Final Act. 4; see also id. at 4–5; Ans. 97
(discussing “Attachment 2” and Final Act. 4–5).
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81; see id. at 81–88 (citing Spec. 11:7–8, 92:1–21, 92–95, 221B–221I,
221M, Fig. 8 (reproduced at Appeal Br. 86); U.S. Application Nos.
05/101,881 (p. 1:27–29) and 05/849,812 (pp. 3:30–31, 4:10–17) (both
incorporated by reference); App. K; U.S. Application No. 05/101,881, Fig. 1
(reproduced at Appeal Br. 84); U.S. Application No. 05/849,812, Fig. 1A
(reproduced at Appeal Br. 85)).
Upon consideration, we disagree with Appellant that the Specification
describes an embodiment having the identified claimed elements and
variations interconnected as recited in claim 95 and the other selected
claims. Many of the passages cited by Appellant have been addressed
above. As for cited Figure 8 of the Specification (see id. at 86), this figure
includes computer 112R that is connected to scratch pad memory 131R and
RAM 803. Spec. 11:7–8, 92:4–6, 92:9, 92:19–21, 92:27–29, Fig. 8,
reproduced in both Appeal Br. 86 and Reply Br. 35. Also, as previously
discussed, computer 112R can be a data processor arrangement. Spec.
92:11–15.
Thus, Figure 8 reasonably conveys to an ordinarily skilled artisan a
system that includes using a scratch pad memory, random access memory,
and a data processor together. See Reply Br. 33 (quoting Spec. 92:1–10)
(noting scratch pad memory can be used in conjunction with a processor).
But, this figure does not convey with reasonable clarity to an ordinarily
skilled artisan an arrangement that further includes the claimed “direct
memory access circuit” and “a computer output circuit” as claim 95 recites
and as identified by the rejection.
Although not part of the instant disclosure, U.S. Application No.
05/101,881’s Figure 1 (reproduced in Appeal Br. 84) and U.S. Application
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No. 05/849,812’s Figure 1A (reproduced in Appeal Br. 85) may show some
form of an “output circuit” connected to a computer, but do not show to an
ordinarily skilled artisan an arrangement that further includes the claimed
“random access memory” and “direct memory access circuit” as identified
by the rejection. See Final Act. 22. Similarly, the cited passages in U.S.
Application Nos. 05/101,881 and 05/849,812 (Appeal Br. 89–91) provide
support that a processor and memories can be on a single integrated circuit
chip but do not provide reasonably clarity to support all the elements
implemented as part of an integrated circuit chip in claim 95 and in the other
selected claims identified as rejected.
For the first time in the Reply Brief, Appellant cites to yet other
portions of the disclosure for written description support. Reply Br. 35–36
(citing Spec. 60:6–18, 92:25–31). These arguments are untimely and will
not be considered. See 37 C.F.R. § 41.41(b)(2). In any event, the newly
cited passages do not reasonably convey to an ordinarily skilled artisan a
system that includes using a scratch pad memory, random access memory,
direct memory access circuit, a data processor, and a computer output circuit
together and implemented as part of the “integrated circuit stored program
computer” as claim 95 recites.
Thus, Appellant has not demonstrated sufficiently how the
Specification supports the particular combination of limitations identified by
the Examiner recited in the selected claims. See Novozymes A/S v. DuPont
Nutrition Biosciences APS, 723 F.3d 1336, 1349 (Fed. Cir. 2013)
(explaining that each claim must be taken “as an integrated whole rather
than as a collection of independent limitations”); see also Hyatt v. Dudas,
492 F.3d at 1371 (upholding examiner’s rejection when the examiner stated
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that “while each element may be individually described in the specification,
the deficiency was the lack of adequate description of their combination”);
see also Flash-Control, LLC v. Intel Corp., -- Fed. Appx. --, 2021 WL
2944592, *4 (Fed. Cir. July 14, 2021) (“A patent owner cannot show written
description support by picking and choosing claim elements from different
embodiments that are never linked together in the specification.”).
Conclusion
Upon consideration, we are not persuaded the Examiner erred in
determining that the Specification does not convey with reasonably clarity to
ordinarily skilled artisans that the inventor was in possession of the noted
interconnected combination of particular elements found in the selected
claims.

III. THE OBVIOUSNESS REJECTIONS
References
The prior art relied upon by the Examiner is:
Name Reference Date
Gilbert 3,753,234 Aug. 14, 1973
Berg 3,824,597 July 16, 1974
Levine 3,958,210 May 18, 1976
Lester 4,129,125 Dec. 12, 1978
Morley 4,162,536 July 24, 1979
Ewanus 4,185,241 Jan. 22, 1980

A. OBVIOUSNESS REJECTION OVER LEVINE, MORLEY,
AND GILBERT

Claims 95, 101, 109, 113, 118, 121, 125, 136, 139, 141, 145, 151,
153, 163, 167, 174, 187, 193, 198, 203, 209, 213, 217, 226, 230, 235, 240,
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241, 247, 251, 256, 260, 266, 269, 275, 284, 288, 291, 296, 316, 328, 336,
340, 365, 388, 399, and 421 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Levine, Morley, and Gilbert. Final Act. 108–257. We
address each claim below.
Claim 95
The Examiner relies on Levine to teach the steps of storing analog
information and generating digital information in claim 95 but does not
teach the digital information includes at least some computer instructions
and the remaining limitations in claim 95. Final Act. 108–10 (citing Levine
1:35–43, 4:27–40). The Examiner states Morley teaches a digital
input/output system and parallel process controller similar to Levine’s
storage and conversion system. Id. at 110. Specifically, the Examiner turns
to Morley, in combination with Levine, to teach the steps of storing
computer instructions, storing information in a scratch pad memory, storing
information in an integrated circuit random access memory (RAM), loading
computer instructions in the integrated circuit RAM, generating process
information, and generating computer output information in claim 95. Id. at
110–11 (citing Morley 3:3–11, 4:67–5:3, 5:22–27, 5:45–48, 15:11–18,
17:20–55, 54:8–9, 55:27–50, Figs. 24–25). However, Levine and Morley do
not teach the scratch pad memory, the integrated circuit RAM, the direct
memory access circuit, the data processor, and the computer output circuit
are all implemented as part of an integrated circuit stored program computer,
and thus, the rejection includes Gilbert’s teachings in this regard. Id. at 111–
12 (citing Gilbert 1:61–68, 8:44–60, Fig. 1a).
Appellant disputes that the prior art discloses all the recitations in
claim 95, which we address below.
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Storing analog information in charge storage elements and
generating digital information including at least some computer instructions
Appellant states Levine discloses charge storage memory that receives
analog information but argues that the reference “would not be appropriate”
for storing computer instructions (Appeal Br. 94) “because of the slow serial
transfer of data through the memory and the slow conversion from analog to
digital format” (id. at 94–95 (citing Levine 4:13–26, code (57))). Appellant
also argues the rejection omits the recitation “including at least some
computer instructions” in the “generating digital information” step and
contends that storing computer instruction in Levine’s memory would not be
appropriate for reasons similar to those discussed for the “storing analog
information” step. Id. at 95.
These arguments are not persuasive because the rejection turns to
Morley’s teachings related to storing computer instructions in memory in
combination with Levine. Final Act. 110–11; see also Ans. 108 (noting the
“argument ignores the inclusion of the Morley reference to disclose the
storage of computer instructions”). We address the arguments related to the
proposed combination of Levine and Morley more below.
Regarding Morley, Appellant argues that Morley’s “system has no
computer instructions, col. 12:10–13” (Appeal Br. 97–98) and “[t]he Morley
controller has no instructions, col. 12:10–12” (id. at 97). We are not
persuaded. As the Examiner notes (Ans. 111–12), Morley teaches in column
12 that its parallel process controller (PPC) has no instructions “in the mini-
computer sense” (Morley 12:12–13) but that it is “programmed by ‘Line,’
each of which is a stand-alone processing or storage element” (id. at 12:13–
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15). As such, Morley teaches or suggests “at least some computer
instructions” that are “stored in . . . storage elements” as claim 95 recites.
Storing information in a scratch pad memory, storing information in
an integrated circuit random access memory, loading computer instructions
into the integrated circuit random access memory, generating process
information with a data processor, and generating computer output
information with a computer output circuit
Appellant states Morley does not disclose the “storing information in
a scratch pad memory” and “storing information in an integrated circuit
random access memory” steps because the rejection “omit[s] the recitation
of implemented as part of a stored program computer.” Appeal Br. 98, 101.
Appellant similarly states Morley does not disclose the “loading computer
instructions” step because the rejection “omit[s] the recitation of based at
least in part on computer instructions stored in the (previously recited)
plurality of the charge storage elements as well as the recitation of
implemented as part of the (previously recited) integrated circuit stored
program computer.” Id. at 101. Similar arguments are made concerning the
“generating processed information” and “generating output information”
steps. Id. at 103, 105.
These arguments are unavailing because they fail to consider that the
rejection relies on Gilbert in combination with Levine and Morley to teach
the features in dispute. Final Act. 111–12; see also Ans. 113 (stating “the
Gilbert reference, not Morley, is relied upon to disclose implementing the
various elements as part of a stored program computer”); id. at 114.
Appellant further repeats the argument that Morley has “no
instructions” and does not load instructions into memory. Appeal Br. 102.
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We are not persuaded for the reasons discussed above when addressing
Morley and that the argument fails to consider the combined teachings of
Levine and Morley.
Appellant also contends Morley does not teach “a direct memory
access circuit.” Appeal Br. 102. We are not persuaded because, as the
Examiner explains (Ans. 115), Morley teaches a timing and control circuity
that allows data to be loaded into random access memory and “DM
memory” (Morley 55:23–50, Figs. 24–25), thus suggesting “loading
computer instructions” into RAM “with a direct memory access circuit” as
claim 95 recites.
Also, although discussed in the context of claims 213, 291, and 299
(Reply Br. 53), Appellant separately argues the “loading information into the
integrated circuit random access memory with a direct memory access
circuit” limitation, asserting that the Examiner’s construction of “direct
memory access circuit” is “faulty” and “both over-inclusive and under-
inclusive.” See id. at 54 (citing Ans. 115). Appellant also contends Morley
does not use the phrase “‘direct memory access circuit’ or any other similar
terms.” Id. But, identity of terminology between Morley and the claim
language is not required to teach the limitations in claims. See Bond, 910
F.2d at 832.
Regarding the Examiner’s construction being under-inclusive by
narrowing memory to RAM, we are not persuaded. The Examiner has not
narrowed the construction of the phrase “direct memory access circuit” but
rather has mapped Morley’s RAM to the separately recited “random access
memory” also found in claim 95 (see Final Act. 110) and has indicated claim
95 recites the computer instructions are loaded into the integrated circuit
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random access memory “with a direct memory access circuit” (see Ans.
115)). Regarding the Examiner’s construction being over-inclusive,
Appellant asserts the construction “ignores the word ‘direct’ . . ., regardless
of whether the circuit causes the storage directly or indirectly.” Reply Br.
54. Yet, Appellant has provided no evidence or support that the recited
“direct memory access circuit” is limited to Appellant’s purported
understanding and a plain understanding would include a circuit that
accesses parts of memory directly, which Morley’s teachings suggest as
previously explained.
Appellant, for the first time in the Reply Brief, provides a construction
of “DMA” to include “a circuit [that] sends and receives data directly to or
from the main memory while bypassing the CPU.” Id. at 54–55, App. M
(citing https://www.techopedia.com/definition/2767/direct-memory-access-
dma and https://techterms.com/definition/dma). Appellant contends
Morley’s discussion in column 55 does not support this construction. Id. at
55. These arguments are untimely. See 37 C.F.R. § 41.41(b)(2). Moreover,
one of the provided definition states “DMA” “is a method of transferring
data from the computer’s RAM to another part of the computer” (Reply Br.,
App. M) (emphases added), whereas claim 95 recites “loading computer
instructions into the integrated circuit random access memory with a direct
memory access circuit.” Appeal Br., App. L1 (emphases added). The
definition provided by Appellant also has a 2020 copyright and does not
demonstrate the understanding of the term “direct memory access circuit” at
the time of the invention. See Brookhill-Wilk 1, LLC. v. Intuitive Surgical,
Inc., 334 F.3d 1294, 1299 (Fed. Cir. 2003) (rejecting non-contemporaneous
dictionary definitions).
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Implemented as part of the integrated circuit stored program
Claim 95 recites that the scratch pad memory, the integrated circuit
random access memory, the direct memory access circuit, the data processor,
and the computer output circuit are implemented as part of the integrated
circuit stored program computer. Appeal Br., App. L1. The rejection relies
on Gilbert in combination with Levine and Morley to teach or suggest this
recitation. Final Act. 111–12.
Appellant argues that Gilbert does not teach this feature because
Gilbert explains that its scratch pad memory may contain integrated circuit
registers but this is not an integrated circuit stored program computer.
Appeal Br. 106 (citing Gilbert 8:44–60, Fig. 1a). We are not persuaded.
First, as noted by the Examiner (Ans. 116–17) and discussed above
under Section II, the phrase “integrated circuit stored program computer” is
not discussed or defined in the Specification.
Second, as broadly as it is recited in claim 95, we agree with the
Examiner that the phrase “implemented as part of an integrated circuit stored
program computer” in claim 95 should be “interpreted to include stored
program computers with integrated circuit elements.” Id. at 117. Indeed,
Appellant states “[w]here the claim language does not require a single IC,
the ‘part of’ language requires that the recited features be part of the
‘integrated circuit stored program computer,’ whether it is spread across
multiple IC chips or not.” Reply Br. 51. Based on this understanding,
Gilbert teaches and suggests stored program digital computer units that
execute programs (e.g., “computer instructions”) and output information
(e.g., “a computer output circuit”), the computer units having integrated
circuit memory (e.g., “random access memory” and/or “scratch pad
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memory”) and an arithmetic unit (e.g., “a data processor”). Gilbert 5:23–57,
8:34–60, code (57), Fig. 1. These teachings collectively suggest that
Gilbert’s stored program computer is an “integrated circuit stored program
computer” and various elements (e.g., “memory,” “a data processor,” and “a
computer output circuit”) are “implemented as part of the integrated circuit
stored program computer” as claim 95 recites.
Third, even assuming, without agreeing, that the phrase “integrated
circuit stored program computer” is limited to a single program computer,
Gilbert further teaches each program computer has memory (e.g., “random
access memory” and/or “scratch pad memory”), a control unit and
register/decoders communicating with memory (e.g., a direct memory access
circuit), arithmetic unit (e.g., “a data processor”), and I/O unit (e.g., “an
output circuit”) (see id. at 4:35–36, 8:34–9:53, Fig. 1a), further suggesting
that its various elements (e.g., “memory,” “direct memory access circuit,” “a
data processor,” and “a computer output circuit”) are all “implemented as
part of the integrated circuit stored program computer” as claim 95 recites.
In the Reply Brief, Appellant also contends “th[e] [above]
construction is not the broadest reasonable interpretation.” Reply Br. 52. In
particular, Appellant argues “the ‘stored program computer’ must be
implemented with ICs, not merely contain IC elements,” and “[a]n
integrated circuit memory, standing alone and separate from a non-IC-based
computer, is not an ‘integrated circuit stored program computer.’” Id. This
argument is unavailing because, as discussed under Section II, the
Specification at best supports that main memories are for or are part of
stored program computers and that memories can be integrated circuit
memories. See Spec. 5:24–26, 7A:5–6, 40:5–7 (discussing a data processor
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having an integrated circuit ROM or alterable memory), 92:16–21, 27–28
(discussing integrated circuit main memory, ROM, core memory, or
scratchpad memory). Thus, consistent with the Specification, Gilbert’s
teaching that the memory is an integrated circuit memory and that its
memory and the remaining recited elements are part of overall circuit
structure sufficiently teaches or suggests the recited “integrated circuit stored
program computer” that has various elements “implemented as part of the
integrated circuit stored program computer” as recited.
In the Reply Brief, Appellant further argues the Examiner’s discussion
on page 117 of the Examiner’s Answer “create[s] confusion” (Reply Br. 50)
and that the recited “integrated monolithic structure is still a single chip”
(id.). But, Appellant provides us with no evidence or citation that describes
the “integrated monolithic structure” as being “a single chip” as asserted.
See id. Also, claim 95 recites “an integrated circuit stored program
computer,” not an integrated monolithic structure. Thus, even assuming,
without agreeing, an integrated monolithic structure requires all its elements
to be located within a single chip, this discussion does not apply to the
recited “an integrated circuit stored program computer” in claim 95.
Appellant also argues the references are not similar and the rejection
does not propose how the references are to be combined. Appeal Br. 105–
06. This argument attacks the reasons (or the alleged lack thereof) to
combine the references and will be addressed below.
Motivation to Combine Morley and Gilbert with Levine
Appellant states Levine discloses charge storage memory that receives
analog information but argues that the reference “would not be appropriate”
for storing computer instructions (Appeal Br. 94; Reply Br. 46) “because of
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the slow serial transfer of data through the memory and the slow conversion
from analog to digital format.” Appeal Br. 94–95 (citing Levine 4:13–26,
code (57)); see also Reply Br. 43. Appellant further contends Levine and
Morley are not similar and the rejection does not propose how the references
are to be combine or the resulting structure of the combination. Appeal Br.
105–06 (citing Levine 1:35–38, 4:12–17, code (57); Morley 12:10–12), 108–
09 (further citing Morley 12:12–14); see also Reply Br. 43, 47, 49.
Specifically, Appellant argues that Levine discloses a slow, parallel analog
data charge storage memory with digital output and Morley discloses a
parallel process controller that has no computer instructions (Appeal Br.
105) and “is not a conventional stored program computer” (id. at 106).
We are not persuaded.
First, contrary to Appellant’s assertion (Reply Br. 44), the rejection
provides a reason with some rational underpinning to combine Morley with
Levine. Final Act. 111 (citing Morley 3:3–11) (explaining the combination
provides “the advantage of . . . a reliable special purpose machine equipped
with input/output capability”). Moreover, Morley discloses its machine “is
expandable to fit a desired control system” (Morley 3:6–7) and is “reliable”
in various control systems (id. at 3:19–11).
Second, the test for obviousness is not whether the references are
similar but rather “is what the combined teachings of the references would
have suggested to those having ordinary skill in the art.” In re Mouttet, 686
F.3d 1322, 1333 (Fed. Cir. 2012). Also, “[i]t is well-established that a
determination of obviousness based on teachings from multiple references
does not require an actual, physical substitution of elements.” Id. at 1332.
The rejection proposes to combine Morley’s teachings related to data
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processing with Levine’s memory system. Final Act. 111. “Under the
correct analysis, any need or problem known in the field of endeavor at the
time of invention and addressed by the patent can provide a reason for
combining the elements in the manner claimed.” KSR Int’l Co. v. Teleflex
Inc., 550 U.S. 398, 420 (2007). Thus, the resulting combination of Levine
and Morley suggests and predictably yields no more than an ordinarily
skilled artisan would have expected—a combination that provides a reliable,
special purpose machine equipped with input/output abilities and expandable
to fit various systems, such as Levine’s memory system. See id.
Third, although asserting Levine is slow to process and convert data
(see Appeal Br. 94–95, 108–09; see also Reply Br. 45–46), Appellant
provides insufficient evidence that Morley is unsuitable to be combined with
Levine. See Ans. 120–21. Despite Levine’s transfer rates (see Levine 4:12–
13, 17–18), Levine’s arrangement of analog to digital conversion “still takes
place at reasonably high speed.” Levine 4:25–26; see also Ans. 121
(quoting the same). Also, an obvious system “does not become patentable
simply because it has been described as somewhat inferior to some other
product for the same use.” In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994);
Mouttet, 686 F.3d at 1334 (stating “[t]his court has further explained that
just because better alternatives exist in the prior art does not mean that an
inferior combination is inapt for obviousness purposes”) (citing Gurley, 27
F.3d at 553).
Regarding Gilbert, Appellant further contends the rejection fails to
explain how the proposed combination with Gilbert teaches the “integrated
circuit stored program computer” as claim 95 recites. Appeal Br. 106. We
disagree for the above reasons. Additionally, contrary to Appellant’s
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assertion (Reply Br. 44), the rejection provides a reason with a rational
underpinning why an ordinarily skilled artisan would have combined
Gilbert’s teachings with Levine and Morley, including to calculate problems
with high accuracy. Final Act. 111–12 (citing Gilbert 1:61–68); see also
Reply Br. 47.
Appellant further contends Gilbert is a disparate system from Levine’s
and Morley’s, including that Gilbert is a multi-processor system, where each
processor is a store program processor. Appeal Br. 105–06 (citing Gilbert
8:44–60); see also Reply Br. 49. We are not persuaded by this purported
distinction for the above-explained reasons when addressing Gilbert. Also,
Appellant contends that Levine’s slow system is unsuitable for Gilbert.
Appeal Br. 109. But, as explained previously, Levine’s system still takes
place at reasonably high speed and even if an inferior combination, this
alone is insufficient to demonstrate nonobviousness.
Appellant even further argues that Morley’s control system is not a
conventional stored program computer, such that it would not have been
obvious to combine its system with Gilbert’s stored program computer
components. See Appeal Br. 106, 109; see also Reply Br. 47. This
argument is unavailing because the rejection relies on Gilbert’s discussion
—not Morley—to teach the recited “stored program computer” (Final Act.
110–12), such that combining Gilbert’s components with any stored
program computer in Morley do not form part of the rejection. See id. We
further adopt the Examiner’s explanation concerning combining Gilbert with
Levine and Morley. See Ans. 121.
Lastly, to the extent Appellant’s arguments related to the references’
dissimilarities contend Levine, Morley, and Gilbert are non-analogous art,
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both Levine and Morley address memory features used to process data in
parallel. See Levine 1:31–32, 4:20–26, Fig. 5; Morley, code (57); see also
Appeal Br. 105 (indicating Levine includes a “parallel analog data charge
storage memory”). Likewise, Gilbert addresses memory features used to
process data (Gilbert 8:34–9:53, 10:11–28, code (57) Figs. 1–1a) and also
Gilbert is reasonably pertinent to the problem of implementing various
memory, circuits, and a data processor as part of an integrated circuit stored
program computer as explained above.
In the Reply Brief, Appellant contends: (1) Levine’s arrangement is
unsuitable to use with RAM, (2) Levine’s computer cannot randomly access
data as in RAM but rather requires the computer to wait until data has
shifted through many stages, (3) Levine does not have a random access
output available in RAM, (4) Levine’s output in its alternative embodiment
is still serial and too slow to be used with digital processing, and (5) there is
no random access of data stored in Levine’s B register. Reply Br. 45–48.
Appellant also argues: (1) Gilbert does not disclose the recited “integrated
circuit stored program computer” in the claims (id. at 49) and (2) the
rejection does not articulate how Gilbert teaches the alleged “unfixable”
deficiencies of the Levine and Morley combination (id.). Appellant even
further contends the Examiner uses the Specification improperly to combine
the references. Id. at 47–48.
Many of these arguments are being raised for the first time in the
Reply Brief, and thus are untimely, and will not be considered. See 37
C.F.R. § 41.41(b)(2). As previously noted, obviousness does not require an
actual, physical substitution of elements. See Mouttet, 686 F.3d at 1332.
Notably, the combination proposes to combine Morley’s system with
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Levine, such that the system will have RAM and thus will have the ability to
access data randomly. See Final Act. 111.
Additionally, the Examiner has not relied upon the Specification
improperly in formulating the rejection. See Final Act. 108–112; see also
Reply Br. 47 (stating “the examiner is using appellant’s claims and
specification as a template to make the combination”). Rather, the
discussion in the Examiner’s Answer attempts to address that the
Specification fails to inform how the elements are combined to form the
recited “integrated circuit,” including the “integrated circuit stored program
computer” in claim 95, such that the teachings in Gilbert and “the well-
known MOS technology” described in the Specification that “provide a fully
monolithic memory system” encompass the broadest reasonable construction
of “integrated circuit stored program computer.” Ans. 121; see id. (stating
Morley’s elements are not precluded “elements from being disposed as
integrated circuit chip components, as in Gilbert”). We further refer above
for our response to any arguments presented in the original briefing.
Additionally, implementing analog-to-digital converters in data
processing systems was well-known at the time of the invention, as
evidenced by the Levine’s discussion of a CCD memory device and the
Specification itself. See Levine 1:4–5, 4:27–40; see also Spec. 45:15–16
(discussing “an A/D converter” discussed in “Patent No 4,016,540 or any
other known A/D converter”). Thus, given the record, we disagree that
Levine is too slow to be used with digital processing or a data processor that
handles digital data.

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Claim 101
Claim 101 has limitations similar to claim 95, except that the
“integrated circuit chip stored program computer” is “a single integrated
circuit chip stored program computer.” Appeal Br., App. L4. The rejection
presented is similar to that for claim 95. Final Act. 112–18. Thus, for those
limitations similar to claim 95 argued by Appellant, we are not persuaded for
reasons previously discussed.
Appellant also asserts Morley does not disclose “a single integrated
circuit chip stored program computer.” Appeal Br. 99; see also id. at 100,
104–05. This argument is not persuasive because the rejection relies on
Gilbert, in combination with Levine and Morley, to teach this limitation.
See Final Act. 114–15. Additionally, as explained above, Gilbert teaches
single stored program computer that contains the recited elements and thus,
under its broadest reasonable construction consistent with the Specification,
Gilbert, in combination with Levine and Morley, teach and suggest the
recited elements are “implemented as part of the single integrated circuit
chip stored program computer” as claim 101 recites.
Appellant also argues that Morley fails to teach loading instructions
into the computer main memory because it has no instructions. Appeal Br.
100. Appellant further argues Morley does not teach processing based on
the instructions stored in main memory because Morley’s controller has no
instructions. Appeal Br. 103–04. We are not persuaded for reasons
addressed above related to Morley’s teachings of using computer
instructions.

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Claim 118
Claim 118 has limitations similar to claims 95 and 101. Claim 118
further recites “second charge storage elements included in a second
integrated circuit charge storage memory,” “information stored in the second
charge storage elements including at least some computer instructions,” and
“generating processed information with a data processor . . . based at least in
part on computer instructions stored in the second charge storage elements”
(or similar recitations). See Appeal Br., App. L10. The rejection presented
for this claim is similar to that for claims 95 and 101. See, e.g., Final Act.
120–26. For those limitations similar to claims 95 and 101 argued by
Appellant, we are not persuaded for reasons previously discussed.
Appellant further argues that Levine does not disclose the recited
“storing second analog information in second charge storage elements,”
contending that Levine’s multiple storage electrodes are not what is recited.
Appeal Br. 96 (citing Levine 1:48–55). This argument is not availing.
Identity of terminology between Levine and the claim language is not
required to teach the limitations in claims. See Bond, 910 F.2d at 832.
Additionally, the rejection maps both “first” and “second charge storage
elements” as recited to Levine’s teachings. Final Act. 121 (citing Levine
1:35–43, 1:48–55). Also, Appellant’s assertion that multiple storage
electrodes cannot be charge storage elements is unsubstantiated, amounting
to counsel’s argument that cannot take the place of factually supported
objective evidence. See Geisler, 116 F.3d at 1470; see also Pearson, 494
F.2d at 1405.
Appellant further argues (1) the rejection fails to establish Levine’s
charge storage elements are included in an off-line integrated circuit charge
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storage memory (Appeal Br. 97) and (2) claim 118’s recitation of
“processing based at least in part on computer instructions stored in the
(previously recited) charge storage elements” (id. at 104) and “generating
computer output based at least in part on computer instructions stored in the
(previously recited) charge storage elements” is distinguishable from the
cited art because Morley’s controller has no instructions (id. at 105). We are
not persuaded because claim 118 does not recite an “off-line” integrated
circuit charge storage memory. Appeal Br., App. L10. Regarding the
arguments that Levine fails to teach charge storage elements and Morley
fails to teach a controller with instructions, we refer to our previous
discussion.
Claim 145
Claim 145 has limitations similar to claims 95, 101, and 118. See
Appeal Br., App. L26. The rejection presented for this claim is similar to
that for claims 95, 101, and 118. See Final Act. 137–39. For those
limitations similar to claim 95, 101, and 118 argued by Appellant, we are not
persuaded for reasons previously discussed.
Appellant also contends claim 145 “distinguishes the cited art by
reciting the first charge storage elements included in an off-line integrated
circuit charge storage memory.” Appeal Br. 95. Like claim 118, we are not
persuaded because claim 145 does not recite an “off-line” integrated circuit
charge storage memory.
Claim 198
Claim 198 has limitations similar to claims 95, 101, 118, and 145 and
adds further “the first integrated circuit charge storage memory implemented
as an alternate to a magnetic disk memory.” See Appeal Br., App. L56. The
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rejection presented for this claim is similar to that for claims 95, 101, 118,
and 145. See Final Act. 162–65. For those limitations similar to claim 95,
101, 118, and 145 argued by Appellant, we are not persuaded for reasons
previously discussed.
For claim 198, Appellant also argues that Levine fails to teach a
second integrated circuit charge storage memory, contending different
charge storage elements within a single memory fail to teach this feature.
Appeal Br. 97. But, Appellant has presented no persuasive argument or
corresponding evidence supporting the assertion that the mapped second
charge storage elements are within a single memory. See Appeal Br. 97.
The rejection states the first charge storage elements are used to store analog
signals in A register (Final Act. 163 (citing Levine 1:45–43)) and the second
charge storage elements include multiple storage electrodes in the A register
(id. (citing Levine 1:48–55)). See id., Fig. 1; see also Ans. 110. Levine
further states each set of electrodes (e.g., 14-1–14-3 and 16-1–16-3)
comprises a storage location. Levine 1:50–53. Thus, based on the
arguments, we are not persuaded.
Appellant also argues Levine fails to disclose the recited “charge
storage memory being implemented as an alternate to a magnetic disk
memory” in claim 198. Appeal Br. 95. The Examiner determines this
limitation carries no patentable weight. Ans. 108. We disagree with the
Examiner that this limitation carries no patentable weight. However,
because the breadth of the limitation “being implemented as an alternate to a
magnetic disk memory” includes that the charge storage memory is an
alternative to magnetic disk memory, the recitation does not exclude that the
charge storage memory is implemented as part of other memory, including
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those disclosed in Levine. See Final Act. 163 (citing Levine 1:35–43); see
also Ans. 109 (same).
The Remaining Claims
The remaining claims include recitations similar to claims 95, 101,
118, 145, and 198, and the rejection for the remaining claims are similar to
those for claims 95, 101, 118, 145, and 198 (see Final Act. 115–257).
Appellant presents the same or similar arguments to those discussed above.
See, e.g., Appeal Br. 93–109. We are not persuaded and refer above for
more details.
Conclusion
Based on the record, the Examiner did not err in rejecting claims 95,
101, 109, 113, 118, 121, 125, 136, 139, 141, 145, 151, 153, 163, 167, 174,
187, 193, 198, 203, 209, 213, 217, 226, 230, 235, 240, 241, 247, 251, 256,
260, 266, 269, 275, 284, 288, 291, 296, 316, 328, 336, 340, 365, 388, 399,
and 421 based on Levine, Morley, and Gilbert.

B. OBVIOUSNESS REJECTION OVER LEVINE, MORLEY, AND
GILBERT, AND LESTER

Claims 130, 157, 171, 181, 188, and 208 are rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Levine, Morley, Gilbert, and Lester.
Final Act. 257–84. The Examiner relies on Levine, Morley, and Gilbert in a
manner similar to that when addressing claim 95’s limitations. See, e.g., id.
at 257–60 (citing Levine 1:35–43, 1:48–55, 4:27–40; Morley 3:3–11, 4:67–
5:3, 5:22–27, 5:45–48, 15:11–18, 17:20–55, 54:8–9, 55:27–50, Figs. 24–25;
Gilbert 1:61–68, 8:44–60, Fig. 1a). The rejection further turns to Lester, in
combination with Levine, Morley, and Gilbert, to teach or suggest
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generating second digital information including at least some computer
instructions with a second converter based at least in part on second analog
information stored in the second charge storage elements. Id. at 260 (citing
Lester 2:28–34, Fig. 6).
For those arguments addressing claims 130, 157, 171, 181, 188, and
208 similar to those previously discussed, we are not persuaded and refer
above for more details.
Claim 130
Claim 130 has limitations similar to claims 95, 101, 118, 145, and
198. See Appeal Br., App. L16–17. The rejection presented for claim 130 is
similar to that for the previously discussed claims. See Final Act. 257–260.
Regarding claim 130, Appellant argues that Lester fails to teach
“generating second digital information including at least some computer
instructions based at least in part on second analog information stored in the
(previously recited) second charge storage elements” because Lester or any
other reference fails to disclose the second charge storage elements. Appeal
Br. 98. We are not persuaded. First, as explained above, Levine—not
Lester—teaches or suggests the recited second charge storage elements.
Second, Appellant’s argument attacks each reference individually, even
though the rejection relied on the combination of Levine, Morley, Gilbert,
and Lester to teach and suggest the disputed limitation. See Final Act. 258
(discussing Levine), 260 (citing Lester 2:28–34, Fig. 6).
Appellant further contends that Morley fails to teach generating
computer instructions with a converter because Morley’s controller has no
instructions. Appeal Br. 104. Appellant further argues that Morley fails to
teach “generating computer output based at least in part on computer
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instructions generated with the (previously recited) converter” because
Morley’s controller has no instructions and fails to demonstrate generating
computer instructions with the converter. Appeal Br. 105. We disagree for
reasons previously discussed. Additionally, for these disputed features, the
rejection relies on Morley and Lester (see Final Act. 258, 260), thus
attacking Morley alone does not demonstrate nonobviousness. See In re
Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
Motivation to Combine Lester with Levine, Morley, and Gilbert
For claim 130, Appellant presents similar arguments to those
discussed above related to the combination of Levine, Morley, and Gilbert
(Appeal Br. 108–09). Appellant presents no arguments related to combining
Lester with Levine, Morley, and Gilbert. See id. Therefore, for those
limitations similar to claims 95, 101, 118, 145, and 198 argued by Appellant,
we are not persuaded for reasons previously discussed.
Claim 171
Claim 171 has limitations similar to those discussed above and adds
that charge storage elements are “included in a main computer program
integrated circuit charge storage memory.” See Appeal Br., App. L43–44.
The rejection presented for this claim is similar to that for claims 95, 101,
118, 130, 145, and 198. See Final Act. 264–67. Thus, for those limitations
in claim 171 similar to claims 95, 101, 118, 130, 145, and 198 and argued by
Appellant, we are not persuaded for the reasons previously discussed.
Appellant further argues that the rejection fails to show that Levine
discloses the memory is a main computer program memory. Appeal Br. 97.
Appellant also argues the rejection fails to teach Levine discloses the
memory stores at least some computer instructions. Id.
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These assertions attack Levine individually, whereas the rejection
turns to Morley in combination with Levine to teach the computer
instruction features and Gilbert in combination with Levine and Morley to
teach “a main computer program integrated circuit charge storage memory”
as recited. See Final Act. 264–67. That is, the rejection finds that Levine
teaches the main memory for a computer, Morley teaches a known technique
to store computer instructions in a system in order to process data with
input/output capabilities in reliable manner and with expandability to fit
various systems as previously discussed. See id. at 264–66; see also Ans.
109–10. Additionally, as explained above, Gilbert teaches a known stored
program computer that has various elements (e.g., integrated circuit
memory, register/decoders, arithmetic unit, and control unit) to improve a
system’s accuracy. Final Act. 266–67; see also Ans. 110.
Claim 188
Claim 188 has limitations similar to those claims previously
discussed, including claim 198. See Appeal Br., App. L51–52. The
rejection presented for this claim is similar to that for claims 95, 101, 118,
130, 145, and 198. See Final Act. 271–74. Although this claim is separately
discussed (see Appeal Br. 95), the arguments are similar to those for claim
95. Thus, we are not persuaded for reasons previously discussed when
addressing claim 95 as well as those arguments previously addressed when
addressing claims 101, 118, 130, 145, and 198.
The Remaining Claims
The remaining claims rejected based on Levine, Morley, Gilbert, and
Lester include recitations similar to claims 95, 101, 118, 130, 145, and 198,
and the rejection for the remaining claims are similar to those for claims 95,
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101, 118, 130, 145, and 198. See Final Act. 260–84. Appellant presents the
same or similar arguments to those discussed above. We are not persuaded
and refer above for more details.
Conclusion
Based on the record, the Examiner did not err in rejecting claims 130,
157, 171, 181, 188, and 208 based on Levine, Morley, Gilbert, and Lester.

C. OBVIOUSNESS REJECTION OVER LEVINE, MORLEY,
GILBERT, EWANUS, AND BERG

Claim 330 depends from claim 235 and further recites, among other
things,
receiving input signature modulated information from a
microwave data link with a receiver;
. . .
generating signature demodulated information by
correlating by a correlator at least some of the second signature
information with input signature modulated information
received by the receiver;
generating at least some of the processed information
with the data processor based at least in part on signature
demodulated information generated by the correlator;
generating output signature modulated information by
signature modulation with a signature modulator based at least
in part on at least some of the processed information; and
transmitting signature modulated information onto a
microwave data link coupled to a computer center with a
transmitter based at least in part on at least some of the output
signature modulated information.

Appeal Br., App. L121–22.
Claim 330 is rejected under 35 U.S.C. § 103(a) as being unpatentable
over Levine, Morley, Gilbert, Ewanus, and Berg. Final Act. 285–87. The
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Examiner relies on Levine, Morley, and Gilbert in a manner similar to that
when addressing claim 95. Id. at 285 (referring to claim 235). The rejection
further turns to Ewanus, in combination with Levine, Morley, and Gilbert, to
teach or suggest many of the above features in claim 330. Id. at 285–86
(citing Ewanus 1:7–11, 2:15–3:5). The rejection further turns to Berg, in
combination with Levine, Morley, Gilbert, and Ewanus, to teach or suggest
using a microwave data link, and transmitting signature modulated
information onto a microwave data link coupled to a computer center with a
transmitter based at least in part on at least some of the output signature
modulated information. Id. at 286–87 (citing Berg 13:3–19, 14:33–56).
For the arguments repeating those previously addressed (see Appeal
Br. 106–10), we are not persuaded. We refer above for more details.
Appellant also argues nearly every limitation found in claim 330, which we
address below.
Receiving information from a microwave data link with a receiver
Appellant argues the rejection omits the recitation “from a microwave
data link” recited in claim 330 and that Ewanus’s signal is transmitted from
an antenna and not a microwave data link. Appeal Br. 107 (citing Ewanus,
Fig. 1). We are not persuaded because as noted above, the rejection relies on
Berg, in combination with the teachings of Levine, Morley, Gilbert, and
Ewanus, to teach or suggest the disputed microwave data link. Final Act.
286–87 (citing Berg 13:3–19, 14:33–56); see also Ans. 118. One cannot
show nonobviousness by attacking references individually where the
rejections are based on combinations of references. See Merck, 800 F.2d at
1097. Notably, Appellant does not dispute Berg’s teachings in this regard.
See Appeal Br. 106–10.
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Generating demodulated information by correlating by a correlator
at least some of the second signature information with input signature
modulated information received by the receiver
Appellant argues that Ewanus does not disclose the recited
“generating signature demodulated information by correlating by a
correlator at least some of the second signature information with input
signature modulated information received by the receiver” because the
passage cited in the rejection fails to disclose correlation with input signature
modulated information received by the receiver. Appeal Br. 107 (citing
Final Act. 286; Ewanus 2:15–3:5).
The Examiner disagrees, contending the Specification does not
disclose the “input signature modulated information” or “input signature,”
such that it has a particular meaning beyond “modulated information
received by a receiver.” Ans. 118–19 (citing Spec. 31–32, 221K).
Appellant does not remark on the Examiner’s construction in the Reply
Brief. See generally Spec.
We agree with the Examiner that the Specification does not discuss an
input signature—let alone “input signature modulated information.” See
generally Spec. Nor does the Specification use the phrase “modulated
information” or “modulated.” See generally id. When discussing
“correlation,” the Specification discusses both a “correlation between a
masked reference signature” (Spec. 31:24) and “correlation with a
predetermined signature” (id. at 32:14). As such, we are unsure what the
scope of “input signature modulated information” consistent with the
Specification encompasses beyond modulated information that may be
reference or predetermined information.
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Ewanus teaches a modulation technique, called “correlation slope
modulation,” using a correlator and accomplished at a receiver terminal.
Ewanus 2:34–51, 2:68–3:6, Figs. 1–2; see also Ans. 119. Thus, Ewanus,
when combined with the other references, at least suggests correlation with
“modulated information received by a receiver,” contrary to Appellant’s
arguments, and “input signature modulated information received by the
receiver” as claim 330 recites.
Generating some of the processed information with the data processor
based at least in part on signature demodulated information generated by
the correlator and generating output signature modulated information by
signature modulation with a signature modulator based at least in part on at
least some of the processed information
Appellant argues that Ewanus does not disclose the recited
“generating at least some of the processed information with the data
processor based at least in part on signature demodulated information
generated by the correlator” because the rejection fails to address or
demonstrate what the claim recites. Appeal Br. 107 (citing Final Act. 286).
Similarly, Appellant argues that Ewanus does not disclose the recited
“generating output signature modulated information by signature modulation
with a signature modulator based at least in part on at least some of the
processed information” because the rejection does not address what is
recited and in particular, does not demonstrate Ewanus’s signature
modulation is based on the processed information. Appeal Br. 108 (citing
Final Act. 286; Ewanus 2:39–51).
When considering the rejection in its entirety, the rejection addresses
what claim 330 recites. For example, the rejection refers to claim 235,
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which includes a recitation to “generating processed information with a data
processor.” Appeal Br., App. L74. The rejection of claim 235 relies on the
combination of Levine and Morley to teach this feature and to teach a
system containing input/output ability. See Final Act. 186–88 (citing
Morley 3:3–11, 15:11–18). The rejection then turns to Ewanus, in
combination with Levine, Morley, and Gilbert, to teach or suggest the
recited “signature demodulated information by correlating by a correlator”
as previously discussed and the “output signature modulated information by
signature modulation with a signature modulator,” which outputs its signal
to other components. See id. at 285–86 (citing Ewanus 2:15–3:5, Fig. 2).
Ewanus also teaches that data conversion occurs at the receiver terminal
through correlation. See Ewanus 2:49–51. As such, the combination at least
suggests processing information with information received by the receiver
(e.g., the demodulated information). See id. This rejection further explains
combining Ewanus with the other references improves on security and
privacy. Final Act. 286 (citing Ewanus 1:7–11).
Thus, even when considering Appellant’s arguments, the teachings of
Levine, Morley, Gilbert, and Ewanus when combined, at least suggests
“generating at least some of the processed information with the data
processor based at least in part on signature demodulated information
generated by the correlator” and “generating output signature modulated
information by signature modulation with a signature modulator based at
least in part on at least some of the processed information” in dispute. See
also Ans. 119–20.
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Transmitting signature modulated information onto a microwave data
link coupled to a computer center with a transmitter based at least in part on
at least some of the output signature modulated information
Appellant argues that Ewanus does not disclose the recited
“transmitting signature modulated information onto a microwave data link
coupled to a computer center with a transmitter based at least in part on at
least some of the output signature modulated information” because the
rejection does not state this limitation is taught by any of the references.
Appeal Br. 108 (citing Final Act. 285–87).
We disagree. This argument attacks Ewanus individually when the
rejection relied on Berg for the “microwave data link” features of the claim.
Final Act. 287 (citing Berg 13:3–14, 14:33–56); see also Ans. 120 (same).
The rejection proposes to combine Berg’s teaching with Levine, Morley,
Gilbert, and Ewanus to arrive at the claimed “transmitting” step to decrease
transmission errors. See id. at 286 (noting Levine, Morley, Gilbert, and
Ewanus do not disclose explicitly the “transmitting” step); see id. at 286–87
(citing Berg 13:4–19, 14:33–56). Thus, the rejection discusses what
references teach the “transmitting” step in dispute.
Motivation to Combine Ewanus and Berg with Levine, Morley, and
Gilbert
Appellant also contends the rejection does not propose how the
references are combined or what the resulting structure would be. Appeal
Br. 109. We are not persuaded for reasons stated above and previously
discussed.
Appellant also argues that Ewanus “does not disclose[] a system using
data processing similar to Levine, Morley or Gilbert” and the rejection “fails
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to demonstrate any similarity.” Appeal Br. 106. Appellant further argues
that an ordinarily skilled artisan “would not have been motivated to combine
these disparate references.” Id. at 109. In particular, Appellant contends
“Berg and Ewanus relate to communication,” Levine relates to “analog
memory,” and “Gilbert and Morley” relate to “specialized processing
systems.” Id. Appellant contends Levine, Gilbert, and Morley do not have a
need for a communication system and the combination would not have been
obvious. Id.
As addressed above, the rejection has provided reasons with rational
underpinnings to combine Levine, Morley, and Gilbert. We further
explained above how Levine, Morley, and Gilbert are analogous.
Additionally, the Specification discusses using the CCD arrangement with
“systems including data acquisition, analog signal processing, computer
peripheral, telemetry, and other systems.” Spec. 96:22–24. Thus, teachings
related to analog signal processing (e.g., Levine), computer peripherals (e.g.,
Morley and Gilbert), and telemetry (e.g., Ewanus and Berg) are reasonably
pertinent to the problem Appellant was concerned with or within Appellant’s
field of endeavor. See In re Kahn, 441 F.3d 977, 986–87 (Fed. Cir. 2006).
Additionally, as the Examiner explains, the combined
Levine/Morley/Gilbert system provides an input/output system amenable to
various systems, including Ewanus and Berg. See Ans. 122. Moreover,
“[u]nder the correct analysis, any need or problem known in the field of
endeavor at the time of invention and addressed by the patent can provide a
reason for combining the elements in the manner claimed.” KSR, 550 U.S.
at 420. As explained above, several reasons have been provided to combine
Ewanus and Berg with Levine, Morley, and Gilbert in the manner claimed.
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Appellant also argues one skilled in the art would not have combined
Berg with Ewanus because Berg is a multi-channel, narrow band telephone
communication system and Ewanus, in contrast, is a broadband
communication system. Appeal Br. 110 (citing Berg 14:6–10; Ewanus, code
(57)). This argument is unavailing because the rejection does not propose to
combine Berg’s entire communication system with Ewanus as argued.
Rather, Berg is merely relied upon to teach including and using a microwave
data link and then to combine this teaching with Levine, Morley, Gilbert,
and Ewanus system as proposed to arrive predictably at the recited steps
concerning the microwave data link in claim 330. Final Act. 286–87 (citing
Berg 13:3–19, 14:33–56); see also Ans. 122.
In summary, the record provides at least one reason with a rational
underpinning for an ordinarily skilled artisan to combine the references with
each other.
Conclusion
For the above reasons, we are not persuaded the Examiner erred in
rejecting claim 330 based on Levine, Morley, Gilbert, Ewanus, and Berg.

IV. THE UNDUE MULTIPLICITY REJECTION
The pending claims are rejected under 35 U.S.C. § 112, second
paragraph, as being indefinite for failing to particularly point out and
distinctly claim the subject matter which the applicant regards as the
invention (undue multiplicity). Final Act. 23–104; Ans. 55–100.
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The Examiner found the cumulative effect of presenting 3,273 claims
(1,324 of which are independent claims) directed to this Specification10 and
approximately 115,000 total claims directed to specifications, totaling 399
applications, related by priority claims confuses and blurs the claimed
invention and fails to particularly point out and distinctly claim the subject
matter Appellant regards as the invention. Final Act. 24 (citing MPEP
§ 2173.05(n); the Requirement §§ 4(d), 5, 5(a)), 33 (stating “the repetition
and number of the claims is so overwhelming that one skilled in the art can
no longer be reasonably certain as to the scope of the invention”); see also
Ans. 55–57, 61–63. The Examiner addressed various contributing factors
(e.g., the number of applications, the number of claims in each application,
applicant’s failure to establish a need to present more than 600 claims in the
applications as the Requirement11 sets forth, systematic claim replacement in
response to Office Action after the Requirement, introducing duplicate
claims in different applications, reintroducing previously canceled subject
matter or lost issues in applications, introducing patentably indistinct claims
in applications not sharing common applications, adding claims drawn to
unsupported subject matter, and duplicative/confusing identification of
ancestor claims) that culminated in the undue multiplicity rejection. See
Final Act. 23–104.
Appellant presents rebuttal arguments, including: (1) the family of
applications with a common application are directed to a very large number

10 This application is one of at least 10 applications having “identical
specifications.” Final Act. 24, 34.
11 The Requirement required the Appellant to select a limited number of
claims for examination. See Requirement 2 (first).
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of distinct inventions, (2) the changes in the law, namely the transitional
practice set forth in 37 C.F.R. § 1.129 (“Rule 129”), that took effect in June
8, 1995,12 forced Appellant to file numerous applications, (3) the undue
multiplicity rejection is only appropriate for claims that are confusingly
similar, (4) the raw claim count is not enough to establish an undue
multiplicity rejection, (5) the examination burden is irrelevant, (6) the undue
multiplicity rejection should not apply to all claims in all applications at
once, (7) the Examiner failed to establish material confusion among different
claims in any applications, and (8) the Examiner’s contributing factors are
inaccurate and irrelevant. Appeal Br. 48–74; Reply Br. 10–19.
LEGAL AUTHORITY
The second paragraph of 35 U.S.C. § 112 states “[t]he specification
shall conclude with one or more claims particularly pointing out and
distinctly claiming the subject matter which the applicant regards as his
invention.” 35 U.S.C. § 112; Nautilus, Inc. v. Biosig Instruments, Inc., 572
U.S. 898, 902 (2014). Rule 1.75(a) of the Code of Federal Regulation’s
Title 37 similarly states “[t]he specification must conclude with a claim
particularly pointing out and distinctly claiming the subject matter which the
applicant regards as his invention or discovery.”
Regarding undue multiplicity, one court has stated:
[I]t is proper to allow applicants a reasonable latitude in setting
forth their inventive concepts in different phraseology, but it is
the purpose of claims to point out and define what an applicant

12 The effective date of the Uruguay Round Agreements Act is June 8, 1995.
See also Uruguay Round Agreements Act, Pub. L. No. 103–465, § 532(a),
108 Stat. 4809, 4983–85 (1994). Any patent issuing from the pending
applications filed on or before this date will have a term of seventeen years
from the date of issuance. See 35 U.S.C. § 154 (1994).
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regards as his invention, and that purpose is not served if, as the
result of frequent repetitions, they present to the mind a blur
rather than a definition.

In re Chandler, 254 F.2d 396, 399 (CCPA 1958) (“Chandler I”) (citations
omitted); see also In re Flint, 411 F.2d 1353, 1357 (CCPA 1969) (quoting
the same). “Such latitude . . . should not be extended to sanction that degree
of repetition and multiplicity which beclouds definition in a maze of
confusion. The rule of reason should be practiced and applied on the basis
of the relevant facts and circumstances in each individual case.” In re
Chandler, 319 F.2d 211, 225 (CCPA 1963) (“Chandler II”).
The courts have considered various factors when addressing undue
multiplicity rejections, including the pioneer nature of the invention, the
complexity of the invention, examples of substantial duplication or lack of
material differentiation, and alleged lack of difference in scope of the claims.
Chandler I, 254 F.2d at 398–99; Flint, 411 F.2d at 1356–57. In this
analysis, “[i]t is necessary to balance the possible damage to an applicant
which might result from an insufficient number of claims against the burden
imposed upon the Patent Office and the courts by the presentation of an
unreasonably large number.” Chandler I, 254 F.2d at 399.
ANALYSIS
Based on the record, we sustain the undue multiplicity rejection. We
adopt the undue multiplicity analysis in the Final Office Action and the
Examiner’s Answer, including the discussion related to the Requirement
issued in 2013 and the discussion in the Requirement itself. The Examiner’s
analyses cogently presents the undue multiplicity problem that exists in this
application. Below, we highlight certain points.
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The Requirement, the Final Office Action, and the Examiner’s
Answer indicate this application is one of 399 pending applications, which
contain about 115,000 claims, including about 45,000 independent claims.
Requirement 2–3 (first), 33; Final Act. 4; Ans. 55. The Requirement, the
Final Office Action, and the Examiner’s Answer also indicate this
application is one of at least 10 related applications having identical
specifications, totaling about 3,273 claims, including about 1,324
independent claims. Requirement 2 (first), 7, 33; Final Act. 24; see Ans. 57.
Appendix A includes claim sets for 9 applications that “shar[e] the same
specification as the present application.” Ans. 9, App. A.
As the Examiner explains and as illustrated below, the cumulative
effect of these vast numbers of claims—many of which are independent
claims and repetitive—blurs what Appellant regards as his claimed invention
in this and other applications and results in confusion rather than particularly
pointing out and distinctly claiming the subject matter of Appellant’s
invention. See Final Act. 24. Such blurring between claims and applications
leaves both the Office and the public at large
without any useful way to differentiate between the meanings
of the claims, without any good starting point for determining
what is and what is not covered, and without any meaningful
way to differentiate between the subject matter covered by each
of the largely identical applications. It also leaves the Examiner
(and later a potential licensee or alleged infringer) without any
meaningful way to identify issues related to double patenting
and makes the task of the examiner in drawing a consistent line
of patentability nearly impossible without any identifiable
benefit to the record of the applications.

Id. at 30.
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The Requirement similarly articulated the Office’s challenges with the
vast number and repetition of claims in these applications as follows:
[T]he repetition of similar elements across a vast number of
claims prevents the examiner from forming an understanding of
an overall picture of the claimed invention(s). This results in
inefficient examination of claims in isolation, makes
identification of a consistent line of patentability impractical
and requires impracticable further effort to ensure consistency
within a single action for little apparent benefit.

Requirement 33; id. at 7–32 (noting the claim multiplication, claim
similarities and lack of demarcation in the applications). In particular, the
Examiner notified Appellant that “this multiplication of claims after the time
of filing is an indication that the claims have been unduly multiplied” (id. at
8) and “applicant has presented significantly repetitive claims” (id. at 9).
We agree with the Examiner and add that the result of the frequent repetition
in and multiplication of the claims results in blurring rather than defining
Appellant’s claimed invention in any one particular application, including
the instant application.
Notably, the Federal Circuit has considered the legality of the
Requirement and found:
The PTO issued the Requirements to ensure that Mr. Hyatt’s
applications complied with § 1.75(b). Given the extraordinary
number and duplicative nature of Mr. Hyatt’s various pending
applications, all drawn from the same 12 specifications, it was
reasonable for the PTO to be concerned that the claims did not
“differ substantially from each other,” and that some claims
were “unduly multiplied.” § 1.75(b). In fact, in the
Requirements the PTO demonstrates that across these
applications, Mr. Hyatt has in numerous cases filed identical or
nearly identical claims. This sort of redundant, repetitive
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claiming is inconsistent with § 1.75(b). These special
circumstances . . . justify issuing the Requirements . . . .

Hyatt v. USPTO, 797 F.3d 1374, 1384 (Fed. Cir. 2015) (emphases added).
Thus, in 2015, the Federal Circuit had identified numerous of Mr. Hyatt’s
pending applications as having identical or nearly identical claims and had
described this claiming as “duplicative,” “redundant,” and “repetitive.” Id.
The Requirement additionally prescribed Appellant to select a
reasonable number of claims for examination, amounting to no more than
600 claims across the 10 related applications. Requirement 35–36. The
Federal Circuit found this particular prerequisite justified under the
circumstances. See Hyatt v. USPTO, 797 F.3d at 1377.
Appellant originally selected 143 claims from the pending claims in
this application to be examined. See April 23, 2014 Response to the 37
C.F.R. § 1.105 Office Action 3 (stating “a total of 200 claims in the current
application”); October 30, 2015 Non-Final Action 4 (stating Applicant re-
designated the selected claims to “a total of 143 selected claims”). At
present, Appellant has selected more than fifty claims. Final Act. 5–6
(identifying claims 95, 101, 109, 113, 118, 121, 125, 130, 136, 139, 141,
145, 151, 153, 157, 163, 167, 171, 174, 181, 185, 187, 188, 193, 198, 203,
208, 209, 213, 217, 222, 226, 230, 231, 235, 240, 241, 247, 250, 251, 256,
260, 266, 269, 275, 284, 287, 288, 291, 292, 296, 316, 328, 330, 336, 340,
365, 388, 399, and 421 as selected); see also Ans. 16 (noting “a total of 54
claims”).
To date, Appellant has not explained meaningfully why he needs
more than 600 claims to address his inventions in this and the related
applications as the Requirement permits him to do. See Final Act. 37
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(stating “Applicant, however, has not been forthcoming with any meaningful
plan or explanation for why he had previously presented 115,000 claims, let
alone why more than 600 claims per disclosure was necessary to adequately
protect any alleged inventions”); see also Final Act. 36 (stating “[t]o date,
Appellant has failed to proffer a traverse of the Requirement’s 600-claim
limit”); In re Katz Interactive Call Processing Pat. Litig., 639 F.3d 1303,
1312 (Fed. Cir. 2011) (rejecting patentee’s due process argument because he
failed to prove why needed more claims). Yet, according to Appellant, 131
independent claims and 297 total claims remain in this application alone.
Appeal Br. 2.
When balancing the possible damage to Appellant that might result
from an insufficient number of claims against the burden imposed upon the
Patent Office and the courts by the presentation of an unreasonably large
number of claims across various applications, we agree with the Examiner
(see Ans. 58–89) that the number of claims presented is greatly in excess of
what is necessary, with the result that the claims as now presented do not
particularly point out and distinctly claim the subject matter which the
Appellant regards as his invention as required by 35 U.S.C. § 112. See id. at
61 (stating “[a] person skilled in the art would not be reasonably certain [of]
the scope of the invention in light of the specification, and the undue
multiplicity rejection is therefore appropriate”); see also In re Katz, 639 F.3d
at 1309 (concluding that limiting patentee to 8 asserted claims per unique
specification did not violate his due process rights).
Turning to the instant application, the claims, including the selected
claims, illustrate examples of repetition or lack of material differentiation in
the claims’ scope. Chandler I, 254 F.2d at 398–99; Flint, 411 F.2d at 1356–
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57. The Examiner’s chart found in the Examiner’s Answer (Ans. 63–75)
and limitations discussed in the Final Action (Final Act. 102–03) highlight at
least six common limitations (i.e., integrated circuit charge storage memory,
computer instructions, scratch pad memory, stored program computer, data
processor, and output circuit) found in the pending claims, including the
selected claims, and provide evidence of the frequent repetition in the claims
of this application. See Appeal Br., App. L1–176. Additionally, a seventh
limitation found in many of the selected claims includes loading computer
instructions into memory based at least on part computer instructions (or a
load circuit configured to store computer instructions). Id.; see also Final
Act. 102–03.
To illustrate, selected claims 95, 101, 109, 113, and 125 each recite all
seven limitations noted above:
“integrated circuit charge storage memory” (“Term 1”),
“information stored” in the “integrated circuit charge storage
memory” “including at least some computer instructions” (or similar
recitation) (“Term 2”),
“storing information in a . . . memory” (“Term 3”),
“memory implemented as part of the integrated circuit stored program
computer” (“Term 4”),
“loading computer instructions into . . . memory. . . based at least in
part on computer instructions” (or similar recitation) (“Term 7”),
“generating processed information with a data processor based at least
in part of on information stored in the . . . memory and based at least in part
on computer instructions stored in . . . memory” (or similar recitations)
(“Term 5”), and
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“generating computer output information with a computer output
circuit based at least in part on computer instructions stored in . . . memory”
(or similar recitation) (“Term 6”).
Id. at App. L1, 4–5, 7–9, 14–15.
To summarize, each of the selected claims include the following
similar concepts below:
Claim Term 1 Term 2 Term 3 Term 4 Term 5 Term 6 Term 7
Charge
storage
memory
Stored info
that
includes
computer
instructions
Storing
info in
memory
integrated
circuit stored
program
computer
Generating
processed info
with a data
processor
based on
computer
instructions
Generating
output info
with an
output
circuit based
on computer
instructions
Loading
computer
instructions
into memory
95 X X X X X X X
101 X X X X X X X
109 X X X X X X X
113 X X X X X X X
118 X X X X X X
121 X X X X X X X
125 X X X X X X X
130 X X X X X X
136 X X X X X X
139 X X X X X X
141 X X X X X X
145 X X X X X X
151 X X X X X X X
153 X X X X X X
157 X X X X X X
163 X X X X X X
167 X X X X X X
171 X X X X X X
174 X X X X X X X
181 X X X X X X
187 X X X X X X X
188 X X X X X X
193 X X X X X X X
198 X X X X X X
203 X X X X X X X
208 X X X X X X
209 X X X X X X X
213 X X X X X X X
217 X X X X X X X
226 X X X X X X X
230 X X X X X X X
235 X X X X X X X
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240 X X X X X X X
241 X X X X X X X
247 X X X X X X
251 X X X X X X X
256 X X X X X X
260 X X X X X X X
266 X X X X X X X
269 X X X X X X X
275 X X X X X X
284 X X X X X X X
288 X X X X X X X
291 X X X X X X X
296 X X X X X X X
316 X X X X X X X
328 X X X X X X X
330 X X X X X X X
336 X X X X X X X
340 X X X X X X X
365 X X X X X X X
388 X X X X X X X
399 X X X X X X X
421 X X X X X X X

Table 1 Showing Terms 1-7 Corresponding to Selected Claims
Appeal Br., App. L1–163 (“X” indicating the claim contains the
corresponding term); see also Ans. 63–75.
Appellant’s summary of the claimed invention in the Appeal Brief
also supports the above findings. See Ans. 80 (citing Appeal Br. 5–16). The
Appeal Brief states the selected claims and other pending claims recite “a
charge storage memory” (i.e., Term 1) (Appeal Br. 7–11 and 13–16),
“storing information” in memory (Term 3) (id. at 8 and 14), “integrated
circuit stored program computer” (or similar recitation) (Term 4) (id. at 9),
“loading computer instructions” in memory (i.e., Term 7) (id. at 6–7 and 12),
“a data processor configured to generate . . . information” (or similar
recitation) (i.e., Term 5) (id. at 6 and 11), and “a computer output circuit
configured to generating computer output information” (or similar
recitation) (i.e., Term 6) (id. at 5 and 10–11).
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The Examiner further states numerous other independent claims in
this application, amounting to 82 independent claims, include the above-
noted, overlapping subject matter (i.e., charge storage memory, integrated
circuit, data processor, and output circuit) (i.e., Terms 1, 4–6). Ans. 63–75.
Thus, the chart in the Examiner’s Answer (Ans. 65–67), the above
Table 1, and Appeal Brief (Appeal Br. 5–12) illustrate the frequent repetition
of claimed subject matter as a whole currently found in the independent
claims of the instant application, which results in blurring rather than
defining what Appellant regards as his invention. See Chandler I, 254 F.2d
at 399; see also Ans. 59 (stating “the instant application includes a ‘volume
of claims and the repetitious . . . ‘elements’ which tend more ‘to confuse
rather than define’ the invention”) (quoting Chandler II). The above
discussion also illustrates substantial duplication of the claims and lack of
material difference in the claims in the application, such that claims fail to
inform with reasonable clarity an ordinary artisan as to what Appellant
regards as the scope of his invention as Nautilus, 572 U.S. at 901, prescribes.
We further agree with the Examiner that the above-discussed unnecessary
repetition in numerous independent claims leads to a degree of multiplicity
and creates ambiguity in the claims as to what Appellant regards as his
invention in this application. See Ans. 63 (stating “Appellant cannot cleanly
divorce the numerosity of his claims from the clarity of his claims; it is
Appellant’s volume of claims in combination with the degree of repetition
and multiplicity that confuses the invention”).
To illustrate further, this application started with forty-five claims in
1994 (Spec. 235–247), grew to 448 claims over the years (see Appeal Br.,
App. L1–176), and resulted in about 297 claims for examination at the time
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of the Final Office Action. See id. at 2 (noting “131 independent claims and
297 total claims remaining in this application”). More specifically, about 45
new claims were submitted in 1995, and, nearly 350 new claims were added
in 1998. Also, in 2003, Appellant submitted substantial amendments to the
claims “to more particularly point out the Applicant’s invention” (see
September 19, 2003 Amendment 1; see id., App. A1–105) and then, in both
2014, and 2016, Appellant substantially or effectively rewrote many of the
pending claims but still continued to recite unnecessary repetition in the
claim language in numerous independent claims, leading to a yet another
degree of multiplicity and ambiguity. See April 23, 2014 Amendments and
Disclosures, App. A1–186; see also June 20, 2016 Reply to Office Action,
Att. 1, pp. 1–309. Only while on appeal, Appellant attempted to cancel
many of the pending claims (including selected claims 95, 101, 109, 113,
118, 121, 130, 136, 141, 145, 153, 157, 163, 167, 171, 181, 193, 198, 203,
208, 209, 217, 226, 240, 241, 247, 251, 260, 266, 269, 275, 284, 288, 296,
316, 328, 330, 336, 340, 365, 388, and 421 in the 2020 Amendment). See
March 18, 2019 Amendment; see also July 2, 2020 Amendment 2–32.13
We need not decide whether the raw claim count alone demonstrates
undue multiplicity as argued. See Appeal Br. 53–55, 59. Rather, as stated
by the Examiner, “the claims as a whole are unduly multiplied such that they
tend to obscure and confuse any contribution to the art rather than
‘particularly pointing out and distinctly claiming’ the invention. The claims
. . . employ repetitive language; they include duplicative and confusingly
similar language.” Final Act. 30 (referring to the Requirement); see also

13 As previously indicated, this amendment was not entered.
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Ans. 18, 59 (noting the repetitive nature of the claims confuses the claimed
invention).
The combination of issues, as discussed above and more below,
demonstrates undue multiplicity. See Ans. 82 (stating “Appellant’s practices
have, from the perspective of the public, obscured the metes and bounds of
the claimed subject matter”), 90 (stating “Appellant is effectively using
amendment practice to obscure the invention rather than clarify it”). For
example, the Examiner indicates that “[t]he total number of claims [within
the nearly 400 applications] ballooned to approximately 115,000, with 3,273
claims drawn to the same specification in this family.” Ans. 19 (footnote
omitted). More specifically, the number of claims in each of the 10 related
applications totaled 3,273 claims and 1,324 of these claims were
independent claims. Requirement 6. The Requirement explains the pattern
of the claims greatly multiplied in the applications over the years and this
multiplication traditionally is “an indication that the claims have been
unduly multiplied.” Id. at 8; see also id. at 7–8. Thus, when balancing the
possible damage to Appellant that might result from an insufficient number
of claims against the burden imposed upon the Office and the courts by the
presentation of an unreasonably large number as Chandler I, 254 F.2d at
399, states, we agree with the Examiner (see Ans. 58–77) that the number of
claims presented in this application exceeds what is necessary, with the
result that the claims as now presented do not particularly point out and
distinctly claim the subject matter which the Appellant regards as his
invention as required by 35 U.S.C. § 112.
Appellant contends that examination burden is an “irrelevant factor”
in an undue multiplicity rejection. Appeal Br. 55; see id. at 55–57. Yet,
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Chandler I states, when addressing an undue multiplicity rejection, “[i]t is
necessary to balance the possible damage to an applicant which might result
from an insufficient number of claims against the burden imposed upon the
Patent Office and the courts by the presentation of an unreasonably large
number.” Chandler I, 254 F.2d at 399 (emphases added). As the Examiner
further explains,
the burden on the public to understand the metes and bounds of
the disclosed subject matter caused by Appellant’s claims is the
key inquiry. The obfuscation of the claimed subject matter
caused by Appellant presenting 3,273 related claims,
complicated by a high degree of overlap and the continued
shifting of subject matter from one application to another, must
be considered when assessing the clarity and definiteness of the
claims of the instant application.

Ans. 79. Thus, we disagree with Appellant that burden considerations are
not pertinent to an undue multiplicity rejection.
Additionally, the “Kunin memo”14 indicates an undue multiplicity
rejection may be appropriate when applicant presents an unreasonable
number of claims in view of the invention’s nature and scope that are
repetitious and multiplied, resulting in confusion rather than clarity. See
Ans. 81 (discussing the Kunin memo, pp. 1–2; MPEP § 2173.05(n)). As
explained above, the record demonstrates how Appellant has presented
repetitious and multiplicative claims in this and other applications that fail to
inform an ordinary artisan what he regards as his invention. See id. at
79–83.
Appellant contends that Appendix E shows “how each of the

14 Appellant refers to the following website: http://www.uspto.gov/web/
offices/pac/dapp/opla/documents/multiplicity.pdf. Appeal Br. 57.
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independent claims is directed to different combinations of elements and
how any pair of claims differ from one another.” Appeal Br. 59; id. at
59–60, App. E1–5. In the Reply Brief, Appellant attempts to further clarify
the distinctions among the claims by presenting Appendix E6. Reply Br. 15,
App. E6; see id. at 15–16. Like the Examiner (Ans. 84–86), we are not
persuaded that these appendices clarify the purported distinctions.
As noted, Appendix E “illustrates the similarities between the instant
claims and the pattern discussed in Chandler II.” Ans. 84. For example,
Appendix E shows each claim, including selected claims 95, 109, 118, 130,
141, 145, 151, 163, 181, 187, 198, 208, 226, 235, 240, 241, 247, 251, 266,
296, 316, 340, 399, and 421 in Appendices E1–E4, includes a “charge
memory” (Term 1 found in Table 1) and “IC computer” (Term 4) (Ans. 84)
and that many other claims include “analog info” and “converters” (id.). See
also Appeal Br., App. E1–E3. Additionally, Appendix E3–E5 shows that
many claims, including the selected claims, include recitations to “computer
instructions” (Term 2) and “loading info. into” memory “with a load circuit”
(Term 7). See id., App. E3–5. Thus, the appendices, when considered in the
context of Table 1, provide evidence of the frequent repetition of claim
language used in numerous independent claims.
To be sure, the appendices show differences between the pending
claims, such that all the same boxes in these appendices are not ticked. See
Appeal Br. 59 (arguing that “Appendix E allows the Board to see . . . how
each of the independent claims is directed to different combinations of
elements”). However, Appellant’s attempt to distinguish the claims as
materially different falls short. For example, Appellant omits that the above-
noted selected claims each recite an “integrated circuit charge storage
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memory” (Term 1) (emphasis added), “information stored” in the
“integrated circuit charge storage memory” “including at least some
computer instructions” (Term 2), “memory implemented as part of the
integrated circuit stored program computer” (Term 4), “generating processed
information with a data processor based at least in part of on information
stored in the . . . memory and based at least in part on computer instructions
stored in . . . memory” (or similar recitations) (Term 5), and “generating
computer output information with a computer output circuit based at least in
part on computer instructions stored in . . . memory” (or similar recitation)
(Term 6). Compare Appeal Br. App. E1–E5, with id., App. L1–163; see
also Ans. 84 (noting “the terms ‘data processor’, and ‘output circuit’ repeat
in nearly every independent claim, [but] they are not represented” in the
appendices). Upon review and as discussed above, these appendices fail to
account for the numerous similarities found in the claims that further
demonstrate repetition and multiplicity of the claims.
Moreover, when addressing an undue multiplicity rejection, one court
noted:
Such an arbitrary division does not establish that there are
material differences between the claims. Whether a claim in
[sic] broad or narrow is a matter of degree and opinion, and it
does not follow that two claims are patentably, or even
materially, different from each other merely because one may
be termed ‘broad’ and the other ‘narrow.’ Similarly, two claims
do not necessarily differ materially because one merely recites
only one engine while the other recites several; and the fact that
one of two claims is drawn to a method, and the other to an
apparatus is not, in itself, proof that both are necessary to
protect appellant’s invention.

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Chandler I, 254 F.2d at 399. Thus, even though some claims are narrower
than others by reciting additional features, Chandler I supports that these
types of claims may not be materially different.
As one example in this application, some claims recite “storing
computer instructions in a computer main memory” (e.g., selected claim
113). Appeal Br., App. L9. Other narrower claims recite “storing
information in charge storage elements included in an integrated circuit
charge storage memory, . . . the information stored in the plurality of charge
storage elements including at least some computer instructions” (or similar
recitation) (e.g., selected claims 109 and 118). Id., App. L7, L10. While yet
other, even narrower claims recite “storing analog information in charge
storage elements” and the “analog information stored in the charge storage
elements including at least some computer instructions” (e.g., selected
claims 95 and 121). Id., App. L1–2.
Appellant also argues “‘[r]epetition’ of specific elements cannot make
the difference.” Appeal Br. 60; see also Reply Br. 18. Claims containing
individual elements repeatedly (e.g., repeating terms in various dependent
claims) may not show the degree of repetition and multiplicity that creates
the requisite confusion to establish undue multiplicity. However, the
frequent repetition of the above-discussed claimed terms (i.e., Terms 1–7 in
Table 1) found in the discussed claims, including the selected claims,
demonstrate the repetition and multiplicity that fails to inform an ordinary
artisan as to what Appellant regards as his invention.
Thus, when balancing the possible damage to Appellant that
might result from an insufficient number of claims against the burden
imposed upon the Patent Office and the courts by the presentation of an
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unreasonably large and repetitive number of claims in this application,
we agree with the Examiner that the number of claims presented is
greatly in excess of what is necessary, with the result that the claims as
now presented do not particularly point out and distinctly claim the
subject matter which the Appellant regards as his invention as required
by 35 U.S.C. § 112. See In re Chandler I, supra; see also In re Katz,
supra.
Appellant argues that we must only consider whether the claims in
this application, not other applications, are unduly multiplied. Appeal Br.
57–58. We disagree, but above, have addressed how the claims in this
application are unduly multiplied. Moreover, the Board opinion cited by
Appellant (id. at 58; Reply Br. 10) is non-precedential. As discussed above,
the Federal Circuit considered nearly 400 applications, and approved the
Office’s “issuance of the Requirements” related to 37 C.F.R. § 1.75(b),
which permits presenting claims “provided they differ substantially from
each other and are not unduly multiplied.” Hyatt v. USPTO, 797 F.3d at
1384 (emphasis omitted); see id. at 1385 (discussing “the volume and
interwoven nature of his claims” in various application).
Regarding the 10 applications with an identical specification to this
application (Ans. 83), the Examiner notes another application (e.g., U.S.
Application No. 08/433,307 (“the ’307 application”)) “includes a total of
109 independent claims reciting the terms ‘charge storage memory’,
‘integrated circuit’, ‘stored program computer’, ‘data processor’, and ‘output
circuit’” and is similarly “drawn to ‘Integrated circuit computers having
hybrid memories’.” Id. at 79; see also id., App. A (including the pending
claims for the ’307 application). For example, similar to claim 118 of this
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application, claim 52 of the ’307 application recites a “charge storage
memory” (Term 1), “information stored” in the “integrated circuit charge
storage memory” “including at least some computer instructions” (Term 2),
“memory implemented as part of an integrated circuit stored program
computer” (Term 4), “a data processor configured to generate correlated
information” based on “computer instructions” (Term 5), and an “output
circuit configured to generate output information” “based at least in part on
computer instructions” (Term 6). See Ans. 33–34; compare id., App. A, the
’307 application, p. 1, with Appeal Br., App. L10 (claim 118). As another
example, claim 55 of the ’307 application recites similar recitations to claim
118 of this application. Ans. 35–36; see id., App. A, the ’307 application, p.
2. Further examples exists. See id. at 32–33 (discussing claim 52 of U.S.
Application No. 08/469,061 and claim 118 of this application); see also id.,
App. A (U.S Application No. 08/469,061, p. 1).
As the Examiner states, “Appellant does not deny the duplication”
exists in the applications. Ans. 91 (citing Appeal Br. 66; Final Act. 43–44).
For example, the Examiner indicated examples of “filing identical (not
merely patentably indistinct) claims across different applications” at the time
of the Requirement. Final Act. 43–44. Certain duplicate claims found in the
related applications (Ans. 9) included: U.S. Application Nos. 08/469,061
(e.g., claims 108, 120, 124, 132, 204, 216, 338, 342, and 357), 08/428,737
(e.g., claims 130, 288, 291, 296, 327, 338, 350, 351, 356, and 369),
08/435,502 (e.g., claims 106, 120, and 124), 08/471,214 (e.g., claims 96,
104, and 108), 08/429,272 (e.g., claims 60, 72, and 92), and 08/285,669
(e.g., claim 353, 364, and 369). Requirement 10–29. Other examples exist.
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See id. at 29–31.15 The noted claims in the above applications therefore
further illustrate the repetition or duplication of claims across applications.
In the Reply Brief, Appellant contends “[n]one of those three
applications[16] contain even one claim directed to the three-memory
computer architecture of the nature described in the summary.” Reply Br.
12. Even presuming Applicant’s statement is accurate, the above examples
illustrate substantial duplication or lack of material differentiation in the
claims of different applications.
Appellant asserts that the undue multiplicity rejection is unsupported
“because a tiny number of claims of applications that are not in this
application . . . at some time in the past contained duplicates in a still further
different application, again not this application.” Appeal Br. 66. For the
above reasons, we are not persuaded by this argument.
Additionally, the Examiner further discusses various, other
contributing factors, including: (1) the number of applications and claims
per application (Final Act. 34–35), (2) systematic claim replacement (id. at
38–43), (3) reintroducing previously canceled subject matter into various
applications (id. at 45–50), (4) introducing patentably indistinct claims in
applications that do not share a common disclosure (id. at 58–71), and (5)
adding claims drawn to unsupported subject matter (id. at 71–73). To extent
the above factors contribute to demonstrating undue multiplicity rejection

15 The Examiner also provides examples of subject matter from “a single
‘Ancestor Claim’ has been identified in more than one different application
as a reason for introducing claims in each of the applications.” Final Act.
75; see id. at 75–98.
16 The three applications are U.S. Applications Nos. 08/428,737, 08/433,307,
and 08/469,061. Reply Br. 11.
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for the claims in this application, we adopt the Examiner’s position (see also
Ans. 57–92) and are not persuaded by Appellant’s arguments (see Appeal
Br. 43–70; see Reply Br. 70–100).
For the foregoing reasons, we agree with the Examiner that the claims
in the instant application and other applications qualify as one of the rare
instances where an undue multiplicity rejection is warranted. We, therefore,
disagree with Appellant that the undue multiplicity rejection is legally and
factually unjustified (Appeal Br. 48; Reply Br. 10) and “largely relies on the
high claim count in many different applications” (Appeal Br. 49).
Accordingly, we sustain the rejection of the pending claims as being
indefinite for failing to particularly point out and distinctly claim the subject
matter which the applicant regards as the invention on undue multiplicity
grounds.
V. THE PROSECUTION LACHES REJECTION
The Examiner rejects the pending claims on the grounds of
prosecution history laches based on Appellant’s delay in prosecuting the
claims in the present application, related applications, and Appellant’s other
applications. Final Act. 287–341; Ans. 18–55.
LEGAL AUTHORITY
The Supreme Court has stated:
Congress relies for the public benefit to be derived from the
invention during the monopoly on the natural motive for gain in
the patentee to exploit his invention and to make, use, and vend
it or its product or to permit others to do so, for profit. . . . Any
practice by the inventor and applicant for a patent through
which he deliberately and without excuse postpones beyond the
date of the actual invention, the beginning of the term of his
monopoly, and thus puts off the free public enjoyment of the
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useful invention, is an evasion of the statute and defeats its
benevolent aim.

Woodbridge v. United States, 263 U.S. 50, 55–56 (1923).
Concerning these principles, the Federal Circuit has stated:
This court has earlier held in this case that prosecution laches
may render a patent unenforceable when it has issued only after
an unreasonable and unexplained delay in prosecution. Symbol
[Techs., Inc. v. Lemelson Med., 277 F.3d 1361, 1363, 1368
(Fed. Cir. 2002)]. We did not set forth any firm guidelines for
determining when such laches exists . . . . Thus, there are no
strict time limitations for determining whether continued
refiling of patent applications is a legitimate utilization of
statutory provisions or an abuse of those provisions. The matter
is to be decided as a matter of equity . . . . [T]he doctrine should
be used sparingly lest statutory provisions be unjustifiably
vitiated.

Symbol Techs., Inc. v. Lemelson Med., 422 F.3d 1378, 1384–85 (Fed. Cir.
2005), amd’d on reh’g in part, 429 F.3d 1051 (Fed. Cir. 2005). Notably,
“an examination of the totality of the circumstances, including the
prosecution history of all of a series of related patents and overall delay in
issuing claims, may trigger laches.” Symbol Techs., 422 F.3d at 1386; see
also Hyatt v. Hirshfeld, 998 F.3d 1347, 1366 (Fed. Cir. 2021) (“We clarify,
consistent with . . . our past precedent, that prosecution laches considers the
totality of circumstances[.]”).
The Federal Circuit held the Office can reject claims in an application
on the ground of prosecution laches. In re Bogese, 303 F.3d 1362, 1368–69
(Fed. Cir. 2002). That is, “[i]t necessarily follows that the PTO has the
authority to reject patent applications . . . that would be unenforceable under
our holding in Symbol Technologies.” Id. at 1367. “Indeed, we think the
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PTO’s authority to sanction undue delay is even broader than the authority
of a district court to hold a patent unenforceable.” Id.
ANALYSIS
Based on the record, we sustain the rejection of the pending claims on
the grounds of prosecution laches.
Preliminary Matters
Appellant argues the Supreme Court does not accept prosecution
laches as a viable defense because equitable defenses cannot override
statutes. Appeal Br. 18–19 (citing SCA Hygiene Prod. Aktiebolag v. First
Quality Baby Prod., LLC, 137 S. Ct. 954 (2017)); see Reply Br. 9.
Appellant contends this principle in SCA Hygiene applies to the instant
application because “the Patent Act requires the PTO to grant patents unless
statutory requirements are found lacking, and conversely confers a legal
right to issuance of patents for applicants satisfying statutory requirements,
see, e.g., 35 U.S.C. §§ 101, 102.” Appeal Br. 18. Appellant also contends
“[t]he SCA case did not restrict its reasoning specifically to statutes of
limitations.” Appeal Br. 19.
This argument is unavailing. SCA Hygiene held that the statutory time
bar for recovering damages overrides any equitable laches remedy. See SCA
Hygiene, 137 S. Ct. at 959 (stating “‘[l]aches’ . . . ‘cannot be invoked to bar
legal relief’ ‘[i]n the face of a statute of limitations enacted by Congress’”)
(quoting Petrella v. Metro-Goldwyn-Mayer, Inc., 572 U.S. 663, 679 (2014)),
963. Here, however, there is no applicable statute of limitations that could
override the prosecution laches doctrine. See Ans. 21 (“[t]he statutes
Appellant references, §§ 120, 132, 133, discuss continuation practice, notice
of patent rejection, and time to respond to actions. SCA Hygiene does not
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abolish of equitable defenses as related to these statutes; to the contrary, SCA
Hygiene explicitly states equitable estoppel is still available”) (citing SCA
Hygiene, 137 S. Ct. at 967). Moreover, as indicated by the Examiner (see
Ans. 20), Appellant’s interpretation of SCA Hygiene is inconsistent with
Symbol Technologies (referred to as “Symbol I”), which determined 35
U.S.C. §§ 120 and 121 do not foreclose a prosecution laches defense. Id.
(“In Symbol I, the defendant, Lemelson, argued that §§ 120 and 121 of the
Patent Act, codifying continuation and divisional practice respective to filing
dates of parent applications, foreclosed the application of laches. Symbol
Techs., Inc. v. Lemelson Medical, Educ. & Research Found., LP, 277 F.3d
1361, 1365 (Fed. Cir. 2002) (“Symbol I”). The Federal Circuit rejected this
argument, explaining the history and commentary on the 1952 Patent Act
‘shows an intent to maintain the [prosecution laches] defense.[’] Id at
1366.”).
Also, Bogese stated that statutes, such as “35 U.S.C. §§ 120 and 121,
which entitled continuation and divisional applications to the filing dates of
their parent applications, did not foreclose the application of prosecution
history laches to bar enforcement of a patent claim.” Bogese, 303 F.3d at
1367 (citing Symbol Techs., 277 F.3d at 1365–66). The court further stated
“the equitable doctrine of laches may be applied to bar enforcement of a
patent that issued after unreasonable and unexplained delay in prosecution,
even though the patent applicant complied with pertinent statutes and rules.”
Id. (citing Symbol Techs., 277 F.3d at 1368); see also Hyatt v. Hirshfeld, 998
F.3d at 1369 (“Hyatt’s conduct—including his delay in presenting claims,
his creation of an overwhelming, duplicative web of applications and claims,
and his failure to cooperate with the PTO—was a clear abuse of the patent
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system, even if it did not literally violate regulations or statutory
provisions.”).
Both the Supreme Court and the Federal Circuit recognized rejections
based on the principle of prosecution laches. In Bogese, the Federal Circuit
stated:
We found that the Supreme Court had recognized the doctrine
of prosecution history laches in at least four decisions,
including General Talking Pictures Corp. v. Western Electric
Co., 304 U.S. 175 . . . , Crown Cork & Seal v. Ferdinand
Gutmann Co., 304 U.S. 159 . . . (1938), Webster Electric Co. v.
Splitdorf Electrical Co., 264 U.S. 463 . . . (1924),
and Woodbridge v. United States, 263 U.S. 50 . . . (1923). . . .
Thus, . . . we held that a patent may be rendered unenforceable
if it was obtained after an unreasonable and unexplained delay
in prosecution.

Bogese, 303 F.3d at 1367. SCA has not changed these principles.
When addressing the concept of prosecution laches, Symbol
Technologies states, “an examination of the totality of the circumstances,
including the prosecution history of all of a series of related patents and
overall delay in issuing claims, may trigger laches.” Symbol Techs., 422
F.3d at 1386 (emphasis added); see Hyatt v. Hirshfeld, 998 F.3d at 1362
(quoting the same). Thus, despite any arguments to the contrary (see Appeal
Br. 20, 58; see also Reply Br. 17), the Examiner properly considered the
prosecution history of this application and applications related to this instant
application. See Final Act. 289 (quoting Symbol Techs., 422 F.3d at 1385–
1386); see Ans. 21 (discussing the “laches [rejection] is based on ‘the
totality of the circumstances, including the prosecution history of a series of
related patents and overall delay in issuing claims’”) (quoting Symbol
Techs., 422 F.3d at 1386), 29 (indicating the prosecution history of all
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Appellant’s applications are part of the “totality of circumstances” test), 43
(same).
To the extent Appellant contends the Office must follow the court’s
holding in Hyatt v. Iancu, No. 1:09-cv-018690 (D.D.C. July 31, 2018)
(Appeal Br. 41–42; id., App. C) and that the prosecution laches rejection is
precluded by this decision (see id. at 41–42), we note that we do not take
exception with Appellant filing the related applications but rather determine
the record shows delay in prosecuting the claimed invention through the
repetitive filings of the same or substantially identical claims in later
applications. Also, the prosecution laches portion of Hyatt v. Iancu has been
vacated and remanded. Hyatt v. Hirshfeld, 998 F.3d 1347 (Fed. Cir. 2021).
Specifically, the Federal Circuit found that “[w]hen the above circumstances
are considered in their totality, we believe the conclusion is inescapable that
the PTO satisfied its burden of proving that Hyatt engaged in unreasonable
and unexplainable delay, as prosecution laches requires.” Id. at 1369. The
Federal Circuit added that “Hyatt’s time-wasting process obstructed the PTO
from examining not only Hyatt’s four applications at issue, but nearly all of
his GATT Bubble applications.” Id.
Prosecution Histories of this Application and Related Applications
Turning to the prosecution histories of the applications, the instant
application was filed on August 3, 1994. This application was one of 10
applications “sharing the same specification as the present application.”
Ans. 9. As originally filed, the instant application indicated it is a
continuation of U.S. Application Nos. (1) 07/495,808 (now U.S. Patent No.
5,339,275), filed March 16, 1990, and (2) 07/493,061 (now abandoned),
filed March 13, 1990 (each being a “parent application”). Spec. 1:3–5,
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3:24–26. As filed, the instant application also indicated parent application
07/495,808 is a continuation of U.S. Application No. 06/520,277 (now U.S.
Patent No. 4,910,706), filed August 4, 1983 (“grandparent application”),
which is a divisional application of U.S. 06/160,871 (now U.S. Patent No.
4,445,189), filed June 19, 1980 (“great-grandparent application”), which is a
continuation in part of twenty-nine other applications, including U.S.
Application No. 05/844,765 (now U.S. Patent No. 4,523,290), filed October
25, 1977. Id. at 1:11–3:23. We, as does the Examiner (see Ans. 21–22, 24),
thus disagree that Appellant “has not filed numerous continuations in
series.” Appeal Br. 21.
Appellant states “the Board is entitled to assume that the effective
filing date of any claim supported by this application is October 25, 1977
(with appellant reserving the right to demonstrate an earlier invention date if
appropriate).” Appeal Br. 4; see Reply Br. 2 (stating the priority date is for
the “selected claims” is “October 25, 1977”). The Examiner disagrees (Ans.
17), indicating “the 13 March 1990 priority date of the prior Office action is
maintained.” Id. at 18.17 We need not resolve this disparity but begin with
the great-grandparent 06/160,871 (now U.S. Patent No. 4,445,189) filed
June 19, 1980, based on the above-discussed portions of the Specification.18

17 The Examiner contends this application is a continuation in part of U.S.
Application No. 07/495,808, and U.S. Application No. 07/495,808 is a
continuation of U.S. Application No. 06/250,277. December 16, 2015 Non-
Final Office Action 25–26.
18 In a Response to Requirement, dated September 21, 2006, Appellant
disagreed with the priority representation, but stating “Exhibit A appears to
be ‘a correct representation of Applicants claim for priority[.]’” Response to
Requirement 2. On the other hand, Appellant stated “he is unable to confirm
the representation” (id.) but then indicated that he “is currently relying on
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Great-grandparent application 06/160,871 issued as U.S. Patent No.
4,445,189. Allowable subject matter was indicated as early as 1982. See
U.S. Application No. 06/160,871’s December 27, 1982 Non-Final Act. 1,
box 3 (indicating claims 32–37 allowable). A restriction requirement was
presented in the great-grandparent application in 1982. February 25, 1982
Office Action 1 (restricting claims 1–67). Similarly, allowable subject
matter was indicated in (1) grandparent application 06/520,277 (now U.S.
Patent No. 4,910,706) in 1989, (2) parent application 07/495,808 (now U.S.
Patent No. 5,339,275) as early as 1992, and (3) parent application
07/493,061 (presently abandoned) as early as 1990. See U.S. Application
No. 06/520,277’s September 25, 1989 Notice of Allowance; see also U.S.
Application No. 07/495,808’s April 9, 1992 Non-Final Act. 1, box 5; U.S.
Application No. 07/493,061’s November 7, 1990 Non-Final Act. 1, box 5.
Despite the Office indicated allowable subject matter in parent application
07/493,061 (“the ’061 application”) in 1990, Appellant does not provide a
sufficient explanation why he chose not to pass the allowable claims to
issuance, including the period after the Board decisions in 1998 and 1999
and prior to any letter of suspension in 2007 for the ’061 application (e.g.,
over seven years). The ’061 application went abandoned as of 2017.
In or around 1995, Appellant filed about 400 applications (Appeal Br.
16), including the 10 applications within the instant application’s family to
address the “much more than 10 inventions.” Id. at 49. Thus, Appellant
appears to indicate that if not for the change in law in 1995, he may have
waited even longer to file applications to cover all his invention. Ans. 53–54

the June 19, 1980 effective filing data [sic] of ancestor application SN
06/160,171 for the instant claims.” Id. at 3.
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(stating “[t]he Appellant appears to argue that he was simply waiting and, if
not for the change in law in 1995, he would have waited even longer to file
continuations and divisions of his applications”). Based on the foregoing,
Appellant has not demonstrated how or in what way, prior to May 1995 or
for at least fifteen years from the filing of the great-grandparent application,
he was prevented from prosecuting the other inventions identified in the
great-grandparent, grandparent, and parent applications (or the self-
identified “more than 10 inventions”), such as by filing other applications
prior to 1995. See also Ans. 22 (stating “Appellant has provided no
explanation of the 17 years between his asserted priority date and the filing
of this application in 1994”), 54 (noting “Appellant had already waited 18
years since the filing of the asserted priority document to file this
Application”).
The Examiner further notes Appellant met with “Director Godici on
24 October 1995.” Ans. 22. Specifically, “Applicant agreed to file
supplemental preliminary amendments having focused claims in said 49
related applications, as suggested by Director Godici.” Appeal Br., App.
F15–16. Further, “[t]he Applicant said that he would diligently work to do
as Director Godici had suggested, that he would generate amendments that
focused the claims on different inventive features at the rate of five
amendments per week for his applications that were pending in group 2600.”
Id., App. F16. Yet, Appellant waited until June 12, 1998 to submit a
substantive amendment in this application to the claims, adding about 275
new claims. June 12, 1998 Amendment 1, App. A1–95; see also Ans. 19
(stating “[i]nstead of filing claim amendments that would provide ‘better
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focus’ and differentiate his applications, Appellant added hundreds of claims
to each of his applications”).
We thus disagree with Appellant contention’s that he “followed
through on the discussion with Group Director Godici about ‘demarcating’
applications” (Reply Br. 7) at the asserted pace. See Ans. 23 (stating
“[d]espite Appellant’s statements and amendments, such lines of
demarcation were either never established, or were simply made worse, as
the number of Appellant’s claims grew dramatically over time”), 52
(“[D]espite committing to promptly tailor each application to those
inventions and asking for time to differentiate his applications in 1996,
Appellant . . . failed to remedy the problem he created.”).
Appellant specifically argues that “the Godici interview” in addition
to other attacks “are amply addressed by the court decision in the Section
145 Actions, in which the examining group failed to persuade a neutral
decision-maker that appellant did anything improper or caused undue or
unexplained delay. The same findings apply here.” Appeal Br. 26. The
above-noted findings and those discussed below rely on statements made by
Appellant, separate from the Godici meeting, that he sought to better focus
the claims in this and other applications. Also, the facts in this application
differ from those in the district court case, and the district court decision
regarding prosecution laches, including the findings related to the Godici
meeting, has been vacated and remanded. Hyatt v. Hirshfeld, 998 F.3d at
1369 (“As the record shows, Hyatt agreed with Director Godici in October
1995 to demarcate his applications, but he then did precisely the opposite to
an extreme degree. Twenty years later, Hyatt acknowledged he lacked a
‘master plan’ for demarcating his applications.”).
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Appellant indicates that the 400 applications were filed “shortly
before the implementation of the Uruguay Round of the General Agreement
on Tariffs and Trade (GATT)” and any resulting difficulties examining these
applications “do not warrant a prosecution laches finding against” Appellant.
Appeal Br. 22 (quoting id., App. C). This argument is unavailing because
the laches rejection does not rely on the filing of the 400 applications but
rather, as explained above and below, various actions taken by Appellant
prior to and after filing these applications in 1995.
Below highlights the prosecution history of the instant application
and claim amendments submitted:
(1) Preliminary Amendment (Amendment 1) on April 18, 1995,
canceling claims 1–45 and adding claims 46–90. Amendment 1,
3–16.
(2) Another preliminary amendment on June 12, 1998 (Amendment
2), adding claims 91–365. Amendment 2, App. A1–95.
(3) Yet another preliminary amendment on December 14, 1998
(Amendment 3), canceling claims 36–90 and adding claims 366–
442. Amendment 3, App. A3–A16.
(4) A Non-Final Office Action mailed October 6, 1999.
(5) An Amendment (Amendment 4) on May 5, 2000, amending many
claims. Amendment 4, App. A1–A93.
(6) Another Amendment on December 21, 2001 (Amendment 5),
canceling a few claims and amending other claims. Amendment 5,
App. A1–41.
(7) A Final Office Action mailed March 13, 2003.
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(8) Yet another Amendment on September 19, 2003 (Amendment 6),
substantially revising many claims. Amendment 6, App. A1–
A105.
(9) Another amendment on April 23, 2014 (Amendment 7),
substantially amending the pending claims. Amendment 7, App.
A1–186.
(10) Another amendment on June 20, 2016 (Amendment 8),
substantially amending the pending claims. Amendment 8, Att. 1,
pp. 1–309.
The above illustrates the growth in the number of claims was
significant between 1994 and 1998. For example, Appellant added over
forty-five claims in 1995. See Ans. 30 (noting the “claim proliferation,” in
which the initial claim set “included 45 total claims, 19 independent,” and
“[t]he preliminary amendment of 18 April 1995 cancelled the original 45
claims and replaced them with 45 total new claims, 17 independent”). Then,
in 1998, Appellant added about 350 claims. See Ans. 30–31 (“A second
preliminary amendment . . . added 275 claims, increasing the overall claim
count to 320 total claims, 97 independent. A third preliminary amendment
of 14 December 1998 appears to have cancelled the claims introduced in the
18 April 1995 preliminary amendment, while adding 77 new claims to
increase the overall claim count to 352 total claims, 97 independent.”). At
this point, about eighteen years had transpired since the great-grandparent
application had been filed. In fact, although Appellant states “[t]he
amendments to the claims [made in 1998] are proposed in order to more
particularly point out the Applicant’s invention” (Amendment 2, 1),
Amendment 2 and 3 increased the number (and repetition) of the claims
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almost seven-fold about three years after Appellant stated he agreed to focus
the claims better in 1995.
Additionally, when considering the related applications, the Examiner
further indicates that “[t]he total number of claims ballooned to
approximately 115,000, with 3,273 claims drawn to the same specification in
this family.” Ans. 19. This “balloon[ing]” of the number of “claims drawn
to the same specification” and adding about 400 new claims over the course
of nearly three years, after agreeing to focus the claims better in each
application in 1995, provides further evidence of delayed prosecution. Id.;
see also id. at 44 (discussing the “400 applications with 115,000+ claims”
and “the totality of the circumstances in these applications . . . contributed to
the unreasonable and unexplained delay of this application”).
A restriction requirement was mailed April 6, 1999, and Appellant
elected without traverse on May 6, 1999, to pursue a certain invention. On
June 12, 2000, the application went abandoned. The abandonment was
rescinded in 2001, and a Final Office Action was mailed in 2003.
The scope of many claims changed dramatically in September 2003.
For example, claim 95 change from a dependent system claim to an
independent process claim with many new recitations to analog information
and memory cells of integrated circuit random access memory. See
Amendment 6, App. A2–A3. Other examples of significant changes exist,
including claims 101 (amending from a process for making a product to a
process of generating, writing, and storing analog input information and
generating output information), 107–08, 113–14, 119, 144 (amending from a
dependent system claim having multibit nonvolatile memory cells storing
digital bits of information as electrical charge to an independent process
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claim for storing analog information and generating output information), 156
(amending from a dependent system claim having multibit nonvolatile
memory cells storing digital bits of information as electrical charge to an
independent process claim for generating, writing, and storing computer
instruction), 178, and 272. See id. at A4, A6–10, A18, A24–25, A34, and
A64. That is, eight years after Appellant agreed to work diligently and to
file an amendment having focused claims, Appellant changed the focus of
many claims, providing evidence that Appellant postponed or delayed in
claiming the actual subject of this invention for years.
On November 17, 2003, Appellant submitted an Amendment Under
Transitional After-Final Practice, requesting reopening of prosecution.
On March 21, 2006, the Office issued a Requirement for Information,
requesting to agree or disagree with the priority under 35 U.S.C. § 120
represented in Exhibit A.19
Prosecution was suspended on April 17, 2007.
On October 23, 2013, the Requirement to select a reasonable number
of claims in this application was mailed. Requirement 2 (first), 4 (first), 35.
The Requirement also provided numerous examples of claims “with no
appreciable line of patentable distinction” between the related 10
applications. Id. at 10–31 (discussing claims in various applications,
including U.S. Application Nos. 08/285,669, 08/428,737, 08/429,272,

19 Exhibit A indicated that this application is a continuation of U.S.
Application Nos. 08/254,818 and 07/493,061. Exhibit A further indicated
that U.S. Application Nos. 08/254,818 claims continuity to U.S. Application
07/495,808, which is a continuation of U.S. Application No. 06/520,277,
which is a divisional of U.S. Application No. 06/160,871, filed June 19,
1980. March 21, 2006 Requirement, Ex. A.
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08/433,307, 08/435,502, 08/469,061, and 08/471,214). The Requirement
also warned Appellant of the “extraordinary” claim growth (id. at 3 (first))
and that the Office “has also been unable to develop a clear prosecution
record that accurately notifies the public as to Applicant’s invention” (id. at
4 (first)).
On April 23, 2014, Appellant responded, traversing the Requirement
and requesting entry of an August 28, 2013 amendment, which was found
non-compliant on September 13, 2013. Response to the 37 C.F.R. 1.105
Office Action 1, 3; Request to Enter the Previously Filed Amendments to the
Disclosure 1. Under protest,20 Appellant selected claims 91, 95, 97, 101,
103, 109, 113, 115, 118, 119, 121, 124, 125, 127, 130, 131, 133, 136, 137,
139–151, 153–163, 165–167, 169–171, 173–175, 177–179, 181–183, 185–
189, 192, 193, 197, 198, 203, 204, 208, 209, 212, 213, 216, 217, 222, 223,
226, 227, 230, 231, 235, 236, 240, 241, 246, 247, 250, 251, 256, 257, 260,
261, 265, 266, 269, 270, 274, 275, 279, 280, 283, 284, 287, 288, 291, 292,
296, 297, 300, 304, 308, 312, 316, 320, 324, 328, 332, 336, 340, 345, 349,
361–363, 365, 366–368, 370, 371, and 374–442. Response to the 37 C.F.R.
1.105 Office Action 3. “The 23 April 2014 rewrite of the claims generally
altered the scope of the invention by focusing the independent claims on the
correction of analog signal degradation within a computing system.” Ans.
23; see also Amendment 7, App. A1–186.

20 Appellant petitioned for supervisory review and withdrawal of the
Requirement on December 23, 2013, and May 12, 2014. The petitions were
dismissed on April 1, 2014, and denied on December 16, 2014 respectively.
As previous noted, the Federal Circuit found our rules justified the
Requirement. Hyatt v. USPTO, 797 F.3d at 1384.

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A Non-Final Office Action was mailed October 30, 2015 and
December 16, 2015 (restarting the period for response), presenting double
patenting rejections based on claim 48 found in U.S. Application No.
07/493,061. An undue multiplicity rejection was also presented.
On June 20, 2016, Appellant submitted a claim amendment
(Amendment 8), nearly rewriting the pending claims and canceling some
pending claims. Amendment 8, Att. 1, pp. 1–309; see also Ans. 23 (“In
response to the 23 October 2013 Requirement and the 16 December 2015
Office action, Appellant made amendments that completely rewrote nearly
every one of his pending claims”), 25 (“Appellant completely rewrote nearly
every claim and included claims directed towards new or divergent subject
matter with respect to the prior version of the claims”).
As the Examiner states,
Subsequent to the 16 December 2015 Non-Final Office action,
Appellant once again rewrote nearly every one of the pending
claims, moving the subject matter away from the problem of
analog signal degradation and focusing on what appears to be a
general purpose integrated circuit computer (claims set of 20
June 2016). Fully two decades after Appellant agreed to “better
[focus] the claims on a different invention in each application in
order to simplify examination” (Appellant’s Appendix F(II) at
12), Appellant’s alteration of the subject matter in this
application from a digital computer to a computer system
correcting analog signal degradation to an integrated circuit
computing system illustrates a distinct lack of focus; instead of
narrowing the scope of the claims over time, Appellant flip-
flops between broad concepts with each rewrite.

Ans. 23–24, 25 (noting Appellant rewrote nearly every claim between “23
April 2014 and 20 June 2016” “towards new or divergent subject matter
with respect to the prior version of the claims”).
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For example, claim 91 was amended from a process for generating
information, writing and storing an analog signal into memory bits,
correcting degradation of the signal, and generating output information to a
system that has integrated circuit charge storage memories to store
information (including computer instructions), a scratch pad memory to
store information, a data processor, and an output circuit. Amendment 8,
Att. 1, pp. 1. As another example, claim 97 changed from a process claim
for re-establishing the amplitude of an analog signal to a system claim
similar to claim 91 with the addition of computer main memory and a load
circuit for loading the computer instructions into the main memory. Id., Att.
1, pp. 5–6. Thus, about twenty years had transpired since Appellant
indicated to the Office an intent to focus and work diligently to generate
focused claims on different inventive features in each application (Appeal
Br., App. F15–16), Appellant continued to change the focus of the actual
invention in this application. See Ans. 42 (stating “to the extent that the
applications had not been appropriately differentiated through 2015, this is a
delay of . . . 20 years after the meeting with Director Godici in which
Appellant agreed to differentiate his applications with no explanation”).
A Non-Final Office Action was mailed December 30, 2016,
presenting double patenting rejections based on claim 215 found in U.S.
Application No. 08/470,879 and maintaining an undue multiplicity rejection.
A prosecution laches rejection was also presented. The Non-Final Office
Action further indicated warnings were made in various applications
between 2015 and 2016 related to his “system[atic] reworking of his claims
so late into prosecution” and that “his delay” was “unreasonable and
unjustified.” December 2016 Non-Final Act. 286; see id. at 286–88. As one
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example, specific warnings were provided in U.S. Application Nos.
08/435,502 on May 28, 2015 and 08/472,025 on October 2, 2015, both of
which are part of this family of applications. Id. at 287.
Appellant responded July 5, 2017. No claim amendments were
presented.
A Final Office Action was mailed August 16, 2017, maintaining the
double patenting rejection, the undue multiplicity rejection, and the
prosecution laches rejection.
An after-final Amendment was submitted on February 12, 2018
(Amendment 9), making changes to some pending claims. Amendment 9,
Att. 1, pp. 1–200. For example, claim 95 was amended from “based at least
in part on computer instructions stored in the charge storage elements” to
“based at least in part on computer instructions stored in the converter,” and
claim 130 was amended from “an off-line integrated circuit charge storage
memory” to “a first integrated circuit charge storage memory.” Id., Att. 1,
pp. 3, 22.
At the point when Amendment 9 was submitted, about thirty-eight
years had passed since the great-grandparent application had been filed; over
twenty years had passed since Appellant told the Office he would focus the
claims in each application in 1995; about three year had passed since
Appellant contends that, in 2015, he met with the Office “to improve
‘differentiation’ among applications” (Appeal Br. 27). See Ans. 42 (stating
“this is a delay of some 38 years after the asserted 1977 priority date and 20
years after the meeting with Director Godici in which Appellant agreed to
differentiate his applications with no explanation”). As noted previously,
“Appellant was thus made aware of a need to well-differentiate and better
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focus the claims of his applications at least as early as October 1995. Yet, in
subsequent filings over two decades after agreeing to differentiate his
claims, Appellant has failed to meaningfully provide demarcation.” Ans. 30.
Additionally, the Examiner further states:
The instant application was stated to be directed towards
“Correcting degradation and errors in a memory” on 16 June
2015. In a table dated 20 June 2016, the subject matter entry
was changed to “Solid state alternatives to magnetic disc
memories”. Entries on 9 June 2017 and 5 July 2017 listed the
instant application as being directed towards “Hybrid memory
systems having cache memory”, but subsequent entries on 25
September 2017 and 4 December 2017 list the instant
application as being directed back to “Solid state memory
alternatives to magnetic disc memories”. Once again, in entries
dated 8 January 2018 and 12 February 2018, Appellant reverted
the subject matter of the instant application to “Hybrid memory
systems having cache memory”. Finally, in entries since 20
August 2018, the subject matter of the instant application has
been stated as “Integrated circuit computers having hybrid
memories”. If we are to assume that each entry in a subject
matter table is representative of a delineated invention,
Appellant redirected the instant application to a new delineation
five times in a span of just over two years.

Ans. 38. Although not the claims, the title changes provide some evidence
that the subject matter of the actual invention in this application kept
changing and lacked focus over the years.
Thus, as explained above and below, the claim amendments, including
Amendment 9 submitted as late as 2018, show multiple attempts to refocus
the claimed subject matter without working diligently to improve
differentiation among the applications, resulting in unnecessary delays. See
id. at 42 (stating Appellant’s “behavior from 2015 to the present does not
demonstrate an action to improve differentiation”), 43 (“Completely deleting
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claim language and presenting what are effectively new claims nearly 40
years after the asserted priority date and 22 years after the instant filing date
is unreasonable and unexplained delay. Such amendment practice
demonstrates the same culpable neglect discussed in Symbol II above —
‘ignor[ing] the duty to claim his invention promptly’. Symbol II at
1156.”).21
Even at this point and while multiple amendments across the family
applications should have established meaningful differences, some claims in
the family applications remained without distinction. For example, the
Examiner indicates the similarities between this application and those of
U.S. Applications Nos. 08/436,552, 08/429,272, and 08/472,025 in 2019.
See Ans. 37 (noting each recites “charge storage memory” storing computer
instructions). Similarly, the double patenting rejection persisted in this
application between claim 215 of the U.S. Application No. 08/470,879 and
claim 95 of this application. See Final Act. 15–18. Significant overlapping
matter in the claims in this and other related applications does not
demonstrate Appellant’s attempts to focus the claims of this application
from other applications as far back as 1995. Also, repetitive refiling in
different applications can demonstrate a pattern of unjustifiably delayed
prosecution and may constitute laches. See Symbol Techs., 422 F.3d at
1385–86.
Amendment 9 was entered, and a Final Office Action was mailed
April 17, 2018.
Appellant filed a Notice of Appeal on August 20, 2018.

21 Symbol Techs., Inc. v. Lemelson Med., 422 F.3d 1378 (Fed. Cir. 2005).
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While on appeal, Appellant filed an Amendment on March 18, 2019
(Amendment 10), requesting cancellation of a number of claims, including
some of the selected claims. Amendment 10, pp. 2–218.
Amendment 10 was entered. First Advisory 1, box 3.
An Appeal Brief was filed March 22, 2019.
An Examiner Answer was mailed January 2, 2020.
Another after-final amendment was filed on July 2, 2020 (Amendment
11), requesting cancellation of more selected claims. Amendment 11, pp. 2–
32. This provides yet more evidence that Appellant delayed focusing the
claims.
Appellant provides insufficient explanation for the delay in rewriting
or focusing the claims. First, the 2018–2020 amendments were submitted
between four to six years respectively after the Requirement indicated that
several of Appellant’s applications, including the instant application, lack a
clear demarcation between their claims. See Requirement 10, 32. These
amendments also do not demonstrate Appellant’s intent in 1995 to submit
differentiating amendments “at the rate of five amendments per week for his
applications that were pending in group 2600.” Appeal Br., App. F16.
Second, although Appellant is permitted to present “new” claims (see
id. at 21–23), this does not negate the Office from presenting a rejection
based on prosecution laches when Appellant has an inadequate explanation
for the prolonged delays in claiming the instant subject matter. As an
example, Appellant indicated he “would diligently work to do as Director
Godici had suggested, that he would generate amendments that focused the
claims on different inventive features at the rate of five amendments per
week for his applications that were pending in group 2600” in 1995. See id.
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at App. F16. But, any purported improved claim differentiation of the
related applications did not transpire until about 20 years after this assertion.
The Examiner did not enter Amendment 11. Second Advisory 1,
box 4.
Reply Brief was filed July 8, 2020.
This brings us to where we are now. Appellant’s failure to improve
claim differentiation for so many years, resulted in delays (e.g., at least
twenty-five years since filing of this application and at least forty years since
the filing of the great-grandparent application) and unduly postponed the
time the public would be entitled to the free use of the invention. See Final
Act. 287–88 (quoting Woodbridge, 263 U.S. at 56); see also Ans. 45 (“the
prosecution laches rejection outlines numerous ways that Appellant, over
roughly the last 42 years since the asserted priority date of ancestor
application 05/844,765, delayed prosecution unreasonably and without
explanation”).
Based on the totality of circumstances, we find that Appellant’s
actions as well as inaction to differentiate the claims among the 10 related
applications as late as 2018 and 2020 results in an unreasonable delay in
prosecuting this application and demonstrates delays in focusing the claims
in the instant application and other applications for a prolonged time. See
Hyatt v. Hirshfeld, 998 F.3d at 1367 (stating “[t]he magnitude of Hyatt’s
delay in presenting his claims for prosecution suffices to invoke prosecution
laches”).
Appellant argues that the Office delayed in responding to his
submissions, including suspending prosecution and reopening prosecution
rather than addressing Appellant’s appeal, and other actions. See, e.g.,
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Appeal Br. 34–36, 41. Appellant contends these actions by the Office
“preclude[] equitable relief like laches.” Id. at 34. But, as the Examiner
indicates (Ans. 52), “a delay by the PTO cannot excuse the appellant’s own
delay.” Bogese, 303 F.3d at 1369; see also Ans. 48–49.
Moreover, although this application was suspended between 2007 and
2013, some of Appellant’s asserted delay on the part of the Office may be
considered to be attributed to Appellant’s own actions concerning his
proceedings within the courts. See Ans. 42 (“Appellant’s willingness to sue
the PTO in district courts is not evidence of his desire to advance
prosecution and avoid delay”); see also Appeal Br. 17 (discussing suits
within the federal courts), 26 (discussing “the Section 145 Actions”).
Furthermore, those suspensions were for the courts to resolve issues
common to Appellant’s applications and, regardless, nothing prevented
Appellant from filing, during that period, amendments to pursue the claims
that he now asserts are the claims he would like to patent.
Appellant argues that “there is no legal requirement that any applicant
must do ‘differentiation.’” Appeal Br. 27; see also id. at 28 (noting “[l]ack
of ‘differentiation,’ in any event, has absolutely nothing to do with
prosecution laches”). Yet, by failing to differentiate the claims in this
application from the other related applications as noted above, Appellant has
delayed in (1) claiming subject matter in this application over other
applications and (2) demonstrating what Appellant regards as his actual
invention in this application.
Moreover, the double patenting rejections presented as early as 2015
provided Appellant further notice that the Office regarded the claimed
subject matter in this application similar to those in other applications,
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further suggesting that Appellant was not differentiating the subject matter
in this application in a meaningful way from other applications many years
after filing this application and the great-grandparent application and after
agreeing to focus the claims in each application in 1995.
Appellant next contends the prosecution laches warning provided to
him in this application does not meet the requirements set forth in Bogese,
namely contending the rejection was not sufficiently specific. Appeal Br.
25, 32; see also Reply Br. 8. We are not persuaded. Bogese does not
require the specific warning Appellant contends is lacking in this application
(e.g., warning Appellant could not present new claims or define the quantity
or shifting nature that would be impermissible). See Bogese, 303 F.3d at
1364–65; see also Hyatt v. Hirshfeld, 998 F.3d at 1366 (“[p]rosecution
laches does not strictly require formalized notice, warnings, or office
actions, although those may well lend support to a prosecution laches
finding”); Ans. 44 (“[t]he requirement for a warning is not evident in cases
such as Woodbridge or Symbol Techs.; it appears to be fact-specific”).
Additionally, Appellant received multiple warnings (e.g., 50) in related
applications, including U.S. Application Nos. 08/435,502 and 08/472,025 as
early as October 2015. See Ans. 40 (noting “Appellant received warnings in
this family of applications in at least 08/435,502 (Notice of Non-Compliant
Amendment of 28 May 2015) and 08/472,025 (Notice of Non-Compliant
Amendment of 2 October 2015)”), 45 (“Appellant was provided warnings in
the instant family and across Appellant’s applications as a whole.
Specifically, Appellant was warned 50 times between 17 April 2015 and 28
July 2016.”).
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Moreover, the Requirement stated to Appellant that “[t]his
Requirement is necessary to resolve the problems that have stifled the
USPTO’s effective examination of the applications subject to this
Requirement, leading to delays in issuing patents to Applicant and hindered
development of a clear prosecution record for these applications.”
Requirement 2 (second) (emphasis added), 41 (“[i]n the absence of the
assistance required by this document, issuance of patents on Applicant’s
applications will be further delayed and the USPTO will be unable to
construct a clear public record defining Applicant's invention”). Thus,
contrary to Appellant’s contentions (see Appeal Br. 25), Appellant had been
warned about delays related to the prosecution of the claimed invention in
this and other applications by at least 2013.
Warnings against shifting the invention do not contradict other
requirements to improve differentiation among applications as argued. See
Ans. 27 (stating “[n]othing in Rule 129(a) contradicts this policy” of not
permitting shifting claims to another distinct invention after an Office action
on the merits). For example, Appellant could more readily focus the
claimed subject matter by further narrowing the claimed elements that
already exists in the claims without shifting the invention. Additionally, we
note that when prior art is presented that renders the claims novel or
obvious, a claim typically is amended to overcome that art, not totally shift
the subject matter to a different invention essentially requiring restart of
prosecution.
Regarding “shifting” and presenting “new” claims, Appellant further
discusses 37 C.F.R. § 1.129(a) (“Rule 129(a)”), arguing this provision
allows for amendments to claims. Appeal Br. 22–23 (citing Appendix G).
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The prosecution laches rejection presented in 2016 was not based on
Appellant’s submissions under Rule 129(a) but rather on the totality of
circumstances in prosecuting this and related applications. See Ans. 26
(“laches must consider a ‘totality of circumstances’”), 28 (“[f]ilings under 37
CFR 1.129 would then be continuations filed in series and still evaluated
under the totality of the circumstances”); see also id. at 27–28 (citing MPEP
§§ 706.07(h), 714.02, 819 (8th ed.)). We thus do not need to decide here
whether any single claim amendment was permissible under Rule 129(a).
Appellant argues that presenting “‘new’ claims . . . even after a
significant period of time, has never constituted prosecution laches,
regardless of circumstances.” Appeal Br. 21; see also Reply Br. 6–7. The
question, in considering the laches rejection, is whether Applicant’s repeated
submission of new claims, claim cancelations, and significant amendments
(legitimate or not) to the majority of pending claims over the course of many
years supports a finding that Applicant has unreasonably delayed the
prosecution of the application.
As explained above, we find the record does support such
unreasonable delay. See Ans. 43 (“The 23 April 2014 and 20 June 2016
claim amendments demonstrate Appellant’s habit of deleting the entire claim
body and inserting new claim language, often drawn to a new invention.
Completely deleting claim language and presenting what are effectively new
claims nearly 40 years after the asserted priority date and 22 years after the
instant filing date is unreasonable and unexplained delay. . . . A complete
rewrite of a claim so that it is drawn to a new invention is not a conventional
amendment . . . ; such amendments that shift to an entirely new invention do
not qualify as ‘reasonable amendments’.”), 48–49 (“Appellant completely
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rewrites claims with new language drawn to substantially different subject
matter, introducing effectively new claims 30 to 40 years after the asserted
filing date; such a strategy inevitably leads to a slowing of prosecution”), 50
(stating Appellant “persisting in shifting subject matter between applications
and families of applications over two decades after agreeing to focus and
delineate the claims of his applications”).
Appellant contends a prosecution laches rejection requires a showing
of prejudice and intervening rights. Appeal Br. 34 (citing Cancer Research
Tech. Ltd. v. Barr Labs., Inc., 625 F.3d 724, 728 (Fed. Cir. 2010)); Reply Br.
8–9. However, the Federal Circuit has held “an unreasonable and
unexplained prosecution delay of six years or more raises a presumption of
prejudice, including intervening rights.” Hyatt v. Hirshfeld, 998 F.3d at
1370; see also id. at 1366 (stating “[a]n applicant . . . but must also prosecute
its applications in an equitable way that avoids unreasonable, unexplained
delay that prejudices others”) (citing Cancer Research, 625 F.3d at 729). In
addition, “where a patent applicant has committed a clear abuse of the
PTO’s patent examination system, the applicant’s abuse and its effects meet
the prejudice requirement of prosecution laches.” Id. at 1370. Here, as
explained above, the unreasonable and unexplained delay by Hyatt exceeds
six years and Appellant has not met the burden to show that the delay “has
not caused the PTO or any third party material prejudice.” Id. at 1372.
In the Reply Brief, Appellant presents arguments related to the
Office’s purported “failure to examine this application” (Reply Br. 5; see,
e.g., id. at 5–6). These arguments are being raised and the evidence is being
presented for the first time and will not be considered. See 37 C.F.R.
§ 41.41(b)(2).
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The above history illustrates various examples, which cumulatively
amount to an unreasonable and unexplainable delay in prosecuting the
claimed invention in this application and can be viewed as putting off the
free public enjoyment of the invention, including: (1) not pursuing allowable
subject matter in the parent application (now abandoned) as earlier as 1990;
(2) waiting to pursue his self-described “much more than 10 inventions” for
almost fifteen years; (3) agreeing to focus the claims in this and the related
applications in 1995; (4) amending the claim in 1995 with a two-fold
increase in claims; (5) adding 350 more claims in 1998 by amendment,
which increased the claims another six-fold, including resulting in 97
independent claims; (6) substantially changing the scope of many claims in
2003; (7) receiving the Requirement in 2013, which indicated that there (a)
was no appreciable distinction between the 10 related applications and (b)
were delays in prosecution; (8) nearly rewriting all the claims in 2014; (9)
being provided a laches warning in 2015 and 2016 related to the delay to
pursue the inventions previously presented and selected for examination in
related applications in 2015 and in other applications prior to the laches
rejection in this application; (10) substantially rewriting the claims again in
2016, despite Appellant’s agreement with the Office over twenty years prior
to focus the claims in this and related applications in 1995; (11) amending
the claims in 2018, canceling some selected claims; and (12) attempting to
amend the claims in 2020 days prior to filing the Reply Brief, including
canceling some of the selected claims.
When considering the totality of the circumstances, including the
prosecution history of all of a series of related patents and the overall delay
in prosecuting the claimed invention, a rejection based on prosecution laches
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is appropriate. The above discussion demonstrates that the Office is not
relying just on the passage of time as Appellant asserts, but rather that this
application is an example of a rare case of unreasonable and unexplained
delay in prosecution supported by factual evidence.
As to any remaining arguments, we have considered Appellant’s
position but are not persuaded. We further adopt the Examiner’s response as
our own in this regard.
Thus, the totality of the circumstances, including the prosecution
history of this application and all of the related patents and the overall delay
in formulating claims, appropriately trigger laches. We therefore sustain the
rejection of the pending claims based on the doctrine of prosecution laches.
VI. DECISION SUMMARY
In summary:
Claim(s)
Rejected
35
U.S.C. §
Reference(s)/Basis Affirmed Reversed
95, 101,
109, 113,
118, 121,
125, 130,
136, 139,
141, 145,
151, 153,
157, 163,
167, 171,
174, 181,
187, 188,
193, 198,
203, 208,
209, 213,
217, 226,
230, 235,
240, 241,
112, ¶ 1 Written description 95, 101,
109, 113,
118, 121,
125, 130,
136, 139,
141, 145,
151, 153,
157, 163,
167, 171,
174, 181,
187, 188,
193, 198,
203, 208,
209, 213,
217, 226,
230, 235,
240, 241,

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247, 251,
256, 260,
266, 269,
275, 284,
288, 291,
296, 316,
328, 330,
336, 340,
365, 388,
399, 421
247, 251,
256, 260,
266, 269,
275, 284,
288, 291,
296, 316,
328, 330,
336, 340,
365, 388,
399, 421
95, 101,
109, 113,
118, 121,
125, 130,
136, 139,
141, 145,
151, 153,
157, 163,
167, 171,
174, 181,
187, 188,
193, 198,
203, 208,
209, 213,
217, 226,
230, 235,
240, 241,
247, 251,
256, 260,
266, 269,
275, 284,
288, 291,
296, 316,
328, 330,
336, 340,
365, 388,
399, 421
Provisional Non-
Statutory
Obviousness
Double Patenting
(U.S. Application
No. 08/470,879,
Levine, Rawlings)
95, 101,
109, 113,
118, 121,
125, 130,
136, 139,
141, 145,
151, 153,
157, 163,
167, 171,
174, 181,
187, 188,
193, 198,
203, 208,
209, 213,
217, 226,
230, 235,
240, 241,
247, 251,
256, 260,
266, 269,
275, 284,
288, 291,
296, 316,
328, 330,
336, 340,
365, 388,
399, 421

95, 101,
109, 113,
103 Levine, Morley,
Gilbert
95, 101,
109, 113,

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118, 121,
125, 136,
139, 141,
145, 151,
153, 163,
167, 174,
187, 193,
198, 203,
209, 213,
217, 226,
230, 235,
240, 241,
247, 251,
256, 260,
266, 269,
275, 284,
288, 291,
296, 316,
328, 336,
340, 365,
388, 399,
421
118, 121,
125, 136,
139, 141,
145, 151,
153, 163,
167, 174,
187, 193,
198, 203,
209, 213,
217, 226,
230, 235,
240, 241,
247, 251,
256, 260,
266, 269,
275, 284,
288, 291,
296, 316,
328, 336,
340, 365,
388, 399,
421
130, 157,
171, 181,
188, 208
103 Levine, Morley,
Gilbert, Lester
130, 157,
171, 181,
188, 208

330 103 Levine, Morley,
Gilbert, Ewanus,
Berg
330
95–103,
105, 108–
111, 113,
114, 118–
126, 129–
134, 136–
151, 153–
175, 178,
179, 181,
183, 186–
189, 192,
Indefiniteness
(Undue
multiplicity)
95–103,
105, 108–
111, 113,
114, 118–
126, 129–
134, 136–
151, 153–
175, 178,
179, 181,
183, 186–
189, 192,

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193, 196–
221, 223,
226–230,
234–245,
247, 249,
251, 252,
255–273,
275, 277–
286, 288,
291, 295–
352, 361–
363, 365–
368, 370,
372–399,
402–405,
408–411,
414–448
193, 196–
221, 223,
226–230,
234–245,
247, 249,
251, 252,
255–273,
275, 277–
286, 288,
291, 295–
352, 361–
363, 365–
368, 370,
372–399,
402–405,
408–411,
414–448
95–103,
105, 108–
111, 113,
114, 118–
126, 129–
134, 136–
151, 153–
175, 178,
179, 181,
183, 186–
189, 192,
193, 196–
221, 223,
226–230,
234–245,
247, 249,
251, 252,
255–273,
275, 277–
286, 288,
291, 295–
352, 361–
Prosecution laches 95–103,
105, 108–
111, 113,
114, 118–
126, 129–
134, 136–
151, 153–
175, 178,
179, 181,
183, 186–
189, 192,
193, 196–
221, 223,
226–230,
234–245,
247, 249,
251, 252,
255–273,
275, 277–
286, 288,
291, 295–
352, 361–

Appeal 2020-005348
Application 08/285,669

106
363, 365–
368, 370,
372–399,
402–405,
408–411,
414–448
363, 365–
368, 370,
372–399,
402–405,
408–411,
414–448
Overall
Outcome
95–103,
105, 108–
111, 113,
114, 118–
126, 129–
134, 136–
151, 153–
175, 178,
179, 181,
183, 186–
189, 192,
193, 196–
221, 223,
226–230,
234–245,
247, 249,
251, 252,
255–273,
275, 277–
286, 288,
291, 295–
352, 361–
363, 365–
368, 370,
372–399,
402–405,
408–411,
414–448

Appeal 2020-005348
Application 08/285,669

107
VII. TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED