Ex Parte Zuniga et al

Patent Trial and Appeal BoardApr 17, 2018

13572110 (P.T.A.B. Apr. 17, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/572,110 08/10/2012 143959 7590 04/19/2018 Lathrop Gage LLP I Maxim Integrated 2440 Junction Place Suite 300 Boulder, CO 80301 FIRST NAMED INVENTOR Marco A. Zuniga UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 555587 3501 EXAMINER HARGROVE, FREDERICK B ART UNIT PAPER NUMBER 2819 NOTIFICATION DATE DELIVERY MODE 04/19/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): patent@lathropgage.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MARCO A. ZUNIGA, YANG LU, BADREDIN FATEMIZADEH, JAYASIMHA PRASAD, AMIT PAUL, and JUN RUAN Appeal2017-005002 Application 13/572,110 1 Technology Center 2800 Before LINDA M. GAUDETTE, WESLEY B. DERRICK, and MICHAEL G. McMANUS, Administrative Patent Judges. DERRICK, Administrative Patent Judge. DECISION ON APPEAL 2 STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. Â§ 134 from the Examiner's maintained rejection under 35 U.S.C. Â§ 103(a) of (1) claims 1, 12, 17, and 18 1 Appellants identify Volterra Semiconductor LLC, a subsidiary of Maxim Integrated Products, Inc., as the real party in interest. Appeal Br. 3. 2 We refer to the Specification filed August 10, 2012 ("Spec."), the Final Office Action issued August 21, 2015 ("Final Act."), the Advisory Action issued November 18, 2015 ("Adv. Act."), the Appeal Brief filed July 20, 2016 ("Appeal Br."), the Examiner's Answer issued December 1, 2016 ("Ans."), and the Reply Brief filed February 1, 2017 ("Reply Br."). Appeal2017-005002 Application 13/572,110 over You3 and Hsieh,4 (2) claims 2, 3, and 13-16 over You, Hsieh, and Denison, 5 and (3) claims 4--11 over You, Hsieh, and Wilson. 6 We have jurisdiction under 35 U.S.C. Â§ 6. We reverse. THE INVENTION The subject matter of the claims on appeal relates to a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, a source region, and a drain region. Spec. Abstract. Claim I-the sole independent claim-is representative. 1. A transistor comprising: an n-well region implanted into a surface of a substrate; a gate region; a source region on a first side of the gate region, the source region comprising a p-body region in the n-well region wherein an n+ region and a p+ region are implanted in the p-body region such that the n+ region is stacked on the p+ region in a depthwise direction, the p+ region extending deeper into the p-body region than then+ region; and a drain region on a second side of the gate region, the drain region comprising (a) an n-doped shallow drain extending from the surface of the substrate into the n-well region and (b) an n+ region embedded within the n-doped shallow drain and extending from the top surface of the substrate into the n-doped shallow drain, the n-doped shallow drain extending deeper into the n- well region than the n+ region of the drain region. Appeal Br. 10. 3 You et al., US 2005/0106791 Al, published May 19, 2005. 4 Hsieh, US 2012/0161201 Al, published June 28, 2012. 5 Denison et al., US 2009/0256212 Al, published October 15, 2009. 6 Wilson et al., US 2009/0273026 Al, published November 5, 2009. 2 Appeal2017-005002 Application 13/572,110 DISCUSSION We are persuaded that the Examiner has failed to meet the Office's burden of establishing the unpatentability of the claims. For any ground of rejection, "the [E]xaminer bears the initial burden ... of presenting a prima facie case ofunpatentability." In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992). We add the following. Claim 1 requires, inter alia, that the source region of a gate includes a p-body region in an n-well region and that the p-body region has implanted into it an n+ region and a p+ region with the implanted n+ region stacked on the implanted p+ region such that the p+ region extends deeper into the p- body region than the n+ region. The Examiner relies on You's Figure 5 as substantially disclosing the claimed invention. Final Act. 3. Figure 5A of You is reproduced below: \ ' 506Â·~ 514, \~ .................... - I FIG,, ..... 5A 1Â·510 I I ,, 512: t ( ! j:MHJbstrate Figure 5A depicts a schematic cross-sectional view of a lateral double- diffused MOSFET (LDMOS) transistor. You ifif l, 26, Fig. 5A. The Examiner finds that "You differs from the claimed invention because he fails to disclose then+ region [526] is stacked on the p+ region [528] in a depth 3 Appeal2017-005002 Application 13/572,110 wise direction, the p+ region [528] extending deeper into the p-body [530] region than then+ region [526]." Final Act. 3. The Examiner relies on Hsieh, Figure 3, as disclosing a source region having an n+ region 307 stacked on a p+ region 306 in a depth wise direction, the p+ region 306 extending deeper into a p-body region 304 than then+ region 307. Final Act. 3 (citing Hsieh, Fig. 3). Figure 3 of Hsieh is reproduced below: / 300 (~- 312 Â·3:2k-~~ .... -=:>-N~----- ~-~~ I P- 301 I L..,.____ ---Â· â€¢ Â·-' .FIG.3 Figure 3 depicts a cross sectional view of a lateral insulated gate bipolar transistor (LIGBT). Hsieh, Abstract, i-f 19, Fig. 3. The Examiner concludes that "it would have been obvious to one of ordinary skill in the art to modify the device of You to have the source region having a [sic] n+ region is [sic] stacked on the p+ region in a depth wise direction, the p+ region extending deeper into the p-body region than 4 Appeal2017-005002 Application 13/572,110 the n+ region because it provides a fast switching gate bipolar transistor with higher breakdown voltage and lower on-resistance as well as higher switching speed (see Hsieh, Figure 3)." Final Act. 3. The Examiner elaborates in the Advisory Action that Hsieh discloses improving its transistor by providing "a source and drain trenched contact and stacking the N+ region on the p+ region in a depth wise direction" and that "[i]mproving the source and drain to a trenched contact reduces the contact resistance with the source and drain region ... [and] reduces the triggered voltage to a value of 0.7V which improves the switching speed of the transistor." Adv. Act. 2 (citing Hsieh, Figs. 1-3). As to the fact that "Hsieh modifies both the source and drain regions [of transistors depicted in Figures 1 & 2] ... to have the stacked N+ and P+ region," the Examiner concludes that "[i]t would be obvious that if the drain region (313 of Figure 3) promotes high breakdown voltage, low on-resistance, and high switching speed then the stacking of the N+ and P+ region of the source region (311 of Figure 3) would also promote the same improvement." Adv. Act. 2 (emphasis omitted). The Examiner further elaborates in the Answer that "Hsieh teaches the stack[ed] N+ and P+ region with a trenched contact in the source and drain region provides higher breakdown voltage and lower on-resistance." Ans. 2 (citing Hsieh i-f 1 ). The Examiner reasons that "[ s ]ince Hsieh is modifying both the source and drain region from the prior art figures [Figs. IA & IB], it would be evident ... adding trench contacts to both the source and the drain are related aspects of the invention of Hsieh and that any improvement to the drain would also be an improvement to the source." Ans. 2; see also id. at 3--4 (citing Hsieh i-f 28). 5 Appeal2017-005002 Application 13/572,110 Finally, the Examiner clarifies his position, stating that the "Examiner is teaching that modifying You's source region with the entire source region of Hsieh (including the trenched contact) would provide higher breakdown voltage, lower on-resistance and reduce the contact resistance between the source metal 311 and the P body region 304." Ans. 3 (citing Hsieh i-f 28, Fig. 3); see also id. at 3--4 (explaining that "the whole source region of You ... is completely replaced by Hsieh's source region."). Appellants contend that the Examiner's articulated rationale to modify You is deficient. Proffered arguments focus on Hsieh as teaching the modification of a drain region to overcome a deficiency in a different type of transistor rather than any modification to the source region, and particularly to the source region of an LDMOS transistor, such as that in You. See generally Appeal Br. 4--7. As to the source region, the modification made in Hsieh is not an improvement made to a structure as depicted in You, but rather to include a trench contact to, effectively, an already stacked source region, with other apparent differences as to how that stacked source region is formed. Compare Hsieh, Figs. 1 & 2, with Fig. 3, and compare Hsieh, Fig. 3, with You, Fig. 5. See also Reply Br. 2. The Examiner nonetheless maintains that "stacking N+ and P+ regions with the trenched contact reduces contact resistance ... due to the trenched contact." Ans. 2 (citing Hsieh i-f 28). Further, the Examiner fails to adequately explain how paragraph 28 supports stacking an N+ region on a P+ region where it is a further P doped region 304 placed between P+ region 306 and first P body region 305 that is cited as "reduc[ing] contact resistance between the source (cathode) metal 311 and the second P body region 304." Hsieh i-f 28; see also Reply Br. 2-3. 6 Appeal2017-005002 Application 13/572,110 As to modifying the source region of You, the Examiner's further reasoning that Hsieh's invention relates to both the source and drain region, despite its focus on the drain region, such that "it would have been obvious to [also] incorporate the source modification ... for the overall disclosed improvements of higher breakdown voltage and lower on-resistance" (Ans. 3) is lacking. As highlighted by Appellants' arguments, the Examiner has failed to provide a sufficient explanation to account for apparent differences between the device of You and those of Hsieh, including the prior art devices in Figures IA and IB. See generally Final Act.; Advisory Act.; Ans. Further, despite Hsieh's focus on modification of the drain region by adding an n+ region, and stacking the n+ region on a p+ region, the relied on combination lacks such a drain region, and there is no sufficient explanation provided why one of ordinary skill in the art would reasonably expect a transistor with higher switching speed absent Hsieh's drain region. Final Act. 3; Ans. 4. In the Answer, the Examiner addresses various arguments as not persuasive because "[ r ]educing the contact resistance due to the trenched contact is a secondary rationale" (Ans. 3) and because the [h ]igher switching speed taught by Hsieh is [a] secondary motivation" (id. at 4). This leaves, then, the Examiner relying on lower on-resistance as the primary motivation for the combination. The Examiner fails, however, to provide a sufficient explanation how, or if, modifying the source region of You as set forth in the combination would lower the on-resistance of You' s device. See generally Final Act.; Advisory Act.; Ans. In sum, there is no sufficient cogent articulated rationale supported by evidence why one of ordinary skill in the art would have modified the device 7 Appeal2017-005002 Application 13/572,110 in You to include, as its source region, the drain region structure ofHsieh's device. "[O]bviousness concerns whether a skilled artisan not only could have made but would have been motivated to make the combinations or modifications of prior art to arrive at the claimed invention." Belden Inc. v. Berk-TekLLC, 805 F.3d 1064, 1073 (Fed. Cir. 2015). On this record, accordingly, the Examiner's articulated reasoning falls short of that necessary for a prima facie case. See In re Warner, 379 F.2d 1011, 1017 (CCP A 1967) ("The Patent Office has the initial duty of supplying the factual basis for its rejection. It may not ... resort to speculation, unfounded assumptions or hindsight reconstruction to supply deficiencies in its factual basis."); In re Sporck, 301 F.2d 686, 690 (CCPA 1962); see also Oetiker, 977 F.2d at 1445. We decline to scour the record in the first instance for facts that might support a prior art rejection of the claims on appeal, as our primary role is review, not examination de nova. DECISION The Examiner's decision rejecting claims 1-18 is REVERSED. REVERSED 8