Ex Parte Zhang et al

Patent Trial and Appeal Board

Jan 8, 2019

15213529 (P.T.A.B. Jan. 8, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
15/213,529 07/19/2016 Chi Zhang
133964 7590 01/10/2019
HOFFMAN WARNICK LLC
540 Broadway
4th Floor
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
HAUS003-US-NP 1086
EXAMINER
CHEN,SIBIN
ALBANY, NY 12207 ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
01/10/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOCommunications@hoffmanwarnick.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHI ZHANG and ARUL BALASUBRAMANIY AN
Appeal2018-005042
Application 15/213,529
Technology Center 2800
Before BEYERL YA. FRANKLIN, LINDA M. GAUDETTE, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
CASHION, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-3, 5-10, 12-18, and 20-22. We have jurisdiction under 35 U.S.C.
§ 6(b ).
We AFFIRM-IN-PART.
Appeal2018-005042
Application 15/213,529
The invention is generally directed to a switched capacity circuit
having a switching transistor that includes a fully depleted semiconductor on
insulator (FDSOI) channel region positioned laterally between the source
terminal and the drain terminal that provides an additional terminal for
controlling the voltage of a region proximal to the channel region of the
transistor. Spec. ,r 17.
Claim 1 is illustrative of the claimed subject matter on appeal and is
reproduced below:
1. A switched capacitor circuit structure comprising:
a switching transistor including a gate terminal, a source
terminal, and a drain terminal, wherein the switching transistor
further includes:
a fully depleted semiconductor on insulator (FDSOI)
channel region positioned laterally between the source terminal
and the drain terminal,
a buried insulator layer positioned directly beneath the
FDSOI channel region, and
a back gate terminal including n type semiconductor
separated from the channel region of the switching transistor by
the buried insulator layer;
a biasing node coupled to the back-gate terminal of the
switching transistor, the biasing node being alternately
selectable between an on state and an off state;
a first capacitor coupled to the source of the switching
transistor;
a second capacitor coupled to the drain of the switching
transistor; and
a first enabling node coupled to the gate of the switching
transistor, the first enabling node being alternately selectable
between an on state and an off state.
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Appeal2018-005042
Application 15/213,529
Appellant1 (see generally Appeal Brief) requests review of the
following rejections from the Examiner's Final Office Action:
I. Claim 21 rejected under 35 U.S.C. § 112(b) as being indefinite for
failing to particularly point out and distinctly claim the subject matter which
the inventor or a joint inventor regards as the invention.
II. Claims 1, 5-8, 16-18, and 20 rejected under 35 U.S.C. § 103 as
unpatentable over Staszewski (US 2014/0320215 Al, published October 30,
2014), Chan (US 5,706,226, issued January 6, 1998), and Kawahara (US
2007 /0063284 Al, published March 22, 2007).
III. Claims 2, 3, 9, 10, 12-15, 21, and 22 rejected under 35 U.S.C. § 103
as unpatentable over Staszewski, Chan, Kawahara, and Nowak (US
2008/0122519 Al, published May 29, 2008).
OPINION
Rejection I (claim 21 under 35 USC§ l 12(b))
Appellant presented no substantive arguments with respect to the
rejection of claim 21 under 35 U.S.C. § 112(b). See App. Br. 13 and Reply
Br. 8. Instead, Appellant reserves the right to address this rejection with a
claim amendment after one or more claims has been indicated as otherwise
being allowable. Reply Br. 8.
Accordingly, we summarily affirm the Examiner's rejection of claim
21 under 35 U.S.C. § 112(b).
1 Global Foundries, Inc. is the Applicant/ Appellant. Appellant does not
identify a real party in interest. Therefore, we assume the real parties in
interest are the inventors. 37 C.F.R. § 4I.37(c)(i).
3
Appeal2018-005042
Application 15/213,529
Rejection II (claim 1 under 35 US.C. § 103)2
After review of the respective positions provided by Appellant and the
Examiner, we reverse the Examiner's prior art rejection of claims 1, 5-8,
16-18, and 20 under 35 U.S.C. § 103 for the reasons presented by Appellant
and add the following.
The Examiner finds that the combined teachings of Staszewski and
Chan teach a switched capacitor circuit structure that differs from the
claimed invention in that the aforementioned combined teachings do not
teach a switching transistor having a fully depleted semiconductor on
insulation (FDSOI). Final Act. 3--4. The Examiner finds Kawahara teaches
a switching transistor with the claimed FDSOI. Final Act. 4; Kawahara
Figure 3. The Examiner determines that it would have been obvious to the
ordinary artisan to modify Staszewski' s switched capacitor circuit by
incorporating Kawahara's transistor because it is a suitable and well-known
type of switching transistor design. Final Act. 4.
Appellant argues that the Examiner has not adequately explained how
one skilled in the art would modify Staszewski' s switched capacitor circuit
to incorporate Kawahara's switching transistor to arrive at the claimed
invention. App. Br. 6. According to Appellant, Kawahara generally
suggests that an FDSOI transistor could suppress leakage current in
particular cases. Id. at 8. However, Appellant contends that, absent
impermissible hindsight, none of the cited references provide a sufficient
teaching or suggestion to create or adapt a "switched capacitor structure" as
2 Both independent claims 1 and 16 require a fully depleted semiconductor
on insulator (FDSOI). Accordingly, we limit our discussion to independent
claim 1.
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Appeal2018-005042
Application 15/213,529
claimed with an FDSOI to account for varying operating conditions, and/or
adjust performance during or after manufacture. Id. at 7-8.
The weight of the evidence supports Appellant's position. The
premise of the Examiner's rejection is that one skilled in the art would have
modified Staszewski's switched capacitor circuit by using Kawahara's
switching transistor having an FDSOI in place of the one in Staszewski's
switched capacitor circuit because it is a suitable and well-known type of
switching transistor design. However, "[t]he mere fact that the prior art may
be modified in the manner suggested by the Examiner does not make the
modification obvious unless the prior art suggested the desirability of the
modification." In re Fritch, 972 F.2d 1260, 1266 (Fed. Cir. 1992). Further,
"rejections on obviousness ... cannot be sustained by mere conclusory
statements; instead, there must be some articulated reasoning with some
rational underpinning to support the legal conclusion of obviousness." KSR
Int'! Co. v. Teleflex Inc., 550 U.S. 398,418 (2007) (quoting In re Kahn, 441
F.3d 977, 988 (Fed. Cir. 2006)).
Here, the Examiner has not provided the requisite articulated
reasoning to support a legal conclusion of obviousness. The Examiner has
not provided a technical analysis explaining why one skilled in the art would
have found Kawahara's transistor suitable for the purposes of Staszewski's
switched capacitor circuit: improve phase noise performance. Staszewski
Accordingly, we reverse the rejection of claims 1, 5-8, 16-18, and 20
under 35 U.S.C. § 103 as unpatentable over Staszewski, Chan, and
Kawahara for the reasons presented by Appellant and given above.
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Appeal2018-005042
Application 15/213,529
Rejection III (claim 9 under 35 US.C. § 103}3
After review of the respective positions provided by Appellant and the
Examiner, we reverse the Examiner's prior art rejection of claims 2, 3, 9, 10,
12-15, 21, and 22 under 35 U.S.C. § 103 for the reasons presented by
Appellant and add the following.
We refer to the Examiner's Final Action for a statement of the
rejection of independent claim 9. Final Act. 6.
The Examiner's prior art rejection of claim 9 is premised on the
teachings of Staszewski, Chan, and Kawahara rendering the subject matter
of independent claim 1 obvious to one skilled in the art. See Final Act. 5---6.
As discussed above, such is not the case. The Examiner did not rely on the
additionally cited secondary reference to overcome the previously-noted
deficiencies of Staszewski, Chan, and Kawahara. Id.
Thus, given that the Examiner does not direct us to any portions of the
cited art that addresses the subject matter of claim 9, we reverse the rejection
of claims 2, 3, 9, 10, 12-15, 21, and 22 under 35 U.S.C. § 103 as
unpatentable over Staszewski, Chan, Kawahara, and Nowak for the reasons
presented by Appellant and given above.
ORDER
The Examiner's rejection of claim 21 under 35 U.S.C. § 112 (b) is
affirmed.
The Examiner's prior art rejections of claims 1-3, 5-10, 12-18, and
20-22 under 35 U.S.C. § 103 are reversed.
3 We limit our discussion to independent claim 9.
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Appeal2018-005042
Application 15/213,529
Because the affirmed rejection does not reach all the claims, our
decision is an affirmance-in-part.
TIME PERIOD
No time period for taking any subsequent action in connection with
this appeal maybe extended under 37 C.F.R. § 1.136(a)(l).
AFFIRMED-IN-PART
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