Ex Parte ZHANG et al

Patent Trial and Appeal BoardFeb 25, 2019

13481173 (P.T.A.B. Feb. 25, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/481,173 05/25/2012 102324 7590 02/27/2019 Artegis Law Group, LLP/NVIDIA 7710 Cherry Park Drive Suite T #104 Houston, TX 77095 FIRST NAMED INVENTOR Leilei ZHANG UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. NVDA/SC-11-0435-US 1 2675 EXAMINER JEAN BAPTISTE, WILNER ART UNIT PAPER NUMBER 2899 NOTIFICATION DATE DELIVERY MODE 02/27/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): kcruz@artegislaw.com ALGdocketing@artegislaw.com j matthews @artegislaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte LEILEI ZHANG and ZUHAIR BOKHAREY Appeal2018-003763 Application 13/481, 173 Technology Center 2800 Before TERRY J. OWENS, JEFFREY B. ROBERTSON, and JENNIFER R. GUPTA, Administrative Patent Judges. GUPTA, Administrative Patent Judge. DECISION ON APPEAL 1 Appellants2 appeal under 35 U.S.C. Â§ 134(a) from the Examiner's final decision rejecting claims 1-3, 5-7, and 15-22. We have jurisdiction under 35 U.S.C. Â§ 6(b ). We AFFIRM. 1 In this Decision, we refer to the Specification filed May 25, 2012 ("Spec."), the Final Office Action dated April 20, 2017 ("Final Act."), the Appeal Brief filed August 28, 2017 ("Appeal Br."), the Examiner's Answer dated December 20, 2017 ("Ans."), and the Reply Brief filed February 20, 2018 ("Reply Br."). 2 Appellants identify the real party in interest as NVIDIA Corporation. Appeal Br. 3. Appeal2018-003763 Application 13/481, 173 The subject matter of the claims on appeal relates to a packaging substrate with a via structure. Spec. ,r 1. Independent claim 1, reproduced below from the Claims Appendix with emphasis to highlight a key disputed limitation, is illustrative of the claims on appeal. 1. A packaging substrate comprising: a first layer that includes a first opening; a second layer that is formed on the first layer and includes a second opening; and a via structure comprising an electrically conductive layer deposited in the first opening and in the second opening, wherein the electrically conductive layer provides an interface-free electrically conductive path between the first layer and the second layer. Appeal Br. 13 (Claims App.) (emphasis added). Independent claim 15 is directed to a method of forming a packaging substrate and, like claim 1, includes the recitation "an interface-free conductive path between the first layer and the second layer." Id. at 14. DISCUSSION The Examiner maintains the rejection of claims 1-3, 5, 7, 15-19, 21 and 22 under pre-AIA 35 U.S.C. Â§ I03(a) as over Min (US 2006/0099803 Al, published May 11, 2006). Final Act. 3; Ans. 2. The Examiner also maintains the rejection of claims 6 and 20 under pre-AIA 35 U.S.C. Â§ I03(a) over Min in view ofKurita et al. (US 6,448,647 Bl, issued September 10, 2002) ("Kurita"). Final Act. 6; Ans. 2. Appellants argue the claims as a group, and do not present separate arguments for the patentability of separately rejected claims 6 and 20. See 2 Appeal2018-003763 Application 13/481, 173 Appeal Br. 9-11. We choose claim 1 as representative, and claims 2, 3, 5-7, and 15-22 will stand or fall with claim 1. 37 C.F.R. Â§ 4I.37(c)(l)(iv). After review of the cited evidence in light of Appellants' and the Examiner's opposing positions, we determine that Appellants have not identified reversible error in the Examiner's rejections. Accordingly, we affirm the rejections for the reasons set forth below, in the Final Office Action, and in the Examiner's Answer. The Examiner finds that Min's Figure 2 teaches a packaging substrate that meets all the limitations of claim 1 's packaging substrate. Final Act. 3 ( citing Min ,r 22, Fig. 2). Figure 2 of Min is reproduced below. FIG. 2 Figure 2 shows a magnified view of Min's package substrate located between a die and a base substrate (Min ,r 9). Specifically, the Examiner finds that Min's Figure 2 teaches via structures (250, 260) lined with electrically conductive materials (255, 265) 3 Appeal2018-003763 Application 13/481, 173 that extend through capacitor structures ( 140, 150), and a core substrate (160) (i.e., first and second layers). Final Act. 3 ( citing Min ,r 22, Fig. 2). Appellants argue that Min does not teach or suggest an electrically conductive layer that "provides an interface-free electrically conductive path between the first layer and the second layer." Appeal Br. 9-10. Appellants contend that although Min's Figure 2 depicts a packaging substrate that includes vias 250 and 260, it does not provide sufficient detail so as to determine the actual structure and configuration of the vias. Id. at 11. According to Appellants, the only diagram that shows details of the actual structure and configuration of vias in Min is the inset of Figure 2, which clearly shows stacked vias (285) having interfaces between the vias. Id. Appellants' argument is not persuasive of reversible error. Min's Figure 2 teaches a packaging substrate having vias 250 and 260 in which a conductive layer (255, 265) has been deposited. Min ,r 22, Fig. 2. Min further teaches that vias 250 and 260 extend through capacitor structure 140, core substrate 160, and capacitor structure 150. Based on the disclosure in Min's paragraph 22 and Figure 2, one of ordinary skill in the art would reasonably understand that Min teaches an electrically conductive layer that provides "an interface-free electrically conductive path between" a first layer (160) and a second layer (150). In re Preda, 401 F.2d 825, 826-27 (CCPA 1968) ("[I]n considering the disclosure of a reference, it is proper to take into account not only specific teachings of the reference but also the inferences which one skilled in the art would reasonably be expected to draw therefrom."). Appellants' contention that the main diagram in Min's Figure 2 not showing vias 285 between build-up layers 176, but the detailed inset 4 Appeal2018-003763 Application 13/481, 173 diagram of Min's Figure 2 showing stacked vias 285 exist between build-up layers 176 as well as interfaces between vias 285, is evidence that Min's Figure 2 does not teach vias 250 and 260 providing "an interface-free electrically conductive path between" a first layer and a second layer is not well-taken. Reply Br. 3--4. Because Min provides a detailed inset diagram to show stacked vias 285 exist between build-up layers 176, which is not apparent from the main diagram in Min's Figure 2, one would reasonably expect that Min would also provide an inset diagram with a magnified detailed view of vias 250 and 260 if there was a need to show further detail regarding those vias, for example, to show that vias 250 and 260 are stacked in a similar manner to vias 285. Given that Min provides a inset diagram regarding vias 285, but does not provide a similar inset diagram regarding vias 250 and 260, we are not persuaded that the Examiner reversibly erred in finding that Min teaches vias 250 and 260 provide "an interface-free electrically conductive path" between layer 160 (first layer) and layer 150 (second layer). We have carefully considered Appellants' arguments, but find them unpersuasive. Because Appellants have failed to identify reversible error, we sustain the rejections of claims 1-3, 5-7, and 15-22 under 35 U.S.C. Â§ 103(a). DECISION The rejections of claims 1-3, 5-7, and 15-22 are affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. Â§ 1.136(a). 5 Appeal2018-003763 Application 13/481, 173 AFFIRMED 6