Ex Parte ZEDLEWSKI et al

Patent Trial and Appeal BoardMar 11, 2019

13473534 (P.T.A.B. Mar. 11, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. 13/473,534 152606 7590 VMWare-OPW P.O. Box 4277 Seattle, WA 98194 FILING DATE FIRST NAMED INVENTOR 05/16/2012 John R. ZEDLEWSKI 03/11/2019 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. A050.C2 5927 EXAMINER AQUINO, WYNUEL S ART UNIT PAPER NUMBER 2199 MAIL DATE DELIVERY MODE 03/11/2019 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte JOHN ZEDLEWSKI and CARL A. WALDSPURGER Appeal2017-010840 Application 13/473,534 Technology Center 2100 Before THU A. DANG, JOHN A. EV ANS, and JOHN P. PINKERTON, Administrative Patent Judges. PINKERTON, Administrative Patent Judge. DECISION ON APPEAL Appellants 1 file this appeal under 35 U.S.C. Â§ 134(a) from the Examiner's Non-Final Rejection of claims 5-18, which constitute all of the claims pending in this application. Claims 1--4 are withdrawn. We have jurisdiction under 35 U.S.C. Â§ 6(b ). We reverse. 1 Appellants identify VMWARE, INC. as the real party in interest. App. Br. 1. Appeal2017-010840 Application 13/473,534 STATEMENT OF THE CASE Introduction Appellants' disclosed and claimed invention is generally described as follows: A thread scheduling mechanism is provided that flexibly enforces performance isolation of multiple threads to alleviate the effect of anti-cooperative execution behavior with respect to a shared resource, for example, hoarding a cache or pipeline, using the hardware capabilities of simultaneous multi-threaded (SMT) or multi-core processors. Given a plurality of threads running on at least two processors in at least one functional processor group, the occurrence of a rescheduling condition indicating anti-cooperative execution behavior is sensed, and, if present, at least one of the threads is rescheduled such that the first and second threads no longer execute in the same functional processor group at the same time. Abstract. 2 Claim 5 is illustrative and reproduced below: 5. A virtual-machine monitor, implemented as computer instructions encoded within a data-storage subcomponent of a physical computer system that includes one or more mass- storage devices, one or more electronic memories, and one or more physical processors, the virtual machine monitor compnsmg: an interface component that interfaces to hardware components of the computer system on behalf of the virtual- machine monitor and one or more virtual machines and provides a virtual hardware interface to the one or more virtual machines; 2 Our Decision refers to the Non-Final Office Action mailed Aug. 26, 2016 ("Non-Final Act."), Appellants' Appeal Brief filed Jan. 19, 2017 ("App. Br.") and Reply Brief filed Aug. 7, 2017 ("Reply Br."), the Examiner's Answer mailed June 2, 2017 ("Ans."), and the original Specification filed May 16, 2012 ("Spec."). 2 Appeal2017-010840 Application 13/473,534 a scheduler component that schedules execution of the virtual machines on logical processors that are each mapped to an execution thread executing on a physical-processor package, each physical-processor package supporting simultaneous execution of multiple execution threads; an activity sensor within the scheduler component that continuously monitors execution performance and execution characteristics of the virtual machines to detect non-optimal mapping of the logical processors to execution threads within physical-processor packages. Rejections on Appeal3 Claims 5-7, 10-14, 17, and 18 stand rejected under 35 U.S.C. Â§ I03(a) as being unpatentable over Barsness et al. (US 2004/0240933 Al; published Oct. 27, 2005) ("Barsness"), Uchishiba (US 2002/0016812 Al; published Feb. 7, 2002), and Plouffe et al. (US 2005/0120160 Al; published June 2, 2005) ("Plouffe"). Claims 8, 9, and 15 stand rejected under 35 U.S.C. Â§ I03(a) as being unpatentable over Barsness, Uchishiba, Plouffe, and Cota-Robles et al. (US 2003/0037089 Al; published Feb. 20, 2003) ("Cota-Robles"). 3 The Examiner finds that should claim 5 be determined to be allowable, claim 12 will be objected to under 37 C.F.R. Â§ 1.75 as being a substantial duplicate of claim 5. Non-Final Act. 3. The Examiner objects to claim 16 as being dependent upon a rejected base claim, but finds claim 16 would be allowable if rewritten in independent form, including all of the limitations of the base claim and any intervening claims. Id. The Examiner also objects to claim 16 because it recites "I5wherein" and should recite "15 wherein." Id. The Examiner's objections are not before us for review as part of the instant appeal. 3 Appeal2017-010840 Application 13/473,534 ANALYSIS Rejection of Claim 5 UnderÂ§ 103 (a) We have reviewed the Examiner's rejection of claim 5 in light of Appellants' arguments that the Examiner erred. See App. Br. 4--17. We have also reviewed the Examiner's response to Appellants' arguments (see Ans. 12-19), and Appellants' responsive arguments in the Reply Brief (see Reply Br. 2-8). As discussed below, we are persuaded by Appellants' argument that the Examiner erred in rejecting claim 5 because the Examiner has failed to show by a preponderance of the evidence that the combination of Barsness, Uchishiba, and Plouffe teaches or suggests all of the limitations of claim 5. Appellants argue that the Examiner failed to identify any teaching or "even the slightest of suggestions" in the combination of Barsness, Uchishiba, and Plouffe of the "scheduler component" or "activity sensor" limitations of claim 5. App. Br. 17. The "activity sensor" limitation, for example, recites "an activity sensor within the scheduler component that continuously monitors execution performance and execution characteristics of the virtual machines to detect non-optimal mapping of the logical processors to execution threads within physical-processor packages." The Examiner finds that Barsness and U chishiba both teach an "activity sensor." Ans. 12 (citing Barsness Fig. 1, partition monitor 150; Uchishiba Fig. 1, reserve resource assigning/collecting unit 30 ("resource unit"). The Examiner also finds that Barsness teaches that, upon a determination of processor degradation among Virtual Machines ("VMs"), as detected by a partition monitor, corrective actions may be performed. Id. (citing Barsness ,r,r 67----69). The Examiner further finds that Uchishiba 4 Appeal2017-010840 Application 13/473,534 teaches the resource unit receives information from the VMs to identify another form of degradation-resource shortages. Id. (citing Uchishiba ,r,r 45, 48, 52). Citing Figure 7, the Examiner then finds that Uchishiba teaches VMs executing "on logical processors that are each mapped to an execution thread." Id. 12-13 ("Fig. 7 depicts two VMs as logical partition 1 (VM 1) with logical processors 705 and 706 and logical partition 2 (VM 2) with logical processors 707 and 709. Fig. 7 further depicts each logical processors as 'mapped' to instruction processors (i.e.[,] 'execution thread"')); see also id. at 15 and 18 ("the instruction processor and execution thread are interpreted as being equivalent"). The Examiner also finds that the combination of Barsness and Uchishiba teaches an activity sensor within the scheduler component "that detects non-opti[ m Jal mapping of the logical processors threads (i.e. Uchishiba monitoring processor degradation thereby implementing corrective action upon logical processors." Id. at 13 (citing Uchishiba ,r,r 63---65, 78); see also id. at 14. We are persuaded by Appellants' arguments that the combination of Barsness and Uchishiba, as asserted by the Examiner, does not teach or suggest the "activity sensor" limitation of claim 5 for several reasons. First, as Appellants argue, and we agree, there is nothing in Figure 7 ofUchishiba, or its description, that teaches or suggests "execution threads within a processor ... [or] anything related to physical-processor packages that support hardware threads." App. Br. 13 (emphasis omitted); see also Reply Br. 4. Although we agree with the Examiner that Figure 7 ofUchishiba shows a mapping of physical computers to logical partitions, we agree with Appellants that the Examiner has not identified any portion of U chishiba that teaches or suggests "that Uchishiba's logical partitions, which contain 5 Appeal2017-010840 Application 13/473,534 logical instruction processors, have anything at all to do with hardware threads or that the physical instruction processors within the physical computer shown in Figure 7 ofUchishiba have anything at all to do with hardware threads." Reply Br. 4. Second, we are not persuaded by the Examiner's finding that the "instruction processor [ of U chishiba ]" and execution thread are "interpreted as being equivalent" because this finding is conclusory and unsupported. Ans. 18. Moreover, this finding is based on the Examiner's finding that "both instruction processor[ s] and execution threads perform the same function." Id. The Examiner, however, has not provided sufficient technical reasoning or evidence to support either of these findings. Third, we are not persuaded by the Examiner's finding that the combination of Barsness and Uchishiba teaches an activity sensor within the scheduler component "that detects non-opti[ m Jal mapping of the logical processors threads (i.e.[,] Uchishiba monitoring processor degradation thereby implementing corrective action upon logical processors." Ans. 13 (citing Uchishiba ,r,r 63---65, 78). Instead, we agree with Appellants that the portions of U chishiba cited by the Examiner do not teach or suggest detecting non-optimal mapping of logical processors to execution threads: Furthermore, the above quoted text is not, in any way, related to detecting non-optimal mapping of the logical processors to execution threads within physical-processor packages, as asserted by the Office, but is instead directed to assigning more processors to a logical partition when the logical partition is experiencing a deficiency in computational bandwidth. Allocating additional resources to logical partitions is completely unrelated to detecting non-optimal mapping of the logical processors to hardware threads, or execution threads, within physical-processor packages, which involves, in one example 6 Appeal2017-010840 Application 13/473,534 discussed in the current application, detecting anti-cooperative behavior among virtual machines, each mapped to a different hardware thread of a single processor. App. Br. 13-14. Accordingly, on this record, we are constrained to find the Examiner erred because the Examiner has not shown that the combination of Barsness, Uchishiba, and Plouffe teaches or suggests the "activity sensor" limitation as recited in claim 5, and as similarly recited in claim 12, by a preponderance of the evidence. See In re Caveney, 761 F.2d 671, 674 (Fed. Cir. 1985) (Examiner's burden of proving non-patentability is by a preponderance of the evidence). Thus, we do not sustain the Examiner's rejection of claims 1 and 12, and dependent claims 6-11 and 13-18, for obviousness under Â§ 103(a). DECISION We reverse the Examiner's decision rejecting claims 5-18 under 35 U.S.C. Â§ 103(a). REVERSED 7