Ex Parte Yeh et al

Patent Trial and Appeal BoardJul 31, 2014

12370276 (P.T.A.B. Jul. 31, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/370,276 02/12/2009 Matt Yeh 2008-0522 / 24061.1147 5413 42717 7590 07/28/2014 HAYNES AND BOONE, LLP IP Section 2323 Victory Avenue Suite 700 Dallas, TX 75219 EXAMINER ENAD, CHRISTINE A ART UNIT PAPER NUMBER 2823 MAIL DATE DELIVERY MODE 07/28/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE __________ BEFORE THE PATENT TRIAL AND APPEAL BOARD __________ Ex parte MATT YEH, FANG WEN TSAI, and CHI-CHUN CHEN __________ Appeal 2012-002270 Application 12/370,276 Technology Center 2800 ___________ Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and JAMES C. HOUSEL, Administrative Patent Judges. HANLON, Administrative Patent Judge. DECISION ON APPEAL A. STATEMENT OF THE CASE Matt Yeh, et al. (“Appellants”) appeal under 35 U.S.C. § 134 from a final rejection of claims 1-20, which are all of the pending claims. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. Claim 1 is representative of the subject matter on appeal and is reproduced below from the Claims Appendix of the Appeal Brief dated June 23, 2011 (“App. Br.”). The limitation at issue is italicized. 1. A method for making a semiconductor device, comprising: Appeal 2012-002270 Application 12/370,276 2 providing a semiconductor substrate having a first region and a second region; forming a first gate stack over the first region and a second gate stack over the second region, the first and second gate stacks each including a dummy gate electrode; removing the dummy gate electrodes from the first and second gate stacks, respectively, thereby forming trenches; forming a metal layer to partially fill the trenches; forming an oxide layer over the metal layer so that the trenches are completely filled; applying a first treatment to the oxide layer; forming a patterned photoresist layer on the oxide layer overlying the first region; applying a second treatment to the oxide layer overlying the second region such that the patterned photoresist layer protects the oxide layer overlying the first region from the second treatment; etching the oxide layer overlying the second region; etching the first metal layer overlying the second region; removing the patterned photoresist layer; and removing the oxide layer overlying the first region. App. Br. 26. Claims 16 and 18 are the other independent claims on appeal. They also recite a method for making a semiconductor device. Similar to claim 1, claims 16 and 18 recite, inter alia, removing a dummy gate electrode from first and second gate structures, thereby forming gate trenches; forming a metal layer to partially fill the gate Appeal 2012-002270 Application 12/370,276 3 trenches; and forming an oxide layer or a hard mask layer, respectively, over the metal layer “to completely fill the gate trenches.” App. Br. 28-29 (emphasis added). The claims on appeal stand rejected as follows: claims 1, 8, 10- 16 under 35 U.S.C. § 103(a) as unpatentable over the combination of Akasaka1 and Takahashi2; claims 2-5, 9, and 17 under 35 U.S.C. § 103(a) § 103(a) as unpatentable over the combination of Akasaka, Takahashi, and Mosden3; claim 6 under 35 U.S.C. § 103(a) as unpatentable over the combination of Akasaka, Takahashi, and Tsai4; claims 7 under 35 U.S.C. § 103(a) as unpatentable over the combination of Akasaka, Takahashi, and Cho5 or Kloster6; claims 18- 20 under 35 U.S.C. § 103(a) as unpatentable over the combination of Akasaka, Mosden, and Park.7 B. ISSUE The dispositive issue on appeal is: Did the Examiner reversibly err in finding that Akasaka discloses forming an oxide layer or a hard mask layer over a metal layer to completely fill trenches formed by removing dummy gate electrodes as recited in claims 1, 16, and 18. 1 US 2007/0066077 A1, published March 22, 2007. 2 US 2010/0155844 A1, published June 24, 2010. 3 US 2005/0208434 A1, published September 22, 2005. 4 US 6,878,646 B1, issued April 12, 2005. 5 US 2007/0269979 A1, published November 22, 2007. 6 US 2004/0214427 A1, published October 28, 2004. 7 US 2009/0101993 A1, published April 23, 2009. A A se d th th m T to re o A 8 ppeal 201 pplication C. The E miconduc ummy gat ereby form e trenches etal layer he Examin the oxide cited in cl Akas xide layer kasaka ¶ 7 A The A Examiner 2-002270 12/370,27 DISCUS xaminer f tor device e electrode ing trenc ; and form 316 thereb er finds th layer reci aim 18. A aka Figure 317 depos 8. kasaka Fi ppellants ’s Answer 6 SION inds Akas comprisin s from firs hes 314; fo ing oxide y filling a at dielectr ted in claim ns. 6-7, 8- 20, repro ited on co g. 20 depic in the dis argue: dated Sept 4 aka disclo g, inter al t and seco rming me layer or h remaining ic film or s 1 and 1 9, 13.8 duced belo nductive fi ts a sectio closed me ember 14, ses a meth ia, the step nd gate st tal layer 3 ard mask l portion o oxide laye 6 and the w, shows lm or met nal view o thod. 2011. od for mak s of remo acks, respe 16 to parti ayer 317 o f the trenc r 317 corr hard mask dielectric al layer 31 f a step ing a ving ctively, ally fill ver hes. esponds layer film or 6. A A A il p d ppeal 201 pplication Akas silico depo subst “[A]s trenc comp diele para. FIG. nume portio filled film 3 (emp pp. Br. 13 The A lustrated in ortion of tr ielectric fi A The A 2-002270 12/370,27 aka clearly n-containi sited on th rate.” Aka shown in h portions letely fill ctric film 3 [0078] (em 20,” there rals 301A ns) of rec by the de 17 all ove hasis adde . ppellants Akasaka enches 31 lm or oxid kasaka Fi ppellants 6 states tha ng dielectr e conducti saka, para FIG. 20,” 314 (comp ed by the d 17 all ove phasis ad is clearly and 301B ess portion position of r the subs d). also argue Figure 21 4 are not c e layer 31 g. 21 depic in the dis argue: 5 t “. . . as s ic (insulat ve film 31 . [0078] (e Akasaka are Figs. eposition r the subst ded). Inst a portion ( in Fig. 20 s 314 that silicon-co trate. Aka that the s (reproduc ompletely 7. App. B ts a sectio closed me hown in F ing film) 6 all over mphasis a clearly dis 19 and 20) of silicon- rate. See ead, “as s e.g. refere identify th are not c ntaining d saka, para ubsequent ed below) filled by t r. 14. nal view o thod. IG. 20, a [317] is the dded). closes tha are not containing Akasaka, hown in nce ese ompletely ielectric . [0078] processin , confirms he deposi f a step t g step, that a tion of Appeal 2012-002270 Application 12/370,276 6 As can clearly be seen above in Fig. 21, the photo-resist mask 318 is formed in the portion identified by reference numeral 301A in Fig. 20 of recess portion 314 that was not completely filled by the deposition of silicon- containing dielectric film 317 all over the substrate. Moreover, as can clearly be seen above in Fig. 21 the portion identified by reference numeral 301B in Fig. 20 is still not completely filled by the deposition of silicon- containing dielectric film 317 all over the substrate. App. Br. 14. The Appellants make similar arguments with respect to independent claims 16 and 18. See App. Br. 17, 20-21. Referring to paragraphs 78 and 79 of Akasaka, the Examiner finds that dielectric film 317 “is deposited all over the substrate using CVD.” Ans. 16. The Examiner finds: CVD is a process of depositing a solid continuous film on a wafer or substrate surface through chemical reaction of a gas mixture. In Akasaka’s disclosure, a mask was not utilized during the process of CVD deposition and therefore the film is applied to the entire surface of the substrate and the deposition of the film cannot be preselected. . . . Furthermore, the silicon containing dielectric film 317 in Akasaka is used as an ILD/etching mask/passivation layer. As shown in Table 11.2 Types of CVD Reactors and Principal Characteristics [of Quirk9], passivation and ILD layer/film are deposited by Plasma Assisted CVD which has an excellent gap fill for high aspect ratio gaps. Ans. 16-17. 9 The Examiner identifies “Quirk” as “Quirk, Michael and Serda, Julian; Semiconductor Manufacturing Technology; 2001; Prentice- Hall, Inc., Upper Saddle River, NJ, pp. 271 and 277.” Ans. 16-17. Appeal 2012-002270 Application 12/370,276 7 In response, the Appellants contend that “even though Akasaka discloses using the CVD process to deposit the silicon-containing dielectric film, the result of such CVD deposition includes trench portions that are not completely filled as shown in FIG. 20 . . . .” Reply Br. 8.10 The Appellants’ arguments are supported by the record. Akasaka expressly discloses that “as shown in FIG. 20, a silicon- containing dielectric (insulating) film [317] is deposited on the conductive film 316 all over the substrate.” Akasaka ¶ 78. While Akasaka Figure 20 shows that dielectric film 317 covers the surface of the substrate, Akasaka Figure 20 does not show that trenches 314 are completely filled with dielectric film 317 using the disclosed CVD process. Indeed, as pointed out by the Appellants, in a subsequent step, Akasaka Figure 21 shows that left-hand trench 314 is filled with photo-resist mask 318. See Akasaka ¶ 80. To the extent that the Examiner is taking the position that the CVD process disclosed in Akasaka could be used to completely fill trenches 314 with dielectric film 317, the Examiner has not directed us to any evidence establishing that it would have been desirable to completely fill trenches 314 with dielectric film 317 in Akasaka’s method. 10 Reply Brief dated November 7, 2011. Appeal 2012-002270 Application 12/370,276 8 Based on the foregoing, a preponderance of the evidence of record weighs against a conclusion of obviousness. Therefore, the § 103(a) rejections on appeal are not sustained. D. DECISION The decision of the Examiner is reversed. REVERSED dm