Ex Parte Wiencke et al

Patent Trial and Appeal Board

Jul 16, 2018

14554709 (P.T.A.B. Jul. 16, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/554,709 11/26/2014
23494 7590 07/18/2018
TEXAS INSTRUMENTS IN CORPORA TED
PO BOX 655474, MIS 3999
DALLAS, TX 75265
UNITED ST A TES OF AMERICA
FIRST NAMED INVENTOR
Christian Wieneke
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TI-75058 4526
EXAMINER
PETRANEK, JACOB ANDREW
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
07/18/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHRISTIAN WIENCKE and SHREY BHATIA
Appeal2017-009715
Application 14/554,709
Technology Center 2100
Before JOSEPH L. DIXON, MAHSHID D. SAADAT, and
DENISE M. POTHIER, Administrative Patent Judges.
POTHIER, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants 1,2 appeal under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1-20. Br. 5-13. We have jurisdiction under 35 U.S.C.
§ 6(b ). We affirm.
1 Throughout this Opinion, we refer to the Final Action (Final Act.) mailed
August 22, 2016, the Appeal Brief (Br.) filed January 20, 2017, and the
Examiner's Answer (Ans.) mailed April 7, 2017. No Reply Brief was filed.
2 The real party in interest is listed as Texas Instruments Deutschland
GmBH. Br. 1.
Appeal2017-009715
Application 14/554,709
Invention
Appellants' invention concerns increasing performance in a processor
using multiple execution pipelines. See Spec. ,r,r 2, 13. A first execution
control unit controls the execution of all instructions executable by the
processor; a second execution control unit controls the execution of only a
subset of the instructions (e.g., the most frequently executed instructions or
relatively simple operand addressing) executable by the first execution unit.
Spec. ,r,r 2, 13, 17. This arrangement increases the instruction execution rate
relative to single-scalar processors and reduces energy consumption relative
to superscalar processors. Spec. ,r,r 12-13, Figs. 4--5.
Claim 1 is reproduced below:
1. A processor, comprising:
a first execution pipeline comprising:
a first decode unit configured to decode all
instructions executable by the processor; and
a first execution control unit coupled to the first
decode unit, and configured to control execution of all
instructions executable by the processor using one or
more of a plurality of execution units and one or more
execution stages;
a second execution pipeline comprising:
a second decode unit configured to decode only a
subset of the instructions executable via the first
execution control unit, the subset of the instructions
executable using only a same selected one of the
execution units and a single execution stage; and
a second execution control unit coupled to the
second decode unit, and configured to control execution
of only the subset of the instructions decoded by the
second decode unit.
Br. 14 (Claims App.).
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Application 14/554,709
The Examiner relies on the following as evidence of unpatentability:
Grochowski
Lin
us 5,416,913
us 5,881,279
May 16, 1993
Mar. 9, 1999
Intel Corporation, INTEL® PENTIUM PROCESSOR AT ICOMP INDEX
510\60 MHz, PENITUM PROCESSOR AT ICOMP INDEX 567\66 MHz
(PRELIMINARY) 1-31 (1994) ("Intel").
John L. Hennessy & David A. Patterson, COMPUTER ORGANIZATION AND
DESIGN, THE HARDWARE/SOFTWARE INTERFACE 151-52 (2d ed. 1998)
("Hennessy").
The Rejections
Claims 1-17 are rejected under 35 U.S.C. § 103 as unpatentable over
Lin, Grochowski, and Official Notice. Final Act. 5-17.
Claims 18-20 are rejected under 35 U.S.C. § 103 as unpatentable over
Lin and Official Notice. Final Act. 2--4.
THE OBVIOUSNESS REJECTION OVER LIN, GROCHOWSKI,
AND OFFICIAL NOTICE
Claims 1-4 and 6-9
Appellants argue the claims 1--4 and 6-9 collectively. Br. 5-8. We
select claim 1 as representative. See 37 C.F.R. § 4I.37(c)(l)(iv).
Appellants argue claim 1 does not require a single instruction pipeline
as the Examiner discusses in the Office Action but rather recites "a second
decode unit configured to decode only a subset of the instructions ... , the
subset of the instructions executable using only a same selected one of
the execution units and a single execution stage." Br. 6 ( citing Final Act.
6-7). Appellants further argue Grochowski does not disclose the destination
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Application 14/554,709
of its Figure 3 's pipelines and, thus, does not teach or suggests, even in
combination with Lin, the emphasized language in claim 1. Br. 6-7 ( citing
Final Act. 6-7). Even more, Appellants contend the Examiner fails to
explain how Lin and Grochowski are being combined, and the proposed
combination has no reasonable expectation of success. Br. 7. Lastly,
Appellants assert the "Examiner has identified the same elements of Lin et
al. as both first and second execution control units [(Figure 1)]" (Br. 8) and
that element 120 cannot be both a decoder and an execution control unit in
claim 1. Br. 8.
ISSUES
Under§ 103, has the Examiner erred in rejecting claim 1 by finding
Lin, Grochowski, and Office Notice collectively would have taught or
suggested (I) "a second decode unit configured to decode only a subset of
the instructions executable via the first execution control unit, the subset of
the instructions executable using only a same selected one of the execution
units and a single execution stage" and (II) "a first execution control unit"
and "a second execution control unit"?
ANALYSIS
Based on the record before us, we are not persuaded of error in the
Examiner's rejection of independent claim 1.
I.
Appellants argue claim 1 does not recite "a single instruction
pipeline." Br. 6 (referring to the Final Act. 6-7). We agree as claim 1 fails
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to use the phrase "single instruction"3 when claiming "a first execution
pipeline" and "a second execution pipeline." Br. 14 (Claims App.).
However, Appellants do not further assert Lin, Grochowski, or the officially
noticed facts fail to teach the recited first and second execution pipelines.
See Br. 6-7. As such, to the extent an argument has been presented related
to the recited pipelines, Appellants' argument is unavailing.
Also, to the extent Appellants contend the combination of references
do not relate or teach the "second decode unit" and, more specifically,
Grochowski does not teach the recited instruction subset is "executable via
one of the execution units" (see Br. 6), the Examiner does not rely
exclusively on Grochowski to teach the recited "second decode unit." See
Final Act. 6 ( citing both Grochowski and Lin). Lin teaches or suggests a
second decode unit (e.g., 122) configured to decode a subset of instruction
(e.g., CISC (complex instruction set) subset decoded into a RISC (reduced
instruction set) micro-operation), the subset of the instruction executable
using a single execution stage (e.g., single-cycle RISC micro-operation).
Lin 2:64--3:3, Fig. 1, cited in Final Act. 6; see also Ans. 2-3. For example,
the Examiner determines, without rebuttal from Appellants, "[i]nteger
instructions are well-known to one of ordinary skill in the art to have many
single-cycle operations." Ans. 3.
3 The Examiner uses both the words "separate" and "single" when
addressing the second pipeline. The rejection discusses both "sending
instructions down a separate pipeline" when describing Grochowski (Final
Act. 6 (italics added)), as well as "sending instructions from the partial
decoder of Lin to a single instruction pipeline of Grochowski" and "a single
execution unit of Lin" (Final Act. 7 (italics added)).
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Lin also teaches functional/execution units 140, 142, and 144 execute
specific operations ( e.g., unit 140 executes only integer micro-operations,
unit 142 executes floating-point micro-operations, and unit 144 executes
certain, special purpose micro-operations). Lin 3: 13-21, cited in Final Act.
6. As such, although silent regarding which instructions are decoded by
decoders 122 and 124 (Ans. 3), Lin suggests "the subset of instructions"
(e.g., subset of CISC instruction set) are executable using only a selected one
of the execution units ( e.g., unit 140 executing only integer micro-
operations ). See Lin 2:67-3:3, 3: 13-20, Fig. 1.
Additionally, Grochowski suggests the instruction subset uses "only a
same selected one of the execution units and a single execution stage" as
recited. Grochowski 3:20-67, 5:1-14, Figs. 2-3, cited in Final Act. 6. The
rejection determines Grochowski discusses "sending instructions down a
separate pipeline." Final Act. 6. Grochowski specifically discusses a P5
processor having av-pipe or pipeline executing "simple" instructions
(Grochowski 3:20-27), such as execution unit 140 in Lin that executes only
integer micro-operations (Lin 3: 13-21) as previously discussed. In the
Examiner's Answer, the Examiner elaborates the P5 processor has a V
pipeline ALU (arithmetic logic unit), which "is a single execution unit"
(Ans. 3 (citing Intel 4)) and "allows for the subset decoder of Lin to output
single-cycle micro-operations to a single execution unit" (Ans. 3--4).
Appellants present insufficient rebuttal to these findings.
Appellants further contend that the proposed combination has no
reasonable expectation of success because the Examiner fails to indicate
how the references are combined. Br. 7. Notably,
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The test for obviousness is not whether the features of a secondary
reference may be bodily incorporated into the structure of the primary
reference; nor is it that the claimed invention must be expressly
suggested in any one or all of the references. Rather, the test is what
the combined teachings of the references would have suggested to
those of ordinary skill in the art
In re Keller, 642 F.2d 413, 425 (CCPA 1981 ). Thus, the Examiner need not
bodily incorporate Grochowski's structure into Lin as Appellants discuss.
See Br. 7. \/foreover, the rejection cites to Grochowski not for the specific
features contested in the brief (Br. 7) but rather to teach sending instructions
down a separate pipeline having a single-cycle ( e.g., the recited "single
execution stage") was known. See Final Act 6. Contrary to Appellants'
assertions, the rejection further proposes to include such a feature in Lin and
indicates what the combined teachings would have suggested to those skilled
in the art. S'ee Final Act 6-7; see also Ans. 4-5.
II.
Next, Appellants assert the "Examiner has identified the same
elements of Lin et al. as both first and second execution control units
[(Figure 1)]" (Br. 8) and that element 120 cannot be both a decoder and an
execution control unit in claim 1. Br. 8. The Examiner responds
The rejection states that the first execution control unit is read
upon by "The inherent control signals output by decoder 120 ..
. [. ]" The rejection states that the second execution control unit
is read upon by "The inherent control signals output by
decoders 122 and 124 ... [. ]" The citation of elements 140-144
are cited as the recipient of the decoded control signals for
executing the actual instruction. However, the execution units
themselves aren't included in either control unit. It's also noted
that the claims recite a first execution pipeline and a second
execution pipeline, but do not require that both are separate and
distinct with no overlap.
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Ans. 5 ( quoting Final Act. 5 and 6). Thus, as explained, the Examiner is not
mapping "the same elements of Lin et al. as both first and second execution
control units." Br. 8.
Nonetheless, to the extent mapping a signal to a "unit" (see Final Act.
5---6) is too broad a claim construction "in light of the specification as it
would be interpreted by one of ordinary skill in the art" (In re Am. Acad. of
Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004), the rejection states
"[t]he control signals for the micro-operations control how the micro-
operation is processed in the pipeline" and cites to various elements. Final
Act. 5---6. For example, the rejection includes reservation station 130 as
teaching the recited "a first execution control unit" and "a second execution
control unit" in claim 1. Final Act. 5---6.
Given that the rejection indicates the execution control unit controls
how micro-operations are processed (see Final Act. 5---6), the rejection's
reliance on both output control signals and element 130 is not misplaced.
That is, Lin teaches micro-operation output queue 130 has a queue for each
execution unit ( e.g., one for integer micro-operations 140, one for floating-
point micro-operations 142, and one for special purpose operations 144).
Lin 15-29, Fig. 1. As such, Lin suggests the control signal outputted to and
received by the three different queues (e.g., from decoder 120) creates "a
first execution control unit" and the control signal outputted to and received
by a single queue (e.g., from decoder 122) creates "a second execution
control unit." See Lin 15-29, Fig. 1.
We emphasize, as did the Examiner, "the claims recite a first
execution pipeline and a second execution pipeline, but do not require that
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both are separate and distinct with no overlap." Ans. 5. As such, although
the Examiner's mapping may result in partially overlapping elements, Lin
suggests a first execution pipeline and second execution pipeline as broadly
as recited.
For the foregoing reasons, Appellants have not persuaded us of error
in the rejection of independent claim 1 and claims 2--4 and 6-9, which are
not separately argued.
Claim 5
Claim 5 depends from claim 1 and further recites, in pertinent part,
"the second execution pipeline is configured to apply only register and
immediate addressing modes supported by the processor." Br. 15 (Claims
App.). When rejecting this claim, the Examiner takes notice of the fact that
register and immediate addressing modes are known to be used to implement
instructions using operands. See Final Act. 9, cited in Br. 9. Appellants
assert they have "not been amply apprised of' the officially noticed facts
(Br. 9--10), they timely challenged the Examiner's taking of Official Notice
(Br. 8 ( citing its July 8, 2016 Response)), and the Examiner has not provided
support for the officially noticed facts (Br. 8-9). We are not convinced.
In the Answer, the Examiner explains the facts taken are well-known
to one skilled in the art and can be "found in any introductory college
textbook to computer architecture." Ans. 7; see also Ans. 9 ( citing
Hennessy). Hennessy describes and illustrates known register addressing,
and known immediate addressing and a single Add operation using both.
Hennessy 151-52, Fig. 3 .17. Additionally, Lin and Grochowski collectively
teach and suggest the second execution pipeline is configured to apply
integer operations and can be embodied in a P5 microprocessor. See, e.g.,
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Lin 3:16-18, Fig. 1; see also Grochowski 2:46-48, 3:25-27. Intel shows
and suggests the P5 microprocessor performs its operations using an
instruction subset involving an Integer Register File performing arithmetic
operations, such as an Add operation, using an ALU. See Intel 4.
Appellants do not rebut these findings.
Given the record, the Examiner has provided sufficient, supporting
evidence that the noticed facts and the recited "second execution pipeline is
configured to apply only register and immediate addressing modes" as
recited are known in the art.
Claims 10-17
For independent claim 10, Appellants repeat many of the arguments
previously addressed, including ( 1) the Examiner's remarks are unrelated to
the disputed "first execution control unit configured to execute only a subset
of all instructions executable by the processor that are executable using only
a same selected one of a plurality of execution units," (2) claim 10 does not
require a single instruction pipeline, (3) Grochowski does not disclose the
pipelines' destinations, ( 4) there is no reasonable expectation of success
when combining Grochowski with Lin, and ( 5) the recited references fail to
teach the instruction subset are executable using only a selected one of a
plurality of execution units. Br. 11-12. We are not persuaded for the above
reasons.
For the foregoing reasons, Appellants have not persuaded us of error
in the rejection of independent claim 10 and claims 11-17, which are not
separately argued.
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Application 14/554,709
THE OBVIOUSNESS REJECTION OVER LIN AND OFFICIAL NOTICE
Claims 18-20 are rejected based on Lin and Official Notice. In
pertinent part, claim 18 recites "a second execution control unit configured
to ... apply only register and immediate addressing modes to access
operands."4 Br. 19 (Claims App.). This limitation is similar to that in claim
5, and Appellants present similar arguments. Br. 12-13. We are not
persuaded of error and refer above for more details.
Additionally, Appellants argue the cited references do not teach
separate execution control units or the features of the second execution
control unit. Br. 12. These contentions are addressed above and are not
convmcmg.
Accordingly, Appellants have not persuaded us of error in the
rejection of independent claim 18 and claims 19 and 20, which are not
separately argued.
DECISION
We affirm the Examiner's rejection of claims 1-20 under 35 U.S.C.
§ 103.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
4 Notably, claim 18 does not recite "the subset of the instructions executable
using only a same selected one of the execution units and a single execution
stage" limitation found in claim 1.
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