Ex Parte Weber et al

Patent Trial and Appeal BoardJun 28, 2013

11289140 (P.T.A.B. Jun. 28, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/289,140 11/29/2005 Bret S. Weber 04-2263 5969 27683 7590 06/28/2013 HAYNES AND BOONE, LLP IP Section 2323 Victory Avenue Suite 700 Dallas, TX 75219 EXAMINER TOWFIGHI, AFSHAWN M ART UNIT PAPER NUMBER 2469 MAIL DATE DELIVERY MODE 06/28/2013 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE _____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD _____________ Ex parte BRET S. WEBER, MOHAMAD H. EL-BATAL, and WILLIAM P. DELANEY _____________ Appeal 2010-009738 Application 11/289,140 Technology Center 2400 ______________ Before, DAVID M. KOHUT, JASON V. MORGAN, and MICHAEL J. STRAUSS, Administrative Patent Judges. KOHUT, Administrative Patent Judge. DECISION ON APPEAL Appeal 2010-009738 Application 11/289,140 2 This is a decision on appeal under 35 U.S.C. § 134(a) of the Final Rejection of claims 1-16. We have jurisdiction under 35 U.S.C. § 6(b). We reverse the Examiner’s rejection of these claims. INVENTION The invention is directed to a method, apparatus, and system that allow direct memory access from one storage controller to a plurality of storage controllers. Spec. 6-8. Claim 1 is representative of the invention and is reproduced below: 1. An apparatus within a storage controller for communication among a plurality of storage controllers in a clustered storage system, the apparatus comprising: a local memory mapped interface for access to local cache memory of the storage controller by other components within the storage controller; a fabric communication interface for inter-controller communication between the storage controllers and other storage controllers of the plurality of storage controllers; and a remote memory mapped interface for access to the local cache memory of the storage controller by the other storage controllers, wherein the fabric communication interface is adapted to permit remote DMA (“RDMA”) access by the storage controller to local cache memories of the other storage controllers and is further adapted to permit RDMA access to the local cache memory of the storage controlled by the other storage controllers. REFERENCES Pecone US 2003/0065733 A1 Apr. 3, 2003 Hoshino US 2003/0131068 A1 Jul. 10, 2003 Appeal 2010-009738 Application 11/289,140 3 Weber1 US 6,732,104 B1 May 4, 2004 Weber2 US 6,820,171 B1 Nov. 16, 2004 REJECTION AT ISSUE Claims 7, 8, and 15 are rejected under 35 U.S.C. § 102(b) as being anticipated by Hoshino. Ans. 3-4. Claims 9, 14, and 16 are rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Hoshino and Pecone. Ans. 4-5. Claims 10, 11, and 13 are rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Hoshino and Weber ’104. Ans. 5-6. Claims 1-5 and 12 are rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Hoshino and Weber ’171. Ans. 6-7. Claim 6 is rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Hoshino, Weber ’171, and Pecone. Ans. 8. ISSUE Did the Examiner err in finding that Hoshino discloses an inter-controller interface that uses remote direct memory access? ANALYSIS Independent claim 1 requires an inter-controller interface that permits remote DMA access between the local cache memory of one or more other storage controllers and the storage controller. Independent claims 7 and 15 contain a similar limitation. Claims 2-6, 8-14, and 16 are dependent upon one of claims 1, 7, and 15. The Examiner agrees with Appellants’ definitions of DMA (direct 1 Hereinafter referred to as Weber ’104. 2 Hereinafter referred to as Weber ’171. Appeal 2010-009738 Application 11/289,140 4 memory access) and RDMA (remote direct memory access) located on the top of page 11 of the Appeal Brief. Ans. 9. These definitions state that DMA and RDMA require data transfer from the main memory of a device to another device without passing the data through the CPU. App. Br. 11. The Examiner finds that Hoshino discloses this process since the storage devices transfer data to each other without the use of the storage devices’ host computer. Ans. 9-10. Appellants contend that the Examiner’s finding is incorrect since each of the storage devices uses a processor to transfer data. App. Br. 12; Reply Br. 5. We agree with Appellants. The Examiner’s findings do not persuasively show that the processor located in each of the storage devices is not the CPU of the storage device as the term CPU is used in and excluded by the definitions of DMA and RDMA provided by Appellants and agreed to by the Examiner. See also Hishino ¶ [0048] (“[t]he memory 35 stores programs to be executed by the processor 34”). Since the storage device processors are used in transferring data, see Ans. 8 (“processor (34) . . . assists the storage device in communicating with other storage devices”), the Examiner’s findings do not persuasively show that Hoshino discloses DMA or RDMA. The additional references were not cited to teach or suggest this limitation and we will not engage in any inquiry as to whether these additional references cure the noted deficiencies. Therefore, we cannot sustain the Examiner’s rejection of claims 1-16. CONCLUSION The Examiner erred in finding that Hoshino discloses an inter-controller interface that uses remote direct memory access. Appeal 2010-009738 Application 11/289,140 5 SUMMARY The Examiner’s decision to reject claims 1-16 is reversed. REVERSED tj