Ex Parte WE et al

Patent Trial and Appeal Board

Aug 31, 2017

14450201 (P.T.A.B. Aug. 31, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/450,201 08/01/2014 Hong Bok WE QC143271 1980
12371 7590 09/05/2017
Mnnrv rre.issle.r Olrk & T owe P P /OT TAT POMM EXAMINER
4000 Legato Road, Suite 310
Fairfax, VA 22033
PAREKH, NITIN
ART UNIT PAPER NUMBER
2811
NOTIFICATION DATE DELIVERY MODE
09/05/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
meo.docket@mg-ip.com
meo@mg-ip.com
ocpat_uspto@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HONG BOK WE,
DONG WOOK KIM, JAE SIK LEE,
KYU-PYUNG HWANG,
and YOUNG KYU SONG
Appeal 2017-001494
Application 14/450,201
Technology Center 2800
Before ADRIENE LEPIANE HANLON, JENNIFER R. GUPTA, and
DEBRA L. DENNETT, Administrative Patent Judges.
HANLON, Administrative Patent Judge.
DECISION ON APPEAL
A. STATEMENT OF THE CASE
The Appellants filed an appeal under 35 U.S.C. § 134(a) from an
Examiner’s decision finally rejecting claims 1—6. According to the Final
Office Action dated January 21, 2016 (“Final Act.”), claims 7—20 are also
pending but have been withdrawn from consideration. We have jurisdiction
under 35 U.S.C. § 6(b).
We AFFIRM.
Appeal 2017-001494
Application 14/450,201
Claims 1 and 2 are reproduced below from the Claims Appendix of
the Appeal Brief dated June 21, 2016 (“App. Br.”). The limitations at issue
are italicized.
1. A packaged semiconductor device, comprising:
a first package comprising a substrate, a first die coupled
to the substrate, and a bonding pad over the substrate;
a second package comprising a second die; and
a frame coupled to the bonding pad and the frame
coupled to the second package at a connection point, wherein
the connection point is offset from the bonding pad and is
located between the first die and the second die.
2. The packaged semiconductor device of claim 1,
further comprising a non-conductive layer between the first
package and the second package such that the first package
directly contacts the non-conductive layer and the second
package directly contacts the non-conductive layer without an
air gap between the first package and the second package.
App. Br. 10.
The Examiner maintains the following rejections on appeal:
(1) claim 2 under 35 U.S.C. § 112(a) as failing to comply with the
written description requirement;
(2) claim 1 under 35 U.S.C. § 102(a)(1) as anticipated by Merilo et
al.;1 and
(3) claims 2—6 under 35 U.S.C. § 103(a) as unpatentable over
Merilo in view of Shim et al.2
1 US 7,986,043 B2, issued July 26, 2011 (“Merilo”).
2 US 6,861,288 B2, issued March 1, 2005 (“Shim”).
2
Appeal 2017-001494
Application 14/450,201
B. DISCUSSION
1. Rejection (1)
The Examiner finds the following limitation recited in claim 2 lacks
written description support: “the first package directly contacts the non-
conductive layer and the second package directly contacts the non-
conductive layer without an air gap between the first package and the second
package.” Final Act. 2. More specifically, the Examiner finds there is no
literal support for the claim limitation at issue and finds annotated Figure 4,
reproduced below, shows an air gap between the side portions of top/second
package 502 and bottom/first package 501. Ans. 2—3, 4.* 3
Examiner’s annotated Figure 4 depicts a block diagram
of a package on package structure and identifies an
air gap between top package 502 and bottom package 501.
3 Examiner’s Answer dated September 21, 2016.
3
Appeal 2017-001494
Application 14/450,201
In response, the Appellants present an additional annotated Figure 4,
reproduced below. Reply Br. 3.* 4 According to the Appellants, in their
annotated Figure 4, the dark line originally shown in Figure 4, the text “TOP
PACKAGE,” and reference numeral 502 and its bracket are removed. Reply
Br. 2.
Appellants’ annotated Figure 4 depicts a block diagram
of a package on package structure.
The Appellants argue that “[a]s can be seen in the edited and
annotated Figure 4 , there is no air gap between bottom package 501 and
top package 502, only the non-conductive layer 590.” Reply Br. 2. The
Appellants argue that the dark line that was removed did not indicate any
structure but merely added clarity to the drawing for the associated “top
package” and “[l]eadframe molded bottom package” text on the right of
original Figure 4. Reply Br. 2.
The Appellants’ argument is persuasive of reversible error. As shown
in Appellants’ Figure 4, the sides of the encapsulant (not numerically
4 Reply Brief dated November 2, 2016.
4
Appeal 2017-001494
Application 14/450,201
referenced) in bottom package 501 are flush with the sides of non-
conductive layer 590, and the sides of the portion of top package 502 that
directly contacts non-conductive layer 590 are flush with the sides of layer
590. Thus, contrary to the Examiner’s findings, there is no air gap between
the side portions of top package 502 and bottom package 501.
The § 112(a) rejection is not sustained.5
2. Rejection (2)
Referring to annotated Merilo Figure 1, reproduced below, the
Examiner finds Merilo discloses a packaged semiconductor device including
a frame comprising leads 104 coupled to a bonding pad of first package 108,
102 and coupled to second package 114 at a connection point (i.e.,
unnumbered bump on the bottom of package 114), wherein the connection
point is offset from the bonding pad and is located between first die 112 and
second die 116 as recited in claim 1. Final Act. 3^4; Ans. 4—5.
5 In the event of further prosecution, the Examiner may consider whether the
empty spaces above connection points 570 in non-conductive layer 590,
depicted in Appellants’ Figure 4, are air gaps.
5
Appeal 2017-001494
Application 14/450,201
N*
4
KJ i
offset
Examiner’s annotated Merilo Figure 1 depicts a
cross-sectional view of an integrated circuit
package on package system.
In response, the Appellants argue that the connection point (i.e.,
unnumbered bump on the bottom of package 114) is not between first
die 112 and second die 116, but rather is off to the sides of the first and
second die. App. Br. 6. The Appellants present an additional annotated
Merilo Figure 1, reproduced below, to illustrate their argument. Reply Br. 5.
6
Appeal 2017-001494
Application 14/450,201
Appellants’ annotated Merilo Figure 1 depicts a
cross-sectional view of an integrated circuit
package on package system.
The Appellants’ argument is not persuasive of reversible error. In
Merilo, the connection point is located above first die 112 and below second
die 116 (i.e., the connection point is between a first die and a second die in a
vertical direction). We recognize that the connection point depicted in
Appellants’ Figure 4 is located between the first die and the second die in a
horizontal direction. However, as in Merilo’s device, the connection point
in Appellants’ Figure 4 is also located between a first die and a second die in
a vertical direction.
Claim 1 recites that “the connection point... is located between the
first die and the second die.” App. Br. 10 (emphasis added). Claim 1 does
not define whether the term “between” refers to a horizontal direction, a
vertical direction, or a combination of horizontal and vertical directions.
Thus, giving the term “between” the broadest reasonable interpretation in
7
Appeal 2017-001494
Application 14/450,201
light of the Appellants’ Specification,6 we interpret “between” as
encompassing an orientation solely in the vertical direction, i.e., a first die
located below the connection point and a second die located above the
connection point and the first die. As the Examiner finds, Merilo describes a
first die, a second die, and a connection point oriented in that manner. See
Examiner’s annotated Merilo Fig. 1. Therefore, the § 102(a)(1) rejection of
claim 1 is sustained.
3. Rejection (3)
The Examiner finds Merilo does not disclose “a non-conductive layer
between the first [108, 102] and second [114] packages such that the first
package directly contacts the non-conductive la[y]er and the second package
directly contacts the non-conductive la[y]er without an air gap between the
first package and the second package” as recited in claim 2. Final Act. 5.
The Examiner finds Shim discloses a packaged semiconductor device
comprising first/bottom interposer package (126, 118, 108) and second/top
package (104, 106) adhesively attached to each other with a conventional
electrically non-conductive and thermally conductive layer (202). Final
Act. 5. The Examiner finds that in the arrangement disclosed in Shim,
a portion of a top surface of the first package directly contacts
the non-conductive layer [202] and the second package directly
contacts the non-conductive layer at a bottom surface thereof
without an air gap between the portion of the top surface of the
first package and the bottom surface of the second package.
Final Act. 5.
6 See In re Herz, 537 F.2d 549, 551 (CCPA 1976) (“claims are given their
broadest reasonable construction consistent with the specification”).
8
Appeal 2017-001494
Application 14/450,201
The Examiner concludes that it would have been obvious to
incorporate the non-conductive layer of Shim between the first and second
packages of Merilo. Final Act. 5—6.
The Appellants do not dispute that it would have been obvious to
combine Merilo and Shim as proposed by the Examiner. Rather, the
Appellants argue that “the stacked package arrangement of Shim uses solder
balls 106 that create an air gap between the bottom package 102 and the top
package 104 as can be seen in Figure 2 of Shim.” App. Br. 8.
In response, the Examiner finds that solder balls 106 in the second/top
package are surrounded by non-conductive layer 202, which removes any air
gap between the first/bottom package and the second/top package. Ans. 6
(bold omitted).
The Appellants do not direct us to any error in the Examiner’s finding.
In the Reply Brief, however, the Appellants argue for the first time on appeal
that the Examiner ignores cavity 128 between the first package and the
second package, which is the equivalent of the air gap recited in claim 2.
Reply Br. 5—6.
The Appellants’ argument is not responsive to an argument raised in
the Examiner’s Answer (see Ans. 6), and the Appellants do not show good
cause why the argument could not have been presented in the Appeal Brief.
37 C.F.R. § 41.41(b)(2) (2015). Therefore, the Appellants’ new argument is
untimely and will not be considered on appeal.
The Appellants do not present arguments in support of the separate
patentability of claims 3—6. Therefore, the § 103(a) rejection of claims 2—6
is sustained.
9
Appeal 2017-001494
Application 14/450,201
C. DECISION
The Examiner’s decision to reject claim 2 under 35 U.S.C. § 112(a) as
failing to comply with the written description requirement is reversed.
The Examiner’s decision to reject claim 1 under 35 U.S.C. § 102(a)(1)
as anticipated by Merilo is affirmed.
The Examiner’s decision to reject claims 2—6 under 35 U.S.C.
§ 103(a) as unpatentable over Merilo in view of Shim is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED
10