Ex Parte Wallach et al

Patent Trial and Appeal Board

Dec 20, 2016

11969792 (P.T.A.B. Dec. 20, 2016)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/969,792 01/04/2008 Steven J. Wallach CONP.P0004US/10717402 1653
137973 7590 12/22/2016
Micron/Norton Rose Fulbright US LLP
2200 Ross Avenue
Suite 3600
Dallas, TX 75201
EXAMINER
TSAI, SHENG JEN
ART UNIT PAPER NUMBER
2136
NOTIFICATION DATE DELIVERY MODE
12/22/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
doipdocket@nortonrosefulbright.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte STEVEN J. WALLACH and
TONY BREWER
Appeal 2015-002229
Application 11/969,792
Technology Center 2100
Before ROBERT E. NAPPI, JOHN P. PINKERTON, and
NABEEL U. KHAN, Administrative Patent Judges.
PINKERTON, Administrative Patent Judge
DECISION ON APPEAL1
Appellants2 appeal under 35 U.S.C. § 134(a) from the Examiner’s Final
Rejection of claims 1—22 and 35—67, which constitute all of the claims pending
this application. Claims 23—34 are canceled. We have jurisdiction under
35 U.S.C. § 6(b).
We affirm-in-part.
1 An oral hearing was held in this case on December 9, 2016.
2 Appellants identify Convey Computer Corporation as the real party in
interest. App. Br. 2.
Appeal 2015-002229
Application 11/969,792
STATEMENT OF THE CASE
Introduction
Appellants’ disclosed and claimed invention is generally directed to
“a system having two memory access paths: 1) a cache-access path in which
block data is fetched from main memory for loading to a cache, and 2) a
direct-access path in which individually-addressed data is fetched from main
memory for directly loading data into processor registers and/or storing
data.” Spec. 12.3
Claims 1 and 4 are exemplary and reproduced below (with the
disputed limitations emphasized)'.
1. A system comprising:
non-sequential access memory;
a processor that is operable to process a first portion of
instructions included in an executable file;
a communication bus via which the processor sends a
second portion of instructions with specific syntax as appearing
in the executable file to a heterogeneous functional unit,
wherein the first portion of instructions and the second portion
of instructions comprise instructions of a same instruction set
architecture adapted to define execution of instructions of an
application by both the processor and the heterogeneous
functional unit',
the heterogeneous functional unit that is operable to
execute the second portion of instructions according to the
specific syntax;
3 Our Decision refers to the Final Action mailed April 9, 2014 (“Final
Act.”); Appellants’ Appeal Brief filed Sept. 9, 2014 (“App. Br.”); the
Examiner’s Answer mailed Oct. 29, 2014 (“Ans.”); Appellants’ Reply Brief
filed Dec. 19, 2014 (“Reply Br.”); and, the original Specification filed
Jan. 4, 2008 (“Spec.”).
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Application 11/969,792
cache memory;
a cache-access path in which block data is communicated
between said non-sequential access memory and said cache
memory for accesses of said block data by said processor for
processing said first portion of instructions; and
a direct-access path in which individually-addressed
data is communicated to/from said non-sequential access
memory for accesses of said individually-addressed data by
said heterogeneous functional unit for processing said second
portion of instructions.
4. The system of claim 1 wherein said processor comprises
a first instruction set that defines instructions that are
executable by said processor, wherein said heterogeneous
functional unit comprises a second instruction set that defines
instructions that are executable by said heterogeneous
functional unit, and wherein said instructions defined in said
first instruction set are not executable by said heterogeneous
functional unit, and said instructions defined in said second
instruction set are not executable by said processor.
Rejections on Appeal
Claims 4 and 63—67 are rejected under 35 U.S.C. § 112(a) or 35
U.S.C. § 112 (pre-AIA), first paragraph, as being indefinite for failing to
comply with the written description requirement. Final Act. 8—11.
Claims 1—14 are rejected under 35 U.S.C. § 112(b) or 35 U.S.C.
§112 (pre-AIA), second paragraph, as being indefinite for failing to
particularly point out and distinctly claim the subject matter which the
inventor or a joint inventor, or for pre-AIA the applicant regards as the
invention. Final Act. 11—14.
Claims 1—10, 12—17, 19-22, 35—57, and 59-67 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Applicants’ Admission of
Prior Art (the Background section, paragraphs 4—24 of the Specification,
and Figure 1 (prior art) of the instant application) (“AAPA”) and Chauvel
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Application 11/969,792
et al. (US 2004/0088524 Al; published May 6, 2004) (“Chauvel”). Final
Act. 14-41.
Claims 11, 18, and 58 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over AAPA, Chauvel, and Sheaffer (US 2004/0236920
Al; published Nov. 25, 2004). Final Act. 41^42.
ANALYSIS
Rejection of Claims 4 and 63—67 under 35 U.S.C. § 112, first paragraph
Appellants argue that there is support, explicit and inherent, at least at
paragraph 33 of the Specification, and at paragraph 71 of U.S. Patent
Application Serial Number 11/841,406 (“the ’406 application”), which was
incorporated by reference at paragraph 1 of the Specification,4 for the
limitations of claim 4. App. Br. 9-12; Reply Br. 3—8. Appellants also argue
there is support, explicit and inherent, for the limitations of claims 63—67 for
at least the same reasons discussed regarding claim 4. App. Br. 11; Reply
Br. 8. The Examiner finds paragraph 33 of the Specification fails to provide
sufficient support for the limitations “said instructions defined in said first
instruction set are not executable by said heterogeneous functional unit, and
said instructions defined in said second instruction set are not executable by
said processor,” as recited in claim 4, and that claim 63 suffers from the
same deficiency as claim 4. See Ans. 3—7.
4 Appellants also argue 37 C.F.R. § 1.57(c) states that ‘“[ejssential material’
may be incorporated by reference . . .,” and 37 C.F.R. § 1.57(c)(1) describes
essential material as “material that is necessary to: (1) Provide a written
description of the claimed invention,... as required by 35 U.S.C. 112(a).”
Reply Br. 4.
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Application 11/969,792
For the reasons argued by Appellants, we agree with Appellants. In
particular, we agree with Appellants that paragraph 33 of the Specification
and paragraph 71 of the ’406 application would explicitly inform a person of
ordinary skill in the art “of an embodiment where the coprocessor is
configured with a different instruction set than the host processor’s
instruction set, where the coprocessor’s instruction set includes instructions
that are not in the instruction set of the host processor, and therefore, not
executable by the host-processor.” Reply Br. 4. We also agree with
Appellants that “at least. . . paragraph [0033], inherently discloses “wherein
said instructions defined in said first instruction set are not executable by
said heterogeneous functional unit.” Id. at 5—8. Thus, we do not sustain the
Examiner’s rejection of claim 4, as well as the rejections of claims 63—67,
under 35U.S.C. § 112, first paragraph.
Rejection of Claims 1—14 under 35 U.S.C. § 112, second paragraph
Regarding claim 1, the Examiner finds the term “heterogeneous” is
indefinite, as is the limitation “the first portion of instructions and the second
portion of instructions comprises of a same instruction set architecture
adapted to define execution of instructions of an application by both the
processor and the heterogeneous functional unit.” Final Act. 11—14; Ans.
10-11. In particular, the Examiner finds paragraph 6 of the Specification
defines “homogenous” to be “with the same instruction set” and because
“heterogeneous” is the antonym of “homogeneous,” it follows that
“heterogeneous” is being associated with different instruction sets. Ans. 10.
The Examiner finds, however, that the language of claim 1 appears to
suggest the processor and the heterogeneous functional unit are more
“homogenous” than “heterogeneous” because of the limitation “the first
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Application 11/969,792
portion of instructions and the second portion of instructions comprise
instructions of a same instruction set.” Id. The Examiner also finds that,
within the context of claim 1, the first portion of instructions and the second
portion of instructions are executable by both the processor and the
heterogeneous function unit “and it does not have anything to do with a
different instruction set at all. Id. at 11 (emphasis added).
Appellants argue that claim 1 “requires that the first and second
portions comprise instructions of a same instruction set architecture adapted
to define execution of instructions of an application by both the processor
and the heterogeneous functional unit,” but this does not mean the
instruction sets of the processor and heterogeneous functional unit are the
same. App. Br. 12—13; Reply Br. 9. Appellants also argue that two
instruction sets need only have one instruction that is not common to both
sets to be different and, therefore, the “recitation of ‘both the first portion of
instructions and the second portion of the instructions are executable by both
the processor and the heterogeneous functional unit’ is consistent with the
use of the phrase ‘heterogeneous functional unit.’” Reply Br. 10—11.
We are not persuaded by Appellants’ arguments. Instead, for the
reasons set forth by the Examiner, we agree with the Examiner’s finding that
that language of claim 1 appears to suggest the processor and the
heterogeneous functional unit are more “homogenous” than
“heterogeneous,” and, therefore, claim 1 is indefinite. Thus, we sustain the
Examiner’s rejection of claims 1—14 under 35 U.S.C. § 112, second
paragraph.
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Application 11/969,792
Rejection of Claims 1—22 and 35—67 under 35 U.S.C. § 103(a)
Appellants’ contend AAPA in view of Chauvel does not teach or
suggest “a direct-access path in which individually-addressed data is
communicated to/from said non-sequential access memory for accesses of
said individually-addressed data by said heterogeneous functional unit,” as
recited in claim 1, and as similarly recited in independent claims 15, 35, 39,
49, and 60. App. Br. 16—20; Reply Br. 15. The Examiner finds AAPA in
view of Chauvel teaches the disputed limitation because Chauvel teaches a
direct-access path of memory bus 222 between the second processor 204, the
heterogeneous functional unit, and the main memory 206. Final Act. 4—5;
Ans. 18.
We are persuaded by Appellants’ arguments that the Examiner has
erred. In particular, we agree with Appellants’ argument that there is no
teaching or disclosure “in Chauvel that the second processor’s type of access
to the main memory is individually-addressed access, as required in claim
1.” App. Br. 17; Reply Br. 15. Thus, the preponderance of the evidence
does not support the Examiner’s (1) findings that Chauvel teaches the
disputed limitation of claim 1 and (2) conclusion that the combination of
AAPA and Chauvel renders the subject matter of claim 1 obvious.
Accordingly, we do not sustain the Examiner’s rejection under
§ 103(a) of claim 1. For the same reasons, we do not sustain the Examiner’s
rejections under § 103(a) of independent claims 15, 35, 39, 49, and 60, as
well as claims 2—14, 16—22, 36—38, 40-48, 50-59, and 61—67, which depend
variously from claims 1,15, 35, 39, 49, and 60.
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Application 11/969,792
DECISION
We reverse the Examiner’s rejection of claims 4 and 63—67 under 35
U.S.C. § 112, first paragraph, for lack of written description.
We affirm the Examiner’s rejection of claims 1—14 under 35 U.S.C.
§112, second paragraph, for indefmiteness.
We reverse the Examiner’s rejection of claims 1—22 and 35—67 under
35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED-IN-PART
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