Ex Parte Walker

Patent Trial and Appeal BoardMar 23, 2017

13533253 (P.T.A.B. Mar. 23, 2017)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/533,253 06/26/2012 WILLIAM L. WALKER 1458-120338 8753 109712 7590 03/27/2017 Advanced Micro Devices, Inc. c/o Davidson Sheehan LLP 8834 North Capital of TX Hwy Suite 100 Austin, TX 78759 EXAMINER WOOLWINE, SHANE D ART UNIT PAPER NUMBER 2135 NOTIFICATION DATE DELIVERY MODE 03/27/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docketing@ds-patent.com AMD@DS-patent.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte WILLIAM L. WALKER Appeal 2016-006824 Application 13/533,253 Technology Center 2100 Before ERIC B. CHEN, MICHAEL J. STRAUSS, and AARON W. MOORE, Administrative Patent Judges. MOORE, Administrative Patent Judge. DECISION ON APPEAL Appeal 2016-006824 Application 13/533,253 STATEMENT OF THE CASE Appellant1 appeals under 35 U.S.C. § 134(a) from a Non-Final Rejection of claims 1—20, which are all of the pending claims. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. THE INVENTION The application is directed to “embodiments of a method and apparatus for concurrently accessing dirty bits in a cache.” (Abstract.) Claim 1, reproduced below, is exemplary of the subject matter on appeal: 1. An apparatus, comprising: a cache configurable to store a plurality of lines, wherein the lines are grouped into a plurality of subsets of the plurality of lines; a plurality of dirty bits associated with the plurality of lines; and first circuitry configurable to concurrently access the plurality of dirty bits associated with at least one of the subsets of the plurality of lines. THE REFERENCES The prior art relied upon by the Examiner in rejecting the claims on appeal is: Chauvel et al. Middleton et al. Nale et al. US 2002/0069331 Al US 2003/0135701 Al US 2014/0040550 Al June 6, 2002 July 17, 2003 Feb. 6, 2014 1 Appellant identifies Advanced Micro Devices, Inc. as the real party in interest. (See App. Br. 1.) 2 Appeal 2016-006824 Application 13/533,253 THE REJECTIONS 1. Claims 1—4, 11—14, and 20 stand rejected under 35 U.S.C. § 102(b) as anticipated by Chauvel. (See Final Act. 9-15.) 2. Claims 5—7 and 15—16 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Chauvel and Middleton. (See Final Act. 15—20.) 3. Claims 8—10 and 17—19 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Chauvel, Middleton, and Nale. (See Final Act. 20-23.) ANALYSIS Independent claims 1 and 20 require “first circuitry configurable to concurrently access the plurality of dirty bits associated with at least one of the subsets of the plurality of lines,” while independent claim 11 recites “means for concurrently accessing” dirty bits, and independent claim 12 recites a method that includes “concurrently accessing” dirty bits. In the anticipation rejection of claims 1—4, 11—14, and 20, the Examiner finds Chauvel to teach the claimed concurrent access of dirty bits in paragraph 80, which states “[concurrent accesses on RAM-sets and cache are supported,” as well as in paragraph 104. (Final Act. 10-11; Ans. 4.) Appellant argues Chauvel’s “system sequentially (rather than concurrently) checks dirty bits for each cache line and sequentially transfers valid lines with set dirty bits to memory.” (App. Br. 3.) Appellant further argues that “paragraph 80 fails to disclose concurrent accesses to a plurality of cache lines of a single cache” because it instead “discloses that a cache can be accessed concurrently with a RAM-set different from the cache.” (Id. at 4.) Finally, Appellant asserts that “concurrent access to different cache 3 Appeal 2016-006824 Application 13/533,253 lines does not imply or require that dirty bits for the different cache lines are also concurrently accessed.” (Id.) Appellants’ Specification discloses that “[ejmbodiments of the storage structures for the cache line dirty bits described in the present application allow the dirty bits for multiple ways to be read out concurrently or in parallel in response to a probe.” (Spec. 120 (emphasis added).) Consistent with the Specification, we construe “concurrent” to mean in parallel, i.e., not sequentially. Having reviewed Chauvel, we find that it does not unequivocally show concurrently accessing the dirty bits. Although Chauvel’s paragraph 80 does use the term “concurrently,” it appears that it refers to concurrently accessing (a) a RAM-set and (b) a cache and, in any event, it does not refer to the dirty bits specifically. Paragraph 104 states that the method “checks a dirty bit associated with the address selected by [the] start address register” and that “all four dirty bits on each line are checked” but is silent about whether the bits are accessed concurrently. We conclude that the reference is, at best, ambiguous regarding concurrent access to dirty bits and, thus, insufficient to support an anticipation rejection. See In re Brink, 419 F.2d 914, 917 (CCPA 1970) (“[I]f a reference is ambiguous and can be interpreted so that it may or may not constitute an anticipation of an appellant’s claims, an anticipation rejection under 35 U.S.C. § 102 based upon the ambiguous reference is improper.”); In re Hughes, 345 F.2d 184 (CCPA 1965) (“[I]f we accept arguendo the board’s position that [the reference] can be alternatively interpreted to show either of two final core structures, then [the reference] becomes an ambiguous reference which will not support an anticipation rejection.”). 4 Appeal 2016-006824 Application 13/533,253 We accordingly do not sustain the rejection of claims 1—4, 11—14, and 20 under 35 U.S.C. § 102(b). We also do not sustain the rejections of dependent claims 5—10 and 15—19 under 35 U.S.C. § 103(a), as they are also premised on Chauvel specifically teaching concurrent access. Because this issue is dispositive, we do not reach Appellant’s other arguments. DECISION The rejections of claims 1—20 are reversed. REVERSED 5