Ex Parte Wada et al

Patent Trial and Appeal BoardDec 7, 2018

13530173 (P.T.A.B. Dec. 7, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 13/530, 173 06/22/2012 Masaaki Wada 132167 7590 12/11/2018 SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (PP) 5005 E. McDowell Road Maildrop A700 Phoenix, AZ 85008 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 201101165US 2787 EXAMINER DOBBS, KRISTIN SENSMEIER ART UNIT PAPER NUMBER 2486 NOTIFICATION DATE DELIVERY MODE 12/11/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): patents@onsemi.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MASAAKI WADA, TORU OKADA, KAZUNORI CHIDA, and HIROKI ISHIDA Appeal2018-004772 Application 13/530, 173 1 Technology Center 2400 Before MAHSHID D. SAADAT, KAL YANK. DESHPANDE, and CATHERINE SHIANG, Administrative Patent Judges. SHIANG, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. Â§ 134(a) from the Examiner's rejection of claims 1-20, which are all the claims pending in the application. We have jurisdiction under 35 U.S.C. Â§ 6(b). We affirm. STATEMENT OF THE CASE Introduction According to the Specification, the present invention relates to "a video signal processing system including a system controller and a display 1 Appellants identify Semiconductor Components Industries, LLC as the real party in interest. App. Br. 3. Appeal2018-004772 Application 13/530, 173 controller." Spec. 1. "During system startup, startup can be speeded up since the display controller directly processes the video signal from the camera without using the system controller." Spec. 3. Claim 1 is exemplary: 1. A video signal processing system comprising a system controller and a display controller, said system controller compnses: a first video signal processing circuit for decoding regarding a video signal from a camera and obtaining a first video signal; and a processing section connected to an external bus, therefrom supplied preset data is utilized for controlling processing at said first video signal processing circuit, and for performing video processing on said first video signal to provide a video processed video signal, wherein in response to a system startup, said system controller performs a startup process and begins to output said video processed video signal when said startup process completes; and said display controller comprises: a second video signal processing circuit for decoding regarding the video signal from the camera and obtaining a second video signal without video processing, wherein in response to said system startup, said second video signal processing circuit provides said second video signal before said first video signal processing circuit provides said video processed video signal; a selector for selecting either said video processed video signal or said second video signal; an interface for outputting an output of the selector toward a display panel; and a setting section connected to said external bus, therefrom supplied preset data is used for performing various settings; wherein at system startup said display controller performs setting using preset data from a memory section, selects the second video signal by the selector, converts the 2 Appeal2018-004772 Application 13/530, 173 resolution of the second video signal and outputs a video signal, and after the system controller has started up, the first video signal is selected by the selector and the first video signal is supplied to said display. References and Re} ections2 Claims 1---6, 10, and 14--17 stand rejected under pre-AIA 35 U.S.C. Â§ I03(a) as being unpatentable over the collective teachings of Yamada et al. (US 2011/0234802 A 1; published September 29, 2011) ("Yamada") and Matsukawa (US 2010/0066516 Al; published March 18, 2010). Final Act. 3-18. Claims 7-9, 11-13, and 18-20 stand rejected under pre-AIA 35 U.S.C. Â§ I03(a) as being unpatentable over the collective teachings of Yamada, Matsukawa, and Shimizu et al. (US 2006/0287826 Al; published December 21, 2006) ("Shimizu"). Final Act. 18-23. ANALYSIS We disagree with Appellants' arguments, and agree with and adopt the Examiner's findings and conclusions in (i) the action from which this appeal is taken and (ii) the Answer to the extent they are consistent with our analysis below. On this record, the Examiner did not err in rejecting claim 1. I 2 Throughout this opinion, we refer to the (1) Final Rejection dated December 29, 2016 ("Final Act."); (2) Appeal Brief dated August 24, 2017 ("App. Br."); (3) Examiner's Answer dated February 8, 2018 ("Ans."); and (4) Reply Brief dated April 5, 2018 ("Reply Br."). 3 Appeal2018-004772 Application 13/530, 173 Appellants argue the recited limitation "a second video signal processing circuit" would not have been obvious in light ofYamada's teachings. App. Br. 11-18; Reply Br. 2--4. In particular, Appellants argue claim 1 recites both "a first video signal processing circuit" and "a second video signal processing circuit," but Yamada only teaches a single video signal processing circuit, and the Examiner improperly relies on In re Harza, 274 F.2d 669 (CCPA 1960) ("Harza") in determining the recited second video signal processing circuit would have been obvious. See App. Br. 11- 18; Reply Br. 2--4. 3 Appellants have not persuaded us of error. The Examiner finds Yamada teaches the claimed "a first video signal processing circuit" for obtaining a first video signal. See Final Act. 3; Yamada, Fig. 1; ,r 50 ( describing "an image generating unit 3 that generates display images after processing the images"). Appellants do not dispute that finding. The Examiner further finds-and Appellants do not dispute-Yamada teaches a video signal processing circuit for obtaining a second video signal. See Final Act. 4 (citing Yamada, Fig. 1, ,r,r 49-54). The Examiner determines "although Yamada does not explicitly teach a separate processing circuit for a second video signal," the claimed "a second video signal processing circuit" would have been obvious in light ofYamada's teachings under Harza. See Final Act. 4--5. 3 Appellants cite Ex Parte Joseph D. Rippolone, Appeal 2009-015057 (BP AI May 26, 2011) and Ex Parte Brian T Pettey, Appeal 2014-006974 (PTAB July 1, 2016) (App. Br. 12-14, 16; Reply Br. 2), but such cases are not precedential. In any event, those cases are inapplicable here because as discussed below, the claimed "a second video signal processing circuit" is the duplication of a first video signal processing circuit. 4 Appeal2018-004772 Application 13/530, 173 We agree with the Examiner. Similar to the duplication of a rib in Harza, the claimed "a second video signal processing circuit" is the duplication of a first video signal processing circuit, and no "new and unexpected result is produced." See Harza, 274 F.2d at 671 ("The only distinction ... is in the recitation in claim 1 of a plurality of ribs on each side of the web whereas Gardner shows only a single rib on each side of the web. It is well settled that the mere duplication of parts has no patentable significance unless a new and unexpected result is produced."). Therefore, we agree with the Examiner that under Harza, "a second video signal processing circuit" for obtaining a second video signal would have been obvious in light ofYamada's teachings. See id. at 671; Final Act. 4--5. 4 We find unpersuasive Appellants' two arguments that the Examiner improperly relies on the holding in Harza. First, Appellants argue Harza is inapplicable because claim 1 recites "a second video signal processing circuit for ... obtaining a second video signal without video processing" ( emphasis added), but "the output of the first video signal processing circuit/decoder is provided to a processing section." App. Br. 15. Appellants' first argument is unpersuasive, because it is not directed to the Examiner's specific finding. The Examiner cites Matsukawa-not the duplication under Harza-for teaching the claimed "without video processing." See Final Act. 8. 4 The Examiner finds-and Appellants do not dispute-Matsukawa teaches using the camera ECU 5b to obtain a second video signal. See Final Act. 8 ( citing Matsukawa, Fig. 1, ,r 48). And Appellants acknowledge "Matsukawa disclose [a] single video signal processing circuit/decoder." App. Br. 16. Therefore, we observe that Matsukawa teaches the function of a second video signal processing circuit for obtaining a second video signal. 5 Appeal2018-004772 Application 13/530, 173 Second, as to the limitation "wherein in response to said system startup, said second video signal processing circuit provides said second video signal before said first video signal processing circuit provides said video processed video signal" ("Wherein Limitation"), Appellants argue"[t]his is not a mere duplication of parts, but rather is a functional limitation that could, by definition, not be produced by duplicating the same thing. A duplicated image generation unit 3 cannot start up faster than the circuit it was duplication from." App. Br. 18; see also App. Br. 15-16; Reply Br. 2--4. The second argument is unpersuasive because it is not directed to the Examiner's specific findings and conclusions, as the Examiner does not merely cite Harza for teaching the Wherein Limitation. See Final Act. 5. Instead, the Examiner further cites Yamada' s paragraphs 106 and 107, and maps the claimed "system startup" to Yamada's disclosure of activating the image display system 120. See Final Act. 5. The Examiner finds Yamada teaches "[w]hen the image display system 120 is activated, the surrounding confirmation mode Ml appears ... when predetermined time elapses ... the mode automatically is changed to the front mode M2." Final Act. 5 (citing Yamada ,r 107). 5 As discussed above, "a first video signal processing circuit for ... obtaining a first video signal" and "a second video signal processing circuit 5 Yamada explains "[t]he surrounding confirmation mode Ml .. . express[ es] images in animated motion ... The front mode M2 ... displays an image for mainly showing the front and the lateral areas of the vehicle"). Yamada ,r 106. The mode Ml shows the second video signal, and the mode M2 shows the first video signal (Final Act. 5). 6 Appeal2018-004772 Application 13/530, 173 for ... obtaining a second video signal" are taught by or would have been obvious in light of the teachings of Yamada. Further, the Examiner finds Yamada teaches "performing video processing on said first video signal to provide a video processed video signal." See Final Act. 4. Therefore, the Examiner determines the Wherein Limitation would have been obvious in light ofYamada's teachings. See Final Act. 5. Appellants fail to critique the Examiner's specific findings and conclusions, and their attorney arguments (App. Br. 18) do not persuasively show Examiner error. See In re Baxter Travenol Labs., 952 F.2d 388, 391 (Fed. Cir. 1991) ("It is not the function of this court [ or this Board] to examine the claims in greater detail than argued by an appellant, looking for [patentable] distinctions over the prior art."). In addition, Appellants' argument regarding "whether video processed video signal output from a first video processing circuit/decoder and a processing section is selected, or a second video signal output from a second video processing circuit that starts up faster than the first video processing circuit is selected" (App. Br. 18) is unpersuasive, because it is not commensurate with the scope of the Wherein Limitation. II Appellants argue: Claim 1 recites "a first video processing circuit for decoding regarding a video signal from a camera" and "a second video signal processing circuit for decoding regarding the video signal from the camera" .... Adding an extra image generation unit to Yamada would at most provide a different video decoder for a separate camera 7 Appeal2018-004772 Application 13/530, 173 signals .... But ... claim[] 1 ... require[ s] that the two video decoders operate with the same camera signal from the same camera. App. Br. 19. The Examiner responds that Yamada discloses "[t]he shooting unit 5 provides the image signals from all of the on-vehicle cameras 51, 52, 53 to the image generating unit 3." Ans. 24 (citing Yamada, Fig. 1, ,r,r 49-54). The Examiner explains the "first video signal processing circuit" and "second video signal processing circuit" would have received and decoded the same video signal from the camera. Ans. 24--25. Appellants do not dispute the Examiner's explanation. As a result, Appellants have not shown Examiner error. III Appellants argue Yamada does not teach "a selector for selecting either said video processed video signal or said second video signal," as recited in claim 1 (emphasis added). App. Br. 20-23. In particular, Appellants argue Figure 1 of the Specification shows switching circuit 54 as the selector. App. Br. 20. Appellants contend that Yamada discloses "changing operating modes does not require a selector, i.e. a circuit for selecting between different video signals" and Yamada' s Figure 9 "show[ s] a transition between modes, but does not disclose a selector such as a switching circuit for selecting between two video signals." App. Br. 22. In the Reply Brief, Appellants argue the selector is "not the same thing as enabling an operating mode of a duplicated element. It is a physical circuit or tangible electrical operation that is distinct from the items between which 8 Appeal2018-004772 Application 13/530, 173 the selecting takes place" and "is not disclosed in the prior art." Reply Br. 5---6. Appellants have not persuaded us of error. It is well established that during examination, "claims ... are to be given their broadest reasonable interpretation consistent with the specification, and ... should be read in light of the specification," but without importing limitations from the specification. In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004) (citations omitted); SuperGuide Corp. v. DirecTV Enters., Inc., 358 F.3d 870, 875 (Fed. Cir. 2004). The Specification explains "FIG. 1 ... show[s] a configuration of an embodiment." Spec. 3. Therefore, Figure 1 shows a switching gate as a non-limiting, exemplary embodiment of a selector. See Spec. Fig. 1, 5 ( describing the switching gate). And Appellants have not persuasively explained why the broadest reasonable interpretation of the claimed "selector" must be a switching circuit, a circuit, or a physical circuit or tangible electrical operation, as Appellants argue (App. Br. 22; Reply Br. 6). Appellants' remaining arguments are not directed to the Examiner's specific finding. The Examiner maps the claimed "selector" to Yamada' s controller 1. See Final Act. 6; Ans. 25; Yamada ,r 103 ("operating modes can be changed by the control of the controller 1 "). Appellants do not critique that specific finding. Therefore, Appellants have not shown Examiner error. VI In the Reply Brief and for the first time, Appellants argue the Examiner used "improper hindsight reasoning." Reply Br. 4 (original 9 Appeal2018-004772 Application 13/530, 173 emphasis omitted); see also Reply Br. 5---6. Appellants have not provided any argument or evidence of "good cause" for presenting the argument for the first time in the Reply Brief. Accordingly, we determine that this argument is untimely. See 37 C.F.R. Â§ 4I.41(b)(2). Because Appellants have not persuaded us the Examiner erred, we sustain the Examiner's rejection of independent claim 1, and independent claims 5 and 14 for similar reasons. We also sustain the Examiner's rejection of corresponding dependent claims 2--4, 6-13, and 15-20, as Appellants do not advance separate substantive arguments about those claims. DECISION We affirm the Examiner's decision rejecting claims 1-20. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. Â§ 1.136(a)(l)(iv). See 37 C.F.R. Â§ 41.50(Â±). AFFIRMED 10