Ex Parte Venkata Subramanian et al

Patent Trial and Appeal Board

Sep 28, 2017

13443912 (P.T.A.B. Sep. 28, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/443,912 04/11/2012 Ramakrishnan VENKATA SUBRAMANIAN KRAUP198WOUSA 7121
18052 7590 10/02/2017
Eschweiler & Potashnik, LLC
Rosetta Center
629 Euclid Ave., Suite 1000
Cleveland, OH 44114
EXAMINER
TSEGAYE, SABA
ART UNIT PAPER NUMBER
2467
NOTIFICATION DATE DELIVERY MODE
10/02/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing @ eschweilerlaw. com
inteldocs_docketing @ cpaglobal. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RAMAKRISHNAN VENKATA SUBRAMANIAN,
DEEPAK GEORGE, and GULAM MOHAMED
Appeal 2017-005929
Application 13/443,9121
Technology Center 2400
Before JOSEPH L. DIXON, ELENI MANTIS-MERCADER, and
SCOTT E. BAIN, Administrative Patent Judges.
BAIN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 3—7 and 11, which constitute all claims pending in
the application. Claims 1, 2, and 8—10 have been canceled. We have
jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
1 Appellants identify the real party in interest as Lantiq Beteiligungs-GMBH
&Co. KG. App. Br. 2.
Appeal 2017-005929
Application 13/443,912
STATEMENT OF THE CASE
The Claimed Invention
The claimed invention relates to a data switch with reduced memory
requirements, “particularly suitable for use in Ethernet voice communication
devices.” Spec. 1. Claim 3, the sole independent claim, is illustrative of the
invention and the subject matter of the appeal, and reads as follows:
3. A data switch for transmitting data packets including a
destination address, the data switch comprising:
a first ingress/egress port and a plurality of second
ingress/egress ports;
a table storage for storing a table containing associations
between the second ingress/egress ports of the switch and MAC
addresses of any devices connected to the switch via the second
ingress/egress ports while refraining from containing
associations between the first ingress/egress port and MAC
addresses',
a switching fabric, and
a control unit for controlling the switching fabric, the
control unit being arranged, upon receiving a data packet from
any of the second ingress/egress ports having a MAC destination
address which is not stored in the table, to control the switching
fabric to transmit the data packet to the first ingress/egress port.
App. Br. 6 (Claims App.) (emphases added).
The Rejections on Appeal
Claims 3,4, and 11 stand rejected under pre-AIA 35 U.S.C. § 102(e)
as anticipated by Asano et al. (US 7,471,690 B2 Dec. 30, 2008) (“Asano”).
Final Act. 2-4.
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Application 13/443,912
Claims 5—7 stand rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Asano and Kramer et al. (US 6,658,027 Bl; Dec. 2, 2003)
(“Kramer”). Final Act. 4—5.
ANALYSIS
We have reviewed the Examiner’s rejection in light of Appellants’
arguments presented in this appeal. Arguments which Appellants could
have made but did not make in the Briefs are deemed to be waived. See
37 C.F.R. § 41.37(c)(l)(iv). On the record before us, we are unpersuaded
the Examiner has erred. We adopt as our own the findings and reasons set
forth in the rejections from which the appeal is taken and in the Examiner’s
Answer, and provide the following for highlighting and emphasis.
Appellants argue the Examiner erred in finding Asano discloses a
“first ingress/egress port” that satisfies both of the following limitations in
independent claim 3: (i) a control unit arranged to “transmit [a] data packet
to a first ingress/egress port,” upon receiving the data packet from a second
ingress/egress port which has an unrecognized MAC destination address
(i.e., not stored in the recited table storage), and (ii) a table storage for
storing associations between second ingress/egress ports and MAC
addresses while “refraining from containing associations between the first
ingress/egress port and MAC addresses.” App. Br. 3—6 (emphases added);
Reply Br. 2—3. Specifically, Appellants argue that although Asano discloses
multiple “ingress/egress ports,” all such ports are mapped to MAC addresses
in a table “storing associations,” and none of the ports receive a data packet
from a “second ingress/egress port” when the packet lacks a MAC
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Application 13/443,912
destination address. Id. We, however, are not persuaded by Appellants’
arguments.
We first address Appellants’ first disputed limitation (i.e., limitation
(i) as described above). As the Examiner finds, Asano discloses a packet
transfer device with ingress/egress ports. An embodiment of the device is
represented in Asano Figure 3, reproduced below.
Figure 3 is a “block diagram showing an example of the arrangement of the
packet transfer system which is built on an Ethernet. . . MAC address-based
switching system having a plurality of ports,” including packet transfer
device 40 having ports shown as 40-0, 40-1, 40-2, 40-3, 40-4, and 40-5
(corresponding to ports labeled “0 through 5,” respectively). Asano col. 2,
11. 37-40. Ports 0, 1, and 2 are “FAN ports,” connected (via physical layer
devices) to “FAN Segment 600.” Id. at col. 5,11. 43—50. Port 4 is a “WAN
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Appeal 2017-005929
Application 13/443,912
port” connected to “WAN segment 800” (via physical layer device), wherein
“WAN 80 is a global network formed, e.g., by the Internet.” Id. at col. 5,11.
40-41, 58—59. Finally, Port 5 is connected (via physical layer device) to a
microprocessor system 50. Id.at col. 5,1. 35.
The Examiner finds the “first ingress/egress port” of claim 3 disclosed
by port 4 in Asano, and the “second ingress/egress ports” disclosed by ports
0, 1, and 2. Ans. 5—8. As the Examiner finds, Asano discloses that packets
are “transferred from the LAN 60 to the WAN 80,” starting with a “packet
inputted via the port #0, #1, or #2,” via routing by the microprocessor
system 50 (i.e., a control unit “receive[s] a data packet from any of the
second ingress/egress ports,” as recited in claim 3). Asano col. 7,11. 32—35.
Further, as the Examiner finds, if “a packet inputted via the port #0, #1, or
#2 has a destination MAC address which does not correspond to any . . .
address registered in the LAN table area, the packet is transferred to the port
#5 so as to be handled by the microprocessor system 50 as a data packet
having an unidentified destination.” Id. at col. 5,11. 42—47 (emphasis
added). “Handling” by the microprocessor results in the packet being
delivered to WAN 80, via port #4. Id. at col. 5,11. 32—35; Ans. 4, 6—7.
Accordingly, we discern no error in the Examiner’s mapping of Asano
port 4 to the “first ingress/egress port” of claim 3, and ports 0, 1, and 2 to the
“second ingress/egress ports” of claim 3. Appellants argue the Examiner
relies on Asano’s disclosure of packets “inputted” via port 4. App. Br. 4
(citing Asano col. 7,11. 60-63). As described above, however, packets also
are outputted via port 4, in the manner recited in claim 3. Specifically,
Asano discloses a control unit arranged, upon receiving a data packet from a
second ingress/egress port having a MAC destination address not stored in
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Application 13/443,912
the table, to “transmit the data packet to the first ingress/egress port.'” Ans.
4, 6.
Regarding the second disputed limitation, as the Examiner finds,
Asano discloses a MAC address table illustrating no association between
port 4 (see Figure 3, above) and a MAC address. Ans. 5. This MAC
address table is shown in Asano Figure 6, reproduced below.
MAC ADDRESS TABLE
ETHERNET FRAME
DESTINATION
MAC ADDRESS
SOURCE MAC
ADDRESS
PROTOCOL TYPE
DATAGRAM
FCS
DESTINATION
MAC ADDRESS
DESTINATION PORT NUMBER
5 4 3 2 i 0
CPUJWAC_ADR 1 0 0 0 0 0 CPUjMAC.ADR ENTRY
.rrrf rrrr f«vi-tlrrjrtttjlTr i 0 0 0 0 0 DMZ TABLE AREA
<*■1vr rmf mrmfjttkntT 1 0 0 1 1 1
LAN TABLE AREA
PC OF PORT No. 0 0 0 0 0 0 1
PC OF PORT No. t 0 0 0 0 1 0
PC OF PORT No. 2 0 0 0 i 0 0
' • ■ ■ ■ ■
FIG. 6
Figure 6 is a block diagram of a MAC address table used by the
packet transfer device shown in Figure 3, above, in which destination port
numbers 5, 4, 3,2, 1, and 0 are (or are not), respectively, registered to
destination and source MAC addresses. Asano col. 6,11. 37 40. As shown
in Figure 6, Asano port 4 — which the Examiner finds is the “first
ingress/egress port” of claim 3 (see supra) — is not mapped to any MAC
address. Id. (column pertaining to port 4 includes all “0’s,” which one of
ordinary skill in the art would understand as no mapping); Ans. 6—7.
Accordingly, as in claim 3, the MAC address table “refrain[s] from
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Appeal 2017-005929
Application 13/443,912
containing associations between the first ingress/egress port and MAC
addresses.” Id.
Appellants argue a different section of Asano discloses “the MAC
address of a node . . . connected to each port is registered in association with
the port number.” Reply Br. 2 (citing Asano col. 6,11. 35—39). Appellants,
therefore, argue there is no “refraining” of association between first
ingress/egress port and MAC addresses. This general statement about the
function of the MAC look-up device, however, does not supersede Asano’s
more specific teachings discussed above. See supra', Ans. 5—7.
For the foregoing reasons, we discern no error in the Examiner’s
rejection of claim 3 as anticipated by Asano. Accordingly, we sustain the
anticipation rejection of claim 3, and its dependent claims 4 and 11 which
were not argued separately. Appellants also do not argue any of the
remaining claims separately. Accordingly, we sustain the obviousness
rejections of claims 5—7 for the same reasons.
DECISION
We affirm the Examiner’s rejections of claims 3—7 and 11.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 41.50(f).
AFFIRMED
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