Ex Parte Van Assche et al

Patent Trial and Appeal Board

Dec 18, 2017

13075488 (P.T.A.B. Dec. 18, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/075,488 03/30/2011 Gilles Van Assche 09-ZV2-409 (813063.414) 1805
38106 7590 12/20/2017
Need TP T aw Orniin T T P/NT fFP ORTOTNATTNOT
EXAMINER
701 FIFTH AVENUE, SUITE 5400
SEATTLE, WA 98104-7092
SAVLA, ARPAN P
ART UNIT PAPER NUMBER
2138
NOTIFICATION DATE DELIVERY MODE
12/20/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
US PTOe Action @ S eedIP .com
pairlinkdktg @ seedip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GILLES VAN ASSCHE and RONNY VAN KEER
Appeal 2017-003414
Application 13/075,488
Technology Center 2100
Before JUSTIN BUSCH, TERRENCE W. McMILLIN, and
SCOTT B. HOWARD, Administrative Patent Judges.
BUSCH, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection
of claims 1, 3-11, 13-16, 20-23, 26-30, and 34-38. We have jurisdiction
under 35 U.S.C. § 6(b).
We reverse.
CLAIMED SUBJECT MATTER
Claims 1,10, and 26 are independent claims. The claims relate to a
particular method used for reading from and writing to an atomicity
memory. Spec. 1:11-15. Atomicity memories are used for writing atomic
transactions, which are transactions involving multiple memory cells that
require all of the memory cells affected to either be in a state after
completion of the entire atomic transaction or in a state they were in before
Appeal 2017-003414
Application 13/075,488
beginning the atomic transaction. Id. at 1:18-27. In other words, if the
atomic transaction is interrupted, the memory cells affected by the
transaction and already altered must revert to storing the data that was stored
prior to the beginning of the atomic transaction. Id. In particular, the
claimed invention uses a marking pattern to indicate or identify the
beginning of data when writing to or reading from an atomicity memory. Id.
at 4:19-25, 4:30-5:6. Claim 1 is reproduced below:
1. A method, comprising:
writing a plurality of data sets to a reprogrammable
non-volatile memory using circular addressing, each data
set including a marking pattern comprising a plurality of
bits to mark a write-start address of the data set and
respective data, the writing of a respective data set of the
plurality including:
randomly selecting a starting address in the
reprogrammable non-volatile memory;
writing the marking pattern comprising the
plurality of bits to the reprogrammable non-volatile
memory; and
writing the data of the data set to the
reprogrammable non-volatile memory, wherein the
data set comprising the marking pattern and
respective data is written to a plurality of addresses
starting from the starting address, with the marking
pattern being at a beginning of the set and identical
for each data set of the plurality of data sets.
REJECTIONS
Claims 1, 3-7, 10, 11, 13-16, 23, 26-30, and 38 stand rejected under
35 U.S.C. § 103(a) as obvious in view of Sepe (US 2009/0013122 Al;
Jan. 8, 2009) and Chang (US 2008/0222350 Al; Sept. 11, 2008). Final
Act. 2-10.
2
Appeal 2017-003414
Application 13/075,488
Claims 8, 9, 20, 21, and 34-37 stand rejected under 35 U.S.C.
§ 103(a) as obvious in view of Sepe, Chang, and Andre (US 2006/0106751
Al; May 18, 2006). Final Act. 10-13.
Claim 22 stands rejected under 35 U.S.C. § 103(a) as obvious in view
of Sepe, Chang, and Ruby (US 2010/0039860 Al; Feb. 18, 2010). Final
Act. 13.
ANALYSIS
The Examiner rejects each of the independent claims as obvious in
view of Sepe and Chang. Final Act. 2-10. In particular, the Examiner finds
Sepe discloses each of the recited limitations in claims 1,10, and 26, except
“Sepe does not expressly disclose randomly selecting a starting address in
the reprogrammable non-volatile memory,” as recited in independent claim
1 and commensurately recited in independent claims 10 and 26. Final
Act. 3, 5, 8. The Examiner finds Chang discloses the randomly determining
a starting address steps not taught by Sepe, and provides a rationale for
combining Sepe and Chang. Id. at 3, 5-6, 8. Of particular note, the
Examiner finds Sepe’s ‘“begin transaction marker’ is equivalent to a
‘marking pattern,’” and finds Sepe teaches writing the data set, which
includes the marking pattern and data, to the memory using circular
addressing, “wherein the data set. . . is written to a plurality of addresses
starting from the starting address, with the marking pattern being at the
beginning of the set,” as recited in the independent claims. Id. at 2-3, 5-8
(citing Sepe 40, 41, 46, 47, Fig. 3b).
Among other arguments, we understand Appellants’ first argument as
asserting that Sepe’s begin transaction marker does not teach or suggest the
recited begin transaction marker. Specifically, Appellants contend Sepe’s
3
Appeal 2017-003414
Application 13/075,488
begin transaction marker is stored in an Index buffer separate from the Data
buffer in which the data is stored such that Sepe’s begin transaction marker
is not “a pattern which is written into the data buffer of the transaction stack
of Sepe and the data buffer of the transaction stack 2 does not appear to
contain data sets comprising” the marker and the “respective data written to
a plurality of addresses starting from a starting address of the data set.”
App. Br. 19; see also Reply 3 (“The claim requires that the data sets are
‘ [written] to a reprogrammable non-volatile memory using circular
addressing,’ and that ‘each data set including [the] marking pattern
comprising a plurality of bits to mark a write-start address of the data set and
respective data.’” (brackets in original)).
The Examiner finds “there is no requirement in the claims that the
marking pattern be in the same buffer as the [respective] data itself, so long
as the marking pattern is before the respective data, which is the case in
Sepe.” Ans. 4 (citing Sepe Fig. 3b) (brackets in original). The Examiner
further finds “the transaction stack in Sepe does in fact contain both the
‘begin transaction marker’ and the respective data, even though they are in
different buffers within the transaction stack.” Id. (citing Sepe Abstract,
Fig. 3b).
Sepe discloses using four buffers to store various information related
to atomic transactions, which Sepe refers to as Secure updates. Sepe ^ 57.
Specifically, Sepe uses a Backup Data buffer to store the original values of
the memory addresses being updated, an Index buffer to store index entries
that “link Address-Length entries in the Address-Length buffers to the
Backup Data entries,” and Address and Length buffers that “are substantially
aligned” for storing the address and length of each entry in the Backup Data
4
Appeal 2017-003414
Application 13/075,488
buffer. Id. 57-61. When executing a Secure update, Sepe “initializes a
begin transaction marker for establishing that. . . only the entries stored after
the begin transaction marker are used as original values of persistent data
involved in the update operation.” Id. 46, Figs. 3, 4.
We agree with Appellants that the Examiner has not sufficiently
explained how Sepe’s begin transaction marker teaches or suggests the
recited marking pattern or, more specifically, writing the data set, which
includes the marking pattern and respective data, as recited in the
independent claims. Sepe’s begin transaction marker, which the Examiner
finds teaches the recited marking pattern, is not in the same buffer as Sepe’s
backup data, which the Examiner finds teaches the recited respective data.
See Sepe ^ 57. The Examiner implicitly acknowledges this fact. See Ans.
3—4. Accordingly, we find problematic the Examiner’s conclusory finding
that Sepe’s “marking pattern is before the respective data” because the
Examiner provides no explanation why Sepe’s marking pattern would be
before the respective data when they are stored in different buffers. We also
find problematic the Examiner’s finding that Sepe’s transaction stack
contains “both the ‘begin transaction marker’ and the respective data, even
though they are in different buffers,” Ans. 4 (citing Sepe Fig. 3b), because
Figure 3b of Sepe does not depict the begin transaction marker. Sepe Fig.
3b. Sepe illustrates the begin transaction marker in Figures 4b 4q in the
Index buffer that is aligned with the Address and Length buffers. Sepe
neither depicts nor describes a relationship, however, between the location
of the Address, Length, and Index buffers and the transaction stack. See
Sepe 40-65, Figs. 3, 4.
5
Appeal 2017-003414
Application 13/075,488
Thus, confined by this record, we are persuaded the Examiner erred in
rejecting the independent claims as obvious. For the reasons discussed
above, we do not sustain the Examiner’s rejection of claims 1, 3-7, 10, 11,
13-16, 23, 26-30, and 38 as under 35 U.S.C. § 103(a) as obvious in view of
Sepe and Chang. Because the Examiner does not rely on either Andre or
Ruby to cure the deficiency discussed above, we also reverse the rejections
of claim 22 as obvious in view of Sepe, Chang, and Ruby and claims 8, 9,
20, 21, and 34-37 as obvious in view of Sepe, Chang, and Andre.
DECISION
We reverse the Examiner’s decision to reject claims 1, 3-11, 13-16,
20-23, 26-30, and 34-38 under 35 U.S.C. § 103(a).
REVERSED
6