Ex Parte Tsvetkov et al

Patent Trial and Appeal Board

Aug 10, 2017

13511781 (P.T.A.B. Aug. 10, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/511,781 05/24/2012 Mikhail S. Tsvetkov ITL.2222US (P32708US) 5020
47795 7590 08/14/2017
TROP, PRUNER & HU, P.C.
1616 S. VOSS RD., SUITE 750
HOUSTON, TX 77057-2631
EXAMINER
BECK, LERON
ART UNIT PAPER NUMBER
2487
NOTIFICATION DATE DELIVERY MODE
08/14/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
tphpto@tphm.com
Inteldocs_docketing @ cpaglobal.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MIKHAIL S. TSVETKOV, ANDREY EFIMOV,
and
EUGENIY A. BELYAEV1
Appeal 2017-004694
Application 13/511,781
Technology Center 2400
Before CARLA M. KRIVAK, HUNG H. BUI, and JON M. JURGOVAN,
Administrative Patent Judges.
KRIVAK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1—3, 5—13, and 15—25, which are all the claims
pending in the application.2 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
1 Appellants indicate that Intel Corporation is the real party in interest.
2 The Examiner rejects claims 1—3 and 5—25 under 35 U.S.C. § 103, and
Appellants’ Argument heading identifies the same claims. However, claim
14 has been cancelled by the Advisory Action entering the Amendment
After Final mailed April 7, 2016. We consider this incorrect reference to
claim 14 by both the Examiner and Appellants to be harmless error.
Appeal 2017-004694
Application 13/511,781
STATEMENT OF THE CASE
Appellants’ invention is directed to methods and systems for
“displaying decompressed pictures on liquid crystal displays in macroblock
raster scan order” (Title (capitalization altered); Spec. 1:5—6).
Independent claim 1, reproduced below, is exemplary of the subject
matter on appeal.
1. A method comprising:
directly showing a picture on a thin film transistor liquid
crystal display in macroblock scan order; and
converting the macroblock scanned decoded stream into a
scanned format used by the liquid crystal display without using
a frame buffer by sending macroblock interface signals in the
form of clock, data, data enable, and macroblock address wherein
the macroblock address is the index of the macroblock in a
macroblock raster scan to said display.
REFERENCES and REJECTIONS
(1) The Examiner rejected claim 1 under 35U.S.C. § 112, first
paragraph, as failing to comply with the written description requirement.
(2) The Examiner rejected claims 1—3, 5—13, and 15—25 under
35 U.S.C. § 103(a) based upon the teachings of Maclnnis (EP 1478186 A2;
published Nov. 17, 2004), Abe (US 2007/0045659 Al; published Mar. 1,
2007), andPau (US 5,986,711; issued Nov. 16, 1999).3
3 The Examiner refers to the Maclnnis reference as “Mclnnis” (see Final
Act. 4).
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Application 13/511,781
ANALYSIS
Rejection under 35 U.S.C. § 112, first paragraph
The Examiner rejected claim 1 under 35 U.S.C. § 112, first paragraph,
as failing to comply with the written description requirement (Final Act. 3).
Appellants did not address this rejection in the Briefs. Thus, we summarily
sustain the Examiner’s rejection of claim 1 under 35 U.S.C. § 112, first
paragraph. SeeMPEP § 1205.02; 37 C.F.R. §§ 41.37(c)(l)(iv)
and 41.39(a)(1).
Rejection under 35 U.S.C. §103
With respect to claim 1, Appellants contend the Examiner’s reliance
on Abe is misplaced because “Abe has no reasonable correlation to the
claimed invention since it has to do with macroblock circuit elements not
macroblock scan order or converting a macroblock scanned decoded
stream,” as claimed (App. Br. 7; Reply Br. 2).4 Appellants assert Abe’s
macroblocks “are explicitly high speed interface circuit blocks formed as a
‘macroblock’ including a ‘pad region’,” having “nothing to do with the
‘macroblock’ set forth in the claims” (App. Br. 7 (citing Abe 65, 108;
Spec. 3:15—17)). Appellants further argue Abe and Maclnnis cannot be
combined because Abe’s “macroblock circuit” is “a circuit element
unrelated to [Maclnnis’] macroblock chunks of data” (Reply Br. 1). As
such, Appellants argue the combination of Maclnnis with Abe—relied upon
for the claimed “macroblock interface signals in the form of clock, data, data
4 Appeal Brief citations are to the Appeal Brief filed on August 29, 2016,
while citations to claim language are to the claims as presented in the
Supplemental Appeal Brief filed on October 7, 2016.
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Application 13/511,781
enable, and macroblock address” (see Final Act. 4—5)—does not teach or
suggest claim 1 (Reply Br. 1—2). We do not agree.
We agree with and adopt the Examiner’s findings as our own.
Particularly, we agree with the Examiner that Maclnnis discloses “directly
showing a picture on a display in macro block scan order,” and “[converting
the macroblock scanned decoded stream” using “macroblock interface
signals in the form [of] macroblock address, wherein the macroblock address
is the index of the macroblock in a macroblock raster scan,” as claimed
(Final Act. 4 (citing Maclnnis ^fl[ 26, 33, Fig. 3) (emphasis omitted)).
Appellants’ argument that Abe does not disclose “macroblock scan order or
converting a macroblock scanned decoded stream” (App. Br. 7) is
conclusory and does not address the Examiner’s findings with respect to
Maclnnis or explain why or how the Examiner erred. See 37 C.F.R.
§41.37(c)(l)(iv).
We further agree with the Examiner that a skilled artisan would know
“how to define the form of the macroblock interface that transmits data”
(Ans. 9). In particular, the skilled artisan would know that interface signals
in the form of clock, data, and data enable are necessary to enable display of
data from decoded macroblocks. Appellants’ Specification confirms that
clock, data, and data enable signals are required to transmit data in line scan
order to a display (see Spec. 1:7—15, 1:31—2:1).5 Thus, as Appellants’
5 Appellants’ Specification provides “[i]n conventional liquid crystal
display systems, an FPD-link interface is used,” and the “FPD-link interface
couples a decoder, such as an H.264 decoder, to the liquid crystal control
logic .... the decoder has to use a frame buffer to convert the macroblock
scanned decoded stream to a line scanned flat panel display stream” (Spec.
1:7—15 (emphasis added)). The Specification further provides the “FPD-link
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Application 13/511,781
Specification explains, clock and data enable interface signals are used by
the FPD[flat panel display]-link interface to “couple[] a decoder ... to the
liquid crystal control logic” for “driv[ing] a thin film transistor (TFT)
display liquid crystal display” (see Spec. 1:10-13, 1:31—2:1).
Thus, we agree with the Examiner that modifying MacTnnis’
macroblock address interface signals to further include interface signals in
the form of clock, data, and data enable would have been obvious to those
skilled in the art as a use of a known technique to transmit displayable data
for predictable results (Final Act. 4—5; Ans. 9). See KSR Int’l Co. v. Teleflex
Inc., 550 U.S. 398, 416 (2007) (“[A] combination of familiar elements
according to known methods is likely to be obvious when it does no more
than yield predictable results.”). In conclusion, we find the weight of the
evidence supports the Examiner’s ultimate legal conclusion of obviousness,
and we sustain the Examiner’s rejection of independent claim 1, independent
claims 10 and 20 argued for substantially the same reasons as claim 1, and
is a low voltage differential signaling (LVDS) bus that is used to transmit
data pixel-by-pixel in line scan order with a bundled clock, data enable,
vertical, and horizontal synchronization signals” (Spec. 1:31—2:1 (emphasis
added)).
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Application 13/511,781
dependent claims 2, 3, 5, 7—9, 11—13, 15, 17—19, and 22—24 for which no
separate arguments are provided (App. Br. 7).6 7
With regard to claim 25 (depending from independent claim 20),
Appellants provide substantially the same arguments as for claims 1 and 20,
6 In the event of any further prosecution, we suggest the Examiner consider
rejecting independent claim 1, and similarly, independent claim 20, under 35
U.S.C. § 112, second paragraph, as being indefinite and incomplete because
the claim is unclear as to: (1) how the first recited step of “directly showing
a picture on a thin film transistor liquid crystal display in macroblock scan
order” can be performed before the second recited step of “converting the
macroblock scanned decoded stream into a scanned format used by the
liquid crystal display;” and (2) any relationship between the first and second
steps. Regarding issue (1), the step of “directly showing a picture on a thin
film transistor liquid crystal display in macroblock scan order” appears to
require the second step of “converting the macroblock” for the liquid crystal
display; that is, the first step cannot be performed before the second step is
performed, as indicated by Appellants’ Figure 3. Regarding issue (2), the
second step of “converting” does not recite a relationship with the first step
of “directly showing a picture.” Additionally, there is no antecedent basis
for “the macroblock scanned decoded stream.”
7 In the event of any further prosecution, we also suggest the Examiner
consider rejecting independent claims 10 under 35 U.S.C. § 112, second
paragraph, as being indefinite for combining two classes of invention by
adding an apparatus limitation (“a decoder”) to a method claim (“A method
comprising: . . . converting the macroblock”). See IPXL Holdings, L.L.C. v.
Amazon.com, Inc., 430 F.3d 1377, 1384 (Fed. Cir. 2005) (holding invalid a
claim covering both a system and a method as a “hybrid” claim); see also In
re Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303, 1318
(Fed. Cir. 2011); Ex parte Miyazaki, 89 USPQ2d 1207, 1211 (BPAI 2008)
(precedential) (“[I]f a claim is amenable to two or more plausible claim
constructions, the USPTO is justified in requiring the applicant to more
precisely define the metes and bounds of the claimed invention by holding
the claim . . . indefinite.”); Rembrandt Data Techs., LP v. AOL, LLC, 641
F.3d 1331 (Fed. Cir. 2011) (“[Rjeciting both an apparatus and a method of
using that apparatus renders a claim indefinite under section 112, paragraph
2 [pre-AIA].”).
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Application 13/511,781
and further argue Abe does not teach “a macroblock address that is an index
of the macroblock in a macroblock raster scan” (App. Br. 8). As discussed
supra with respect to claims 1 and 20, we agree with the Examiner that the
cited combination of references teaches and suggests the claimed
macroblock interface signals in the form of clock, data, and data enable.
Appellants’ arguments also do not address the Examiner’s specific findings
that Maclnnis discloses that a macroblock address is an index of the
macroblock in a macroblock raster scan (Ans. 9 (citing Maclnnis ^fl[ 26, 33,
Fig. 3); Final Act. 4). As Appellants’ arguments do not persuade us of
Examiner error in rejecting claim 25, we sustain the Examiner’s rejection of
claim 25.
With respect to dependent claim 6, Appellants argue “[tjhere is no
reason to believe that the decoder in Figure 1 of Abe is a macroblock
address decoder,” as claimed (App. Br. 7). Appellants’ argument, however,
does not address the Examiner’s specific findings that the skilled artisan
“would be able to derive a macroblock address decoder” from Pau’s Figure
1, which discloses a video decoder accessing “unique internal memory of 16
bits, which is address information” and decoding videos that include
macroblocks (Ans. 10 (citing Pau, Fig. 1)). We agree with the Examiner’s
reasonable findings. Accordingly, Appellants’ arguments do not persuade us
of error in the Examiner’s rejection of claim 6.8
8 In the event of any further prosecution, we suggest the Examiner consider
rejecting dependent claim 6 under 35U.S.C. § 112, second paragraph, as
being indefinite because the claim is unclear as to any relationship between
the claimed “macroblock address decoder in [claim 5’s] liquid crystal
control logic,” and the step limitations recited in claim 1. For example,
claim 6 (and its base claim 5) does not specify whether the macroblock
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Application 13/511,781
Therefore, we sustain the Examiner’s rejection of claim 6, and claims
16 and 21 argued together (App. Br. 7).
DECISION
The Examiner’s decision rejecting claim 1 under 35 U.S.C. § 112,
first paragraph is affirmed.
The Examiner’s decision rejecting claims 1—3, 5—13, and 15—25 under
35 U.S.C. § 103 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
address decoder acts on any of the signals recited in claim 1.
8