Ex Parte Tilke et al

Patent Trial and Appeal BoardSep 28, 2018

13686343 (P.T.A.B. Sep. 28, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/686,343 11/27/2012 25281 7590 10/02/2018 DICKE, BILLIG & CZAJA FIFTH STREET TOWERS 100 SOUTH FIFTH STREET, SUITE 2250 MINNEAPOLIS, MN 55402 UNITED ST A TES OF AMERICA FIRST NAMED INVENTOR Armin Tilke UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. I56l.l09.102/2005P50471US 2397 EXAMINER PIZARRO CRESPO, MARCOS D ART UNIT PAPER NUMBER 2814 NOTIFICATION DATE DELIVERY MODE 10/02/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): USPTO.PA TENTS@dbclaw.com dmorris@dbclaw.com DBCLA W-Docket@dbclaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ARMIN TILKE, 1 Jiang Yan, and Matthias Hierlemann Appeal2018-002913 Application 13/686,343 Technology Center 2800 Before ADRIENE LEPIANE HANLON, MARK NAGUMO, and JAMES C. HOUSEL, Administrative Patent Judges. NAGUMO, Administrative Patent Judge. DECISION ON APPEAL Infineon Technologies AG ("Tilke") timely appeals under 35 U.S.C. Â§ 134(a) from the Final Rejection2 of claims 1-3, 5-7, 24, 25, 34, 36-39, and 41. 3 We have jurisdiction. 35 U.S.C. Â§ 6(b). We reverse. 1 The applicant under 37 C.F.R. Â§ 1.46, and hence the appellant under 35 U.S.C. Â§ 134, is the real party in interest, identified as Infineon Technologies AG. (Appeal Brief, filed 16 October 2017 ("Br."), 3.) 2 Office Action mailed 18 May 2017 ("Final Rejection"; cited as "FR"). 3 Remaining copending claims 8-23 have been withdrawn from consideration by the Examiner (FR 1, Â§ 5a), and are not before us. Appeal2018-002913 Application 13/686,343 A. Introduction 4 OPINION The subject matter on appeal relates to Complementary Metal Oxide Semiconductor ("CMOS") technology used especially in sub-250 nm ultra large-scale integrated ("ULSI") circuits formed on silicon-on-insulator ("SOI") substrates. (Spec. 1.) Generally, CMOS technology is said to use silicon substrates having a crystal orientation of ( 100), which provides low surface state density and high [ negatively charged] electron mobility in the (100) plane, and which allows high performance n-type field effect transistors ("nFETs"). (Id.) The mobility of holes in the (100) plane, however, is significantly less. (Id.; see also Zhu5 1 [0005].) In contrast, silicon substrates having a crystal orientation of ( 110) are said to be optimal for high [positively charged] hole mobility, which allows high performance p-type field effect transistors ("pFETs"). (Spec. 1.) The mobility of electrons in the (110) plane, however, is significantly less. (Id.; see also Zhu 1 [0005].) Tilke seeks patent protection for SOI devices that provide optimal crystal orientation for substrates depending on the device, e.g., (100) silicon for nFETs, and (110) silicon for pFETs. An embodiment of an SOI device is illustrated in Figure 1, reproduced on the following page. 4 Application 13/686,343, Silicon-on-insulator chip having multiple crystal orientations, filed 27 November 2012 as a division of 11/315,069, filed 22 December 2005, now U.S. Patent No. 8,319,285 (issued 27 November 2012). We refer to the '"343 Specification," which we cite as "Spec." 5 Full cite infra at 4 n.10. 2 Appeal2018-002913 Application 13/686,343 t:QÂ· 0 \ ~-- {Figure 1 is shown below} 54 66 _) {Figure 1 shows a cross section of SOI device 50 having two silicon substrate regions 64 and 66, having different crystalline orientations} SOI device 50 6 comprises a substrate 58; an insulating layer 60; a first chip component 54 (e.g., an nFET) having a silicon (100) stratum 64 that contacts directly insulating layer 60; and a second chip component 56 (e.g., a pFET) having a ( 110) silicon stratum 66 that directly contacts strain inducing dielectric layer 90 [ unlabeled; see Figures 5-11, not reproduced here], which in tum directly contacts insulating layer 60. Distinct silicon crystal layers 64 and 66 are separated by isolation trench 68. Claim 1 is representative and reads: A silicon-on-insulator device [50] having multiple crystal orientations comprising: a substrate layer [58]; an insulating layer [60] disposed on the substrate layer [58]; 6 Throughout this Opinion, for clarity, labels to elements are presented in bold font, regardless of their presentation in the original document. 3 Appeal2018-002913 Application 13/686,343 a first strained silicon layer [64] having a first crystal orientation [100] disposed directly on a portion of the insulating layer [ 60]; a strain inducing layer [90] comprising a strained material disposed directly on another portion of the insulating layer [60]; and a second strained silicon layer [ 66] disposed directly on the strain inducing layer [90] and having a crystal orientation [ 11 OJ different from the first crystal orientation [ 100]. (Claims App., Br. 13; some indentation, paragraphing, emphasis, bracketed labels to elements shown in the Figures and to exemplary crystal orientations added.) The Examiner maintains the following grounds of rejection 7, s, 9 : A. Claims 1-3, 5-7, 25, 34, 36, 39 and 41 stand rejected under 35 U.S.C. Â§ I03(a) in view of the combined teachings of Zhu 10 and Chidambarrao. 11 7 Examiner's Answer mailed 27 December 2017 ("Ans."). 8 Because this application was filed before the 16 March 2013, effective date of the America Invents Act, we refer to the pre-AIA version of the statute. 9 A rejection of certain claims under 35 U.S.C. Â§ 112(2) has been withdrawn. (Ans. 2-3, Â§ 4.) 10 Huilong Zhu et al., Structure and method for manufacturing planar SOI substrate with multiple orientations, U.S. Patent Application Publication 2006/0003554 Al (2006), based on an application filed 30 June 2004. 11 Dureseti Chidambarrao et al., Dual stressed SOI substituents, U.S. Patent No. 7,262,087 B2 (2007), based on an application filed 14 December 2004. 4 Appeal2018-002913 Application 13/686,343 Al. Claim 24 stands rejected under 35 U.S.C. Â§ I03(a) in view of the combined teachings of Zhu, Chidambarrao, and Karlsson. 12 A2. Claims 37 and 38 stand rejected under 35 U.S.C. Â§ I03(a) in view of the combined teachings of Zhu, Chidambarrao, and de Souza. 13 B. Discussion The Board's findings of fact throughout this Opinion are supported by a preponderance of the evidence of record. The Examiner finds that Zhu, in Figure 12, shown below, describes 1----22--, r------------24-----, {Zhu Figure 12 shows in cross sectional drawing of SOI substrate 50 with nFET 22 and pFET 24} an SOI device having multiple crystal orientations. More particularly, the Examiner finds that silicon layer 16 has crystal orientation (100), and is disposed directly on insulating layer 33, while silicon layer 26 has crystal orientation (110), and is disposed on material layer 27. (FR 4--5, ,r 12.) 12 Olov B. Karlsson et al., Shallow trench isolation (ST!) region with high-k liner and method of formation, U.S. Patent No. 6,657,276 Bl (2003). 13 Joel P. de Souza et al., Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template lasers, U.S. Patent Application Publication 2005/0116290 Al (2005). 5 Appeal2018-002913 Application 13/686,343 Critically, the Examiner finds that Zhu does not disclose that material layer 27 comprises a strained material. (Id. at 5, ,r 13.) The Examiner finds that Chidambarrao "teaches that a strained layer would improve the performance of Zhu's transistors." (Id., citing Chidambarrao, col. 1, 1. 60- col. 2, 1. 1.) More specifically, the Examiner finds that Chidambarrao would have taught a person having ordinary skill in the art to use "underlying strained dielectric layers like the material layer 27 of Zhu to cause a strain in the overlying silicon regions." (Id. at 6, ,r 16.) Thus, the Examiner concludes, "it would have been obvious ... to have the material layer of Zhu comprising a strained material inducing a strain, as suggested by Chidambarrao, to improve the performance of the transistor." (Id. at ,r 17.) As Tilke points out, Zhu teaches that material layer 27 is a thermal oxide layer, preferably Si 02, "having a thickness ranging from about 10 nm to about 15 nm" (Zhu 4 [0046]), that is "applied on a surface of an already grown strained second semiconductor layer 26 ( see transition from Figure 5 to Figure 6)." (Br. 8, 1st full para.) The Examiner has not directed our attention to any evidence that Zhu provides any indication that material layer 27 is suitable for causing strain in an adjacent silicon crystal layer. Tilke also directs our attention to Chidambarrao' s teachings that strained silicon layers 11 and 12 are deposited on already formed strained dielectric layers 13 and 14, and contrasts this procedure with the teachings of Zhu, which forms material layer 27 after forming strained silicon layers. (Br., para. bridging 8-9.) Tilke urges that the detailed process of making the device shown in Chidambarrao Figure 1 (shown below), illustrated in Figures 4A--4C, and summarized at column 2, lines 21---62, demonstrate further the lack of persuasive merit in the appealed rejection. 6 Appeal2018-002913 Application 13/686,343 Indeed, Chidambarrao teaches that, in the preferred embodiment of the disclosed invention, "the compressively strained and tensile strained dielectric layers 13, 14 are silicon nitride (ShN4) and have a thickness ranging from 50 nm to about 150 nm." (Chidambarrao col. 5, 11. 52-54.) Notably, dielectric layers 13 and 14 are much thicker (50-150 nm) than material layer 27 (10-15 nm). Dielectric layers 13 and 14, with overlying silicon layer 30, are shown in Figure 4a, which is reproduced below. 30Â·Â·Â· 1 Â·c3 . ( l l1 1 _ _....17 1--------------------~ lO {Chidambarrao Figure 4a shows a stage of making an SOI device comprising an nFET and a pFET} Moreover, Chidambarrao teaches that it is the formation of isolation region 5, separating compressively stressed layer 13 from tensilely stressed layer 14, as shown in Figure IA, below, that "allows the strained dielectric { 3. l 5 10 1-~---;~o ----~ {Figure IA shows an SOI device with nFET 25 and pFET 26 separated by isolation region (trench) 5} 7 Appeal2018-002913 Application 13/686,343 layers 13, 14 to transfer the opposite sign strain into the overlying semiconductor layer 30." (Id. at 9, 11. 43--46, describing steps conducted after Figure 4C.) In other words, Chidambarrao indicates that deposition of silicon layer 30 and compressively strained substrate 13 and tensilely strained substrate 14 does not result in the formation of ( 100)- and ( 110)- silicon until the two regions have been separated by isolation trench 5. The Examiner is correct to assume, implicitly, that substituting one substance for another substance known to have similar properties and reasonably expected to function in a similar manner is often prima facie obvious. The difficulty here, however, is that the Examiner has not shown by a preponderance of the evidence that it would have been thought that material layer 27, which is deposited on silicon layer 26, is reasonably similar in structure or function to strained dielectric layers 13, 14, such that the substitution would have been useful. The Examiner makes no findings regarding the remaining claims and references that cure these defects. We therefore reverse the appealed rejections. C. Order It is ORDERED that the rejection of claims 1-3, 5-7, 24, 25, 34, 36- 3 9, and 41 is reversed. REVERSED 8