Ex Parte Tang et al

Patent Trial and Appeal BoardJan 11, 2019

15087892 (P.T.A.B. Jan. 11, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 15/087,892 03/31/2016 83515 7590 01/15/2019 AL TERA CORPORATION C/0 FLETCHER YODER PC P.O.BOX 692289 HOUSTON, TX 77269-2289 FIRST NAMED INVENTOR Lai Guan Tang UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. A04886 (ALTR:0039) 8818 EXAMINER CHEN, PATRICK C ART UNIT PAPER NUMBER 2842 NOTIFICATION DATE DELIVERY MODE 01/15/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docket@fyiplaw.com hill@fyiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte LAI GUAN TANG, KRIS DEHNEL, and BENOIT HERVE Appeal2018-005037 Application 15/087,892 Technology Center 2800 Before TERRY J. OWENS, DEBRA. L. DENNETT, and MERRELL C. CASHION, JR., Administrative Patent Judges. CASHION, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF CASE This is an appeal under 35 U.S.C. Â§ 134(a) from the final rejection of claims 8-20. 1 We have jurisdiction under 35 U.S.C. Â§ 6(b). We reverse. 1 We note that claims 1-7 are directed to allowable subject matter. Final Act. 8; App. Br. 2. Appeal2018-005037 Application 15/087,892 The claimed invention provides an efficient manner in which to specify a voltage output of a voltage regulator device through an integrated circuit that uses a duty cycle of a pulsed signal to specify to a voltage regulator a voltage output level. App. Br. 3. The integrated circuit may also generate a pulsed signal having a particular duty cycle based on a temperature surrounding the integrated circuit and voltage level adjustments as indicated by blown fuses. Id. at 3--4. Claims 8 and 15 illustrate the invention: 8. A system, comprising: an integrated circuit device that generates a pulsed signal having a particular duty cycle that is selected from a group of defined duty cycles; and a voltage regulator circuit that is coupled to the integrated circuit device via a single control wire and receives the pulsed signal having the particular duty cycle from the integrated circuit device via the single control wire, wherein the voltage regulator circuit generates a voltage supply signal that corresponds to the particular duty cycle of the pulsed signal by decoding the pulsed signal to determine a particular voltage level that corresponds to the particular duty cycle. 15. A method for operating an integrated circuit device to control a voltage regulator circuit, the method comprising: using the integrated circuit device, generating a pulsed signal having a particular duty cycle that is based on information on temperature associated with the integrated circuit device and one or more voltage level adjustments based on one or more blown fuses within the integrated circuit device; and 2 Appeal2018-005037 Application 15/087,892 using the integrated circuit device, transmitting the pulsed signal having the particular duty cycle to the voltage regulator. Appellant2 requests review of the following rejections maintained by the Examiner: I. Claims 8-11, 13, and 14 rejected under 35 U.S.C. Â§ I02(a)(2) as anticipated by Nene (US 2016/0164500 Al, published June 9, 2016). II. Claim 12 rejected under 35 U.S.C. Â§ 103 as unpatentable over Nene. III. Claims 15-20 rejected under 35 U.S.C. Â§ 103 as unpatentable over Nene and Naffziger (US 2012/0109550 Al, published May 3, 2012). OPINION After review of the respective positions provided by Appellant and the Examiner, we reverse the Examiner's prior art rejections of claims 8-20 under 35 U.S.C. Â§Â§ I02(a)(2) and 103 essentially for the reasons presented by Appellant in the Appeal and Reply Briefs. We add the following for emphasis. Prior Art Rejections Anticipation Rejection (Independent claim 8) 3 Claim 8 is directed to a system comprising an integrated circuit device that generates a pulsed signal having a particular duty cycle selected from a group of defined duty cycles and a voltage regulator circuit coupled to the integrated circuit device via a single control wire. The voltage regulator 2 Altera Corporation is the Applicant/ Appellant and is identified as the real party in interest. App. Br. 2. 3 For Rejections I and II, we limit our discussion to independent claim 8. 3 Appeal2018-005037 Application 15/087,892 circuit receives the pulsed signal having the particular duty cycle from the integrated circuit device via the single control wire to generate a voltage supply signal that corresponds to the particular duty cycle of the pulsed signal. This is done by decoding the pulsed signal to determine a particular voltage level that corresponds to the particular duty cycle. Appellant defines decoding as "matching the duty cycle of the received pulsed signals to a duty cycle from a predefined group of duty cycles." Spec. ,r 51. The Examiner finds Nene discloses a system comprising an integrated circuit device 210 that generates a pulsed width modulation (PWM) signal having a particular duty cycle selected from a group of defined duty cycles. Final Act. 3; Nene, Fig. 2, ,r,r 17, 23, 25, 26. The Examiner also finds Nene discloses a voltage regulator circuit 220 coupled to the integrated circuit device 210 via a single control wire at node 244 that receives the PWM signal from the integrated circuit device via the single control wire. Final Act. 3; Nene, Fig. 2, ,r,r 17, 23, 25, 26. The Examiner finds that Nene's voltage regulator circuit generates a voltage supply signal Vout (Vout1) corresponding to the particular duty cycle of the PWM signal by decoding the PWM signal through a level shifter 221, drivers 222,223, a driver controller 224, and transistors M1-M3. Final Act. 3; Nene, Fig. 2, ,r,r 17, 23, 25, 26, 58, 68. That is, the Examiner finds that Nene's voltage regulator operates as claimed. Thus, the Examiner determines that the system of N ene anticipates the claimed invention. Final Act. 3. Appellant argues Nene generates a pulsed signal based on a voltage drop between 241 and 242 and does not generate a voltage signal by decoding a pulsed signal to determine a particular duty cycle that corresponds to a particular voltage level for the voltage signal, as recited in 4 Appeal2018-005037 Application 15/087,892 claim 8. App. Br. 6; Nene ,r 25. Instead, Appellant contends that Nene maintains the Vout signal by adjusting the duty cycle of the PWM signal and cannot be interpreted to use the duty cycle of a pulsed signal to determine a voltage level of a voltage signal because the Vout signal never changes regardless of the duty cycle of the PWM signal. That is, Appellant asserts that Nene controls the duty cycle based on the Vout signal. App. Br. 7. We agree with Appellant that there is reversible error in the Examiner's determination of anticipation. For the Examiner to carry the burden of establishing a prima facie case of anticipation, the Examiner must establish where each and every element of the claimed invention, arranged as required by the claim, is found in a single prior art reference, either expressly or under the principles of inherency. See generally In re Schreiber, 128 F.3d 1473, 1477 (Fed. Cir. 1997). The Examiner explains that Nene's Figure 2 shows a pulsed signal PWM (Pulse Width Modulation signal at a node 244) being converted by Level shifter, Drivers and transistors M1-M3 to a particular voltage level (of the voltage supply signal Vout) that corresponds to a particular duty cycle. Ans. 4. The Examiner then determines that the pulsed signal PWM is decoded by Level shifter, Drivers and transistors M1-M3 to generate a particular voltage level (Vout) that corresponds to the particular duty cycle. Id. However, Nene discloses that the control unit 210, and not the voltage regulator 220, adjusts the duty cycle of the pulsed signal in response to a change in the value of voltage VoutÂ· Nene ,r,r 20, 25. Thus, as argued by Appellant, Nene does not generate a voltage supply signal that corresponds to the particular duty cycle of the pulsed signal by decoding the pulsed 5 Appeal2018-005037 Application 15/087,892 signal as claimed, but instead does the opposite: controls the duty cycle based on the Vout signal. App. Br. 7. The Examiner does not adequately address Appellant's arguments. The Examiner does not direct us to any portion ofNene that describes the system as having a voltage regulator circuit that generates a voltage supply signal that corresponds to the particular duty cycle of the pulsed signal by decoding the pulsed signal to determine a particular voltage level that corresponds to the particular duty cycle. The Examiner also does not provide the necessary analysis to establish that Nene's system is inherently capable of performing the claimed function. Accordingly, we reverse the Examiner's prior art rejection under 35 U.S.C. Â§ 102 (a)(2) of claims 8-11, 13, and 14 for the reasons presented by Appellant and given above. We also reverse the separate rejection of claim 12, dependent from claim 8, under 35 U.S.C. Â§ 103 for the reasons presented by Appellant and given above. Obviousness Rejection (Independent claim 15) 4 Independent claim 15 is directed to a method for operating an integrated circuit device to control a voltage regulator circuit by using the integrated circuit device to generate a pulsed signal having a particular duty cycle based on information on temperature associated with the integrated circuit device and one or more voltage level adjustments based on one or more blown fuses within the integrated circuit device. We refer to the Examiner's Final Action for a complete statement of rejection of claim 15. Final Act. 5---6. Briefly, the Examiner recognizes that 4 For Rejection III, we limit our discussion to independent claim 15. 6 Appeal2018-005037 Application 15/087,892 Nene does not disclose using one or more voltage level adjustments based on one or more blown fuses within the integrated circuit device. Id. at 6. The Examiner determines that it is known to one having ordinary skill in the art to regulate voltage by utilizing information from one or more blown fuses during manufacture and cites to Naffziger in support of this determination. Id. Appellant contends that the combination of N ene and Naffziger fails to teach or suggest generating a signal based on temperature associated with a circuit device and voltage level adjustments based on blown fuses within the circuit device, as generally recited in claim 15. App. Br. 10, 11. We agree with Appellant that the Examiner committed reversible error. While the Examiner reasons that utilizing information from one or more blown fuses during manufacture to regulate voltage is known, the Examiner does not adequately explain why or how one skilled in the art would have modified Nene's method to incorporate this feature to arrive at the claimed invention. "[R ]ejections on obviousness grounds cannot be sustained by mere conclusory statements; instead, there must be some articulated reasoning with some rational underpinning to support the legal conclusion of obviousness." In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) (quoted with approval in KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398,418 (2007)). The Examiner's determination lacks an adequate articulated reasoning with some rational underpinning to support the legal conclusion of obviousness. Accordingly, we reverse the Examiner's prior art rejection of claims 15-20 under 35 U.S.C. Â§ 103 for the reasons presented by Appellant and given above. 7 Appeal2018-005037 Application 15/087,892 DECISION The Examiner's prior art rejections of claims 8-20 under 35 U.S.C. Â§Â§ 102(a)(2), and 103 are reversed. REVERSED 8