Ex Parte Tabony et al

Patent Trial and Appeal BoardOct 24, 2017

13655499 (P.T.A.B. Oct. 24, 2017)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/655,499 10/19/2012 Charles Joseph Tabony QC110553 6478 12371 7590 10/26/2017 Mnnrv rre.issle.r Olrk & T owe P C /OT TAT POMM EXAMINER 4000 Legato Road, Suite 310 Fairfax, VA 22033 METZGER, MICHAEL J ART UNIT PAPER NUMBER 2182 NOTIFICATION DATE DELIVERY MODE 10/26/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): meo.docket@mg-ip.com meo@mg-ip.com ocpat_uspto@qualcomm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte CHARLES JOSEPH TABONY, ERICH JAMES PLONDKE, LUCIAN CODRESCU, SURESH K. VENKUMAHANTI, and EVANDRO CARLOS MENEZES Appeal 2017-003356 Application 13/655,499 Technology Center 2100 Before THU A. DANG, CATHERINE SHIANG, and STEVEN M. AMUNDSON, Administrative Patent Judges. SHIANG, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 1—23, which are all the claims pending and rejected in the application. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. STATEMENT OF THE CASE Introduction According to the Specification, the present invention relates to processing systems. See generally Spec. 1. Claim 1 is exemplary: Appeal 2017-003356 Application 13/655,499 1. A method of switching between execution modes in a processor, the method comprising: detecting a first instruction when the processor is operating in a first execution mode; analyzing one or more bits of a target address of the first instruction; and determining whether to switch operation of the processor from the first execution mode to a second execution mode based on the one or more bits, wherein the one or more bits are alignment bits, and wherein the alignment bits are forcibly misaligned for the target address in one of the first execution mode or the second execution mode. References and Rejections Claim 22 is rejected under 35 U.S.C. § 112, second paragraph, as being indefinite.1 Claims 1—6, 9, 10, 12—17, 20, 22, and 23 are rejected under 35 U.S.C. § 102(b) as being anticipated by Krishnan (US 2005/0262329; Nov. 24, 2005). Claims 11 and 19 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Krishnan and Sartorius (US 7, 711,927; May 4, 2010). Claims 7, 8, and 18 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Krishnan and Tan (US 6,189,090; Feb. 13, 2011). Claim 21 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Krishnan and well-known techniques in the art. 1 This decision refers to the pre-AIA version of 35 U.S.C. § 112. 2 Appeal 2017-003356 Application 13/655,499 ANALYSIS 35 U.S.C. § 112, Second Paragraph With respect to claim 22, the Examiner finds the claimed “means for detecting . . means for analyzing . . and means for determining . . are means-plus-fimction limitations that invoke 35 U.S.C. § 112, sixth paragraph, but the written description fails to disclose the corresponding structures for the claimed functions. See Final Act. 4—5; Ans. 2-4. Claims must “particularly point[] out and distinctly claim[] the subject matter which the applicant regards as his invention.” 35 U.S.C. § 112, second paragraph. As to a means-plus-fimction claim term, “[i]f the patentee fails to disclose adequate corresponding structure, the claim is indefinite.” Williamson v. Citrix Online, LLC, 792 F. 3d 1339, 1352 (Fed. Cir. 2015) (citations omitted). Structure disclosed in the specification qualifies as “corresponding structure” if the intrinsic evidence clearly links or associates that structure to the function recited in the claim. . . . Even if the specification discloses corresponding structure, the disclosure must be of “adequate” corresponding structure to achieve the claimed function. . . . Under 35 U.S.C. § 112, paras. 2 and 6, therefore, if a person of ordinary skill in the art would be unable to recognize the structure in the specification and associate it with the corresponding function in the claim, a means-plus-fimction clause is indefinite. Williamson, 792 F. 3d at 1352 (citations omitted). For a computer-implemented means-plus-fimction claim limitation invoking 35 U.S.C, § 112, sixth paragraph, the corresponding structure for performing a specific function must be more than simply a general purpose computer or microprocessor. See In re Katz Interactive Call Processing 3 Appeal 2017-003356 Application 13/655,499 Patent Litig., 639 1. 3d 1303, 1316 (Fed. Cir, 2011). A computer- implemented means-plus-function term is limited to the corresponding structure disclosed in the specification and equivalents thereof, and the corresponding structure is the algorithm. See Aristocrat Techs, Austl Pty Ltd. v. Inti Game Tech,, 521 F.3d 1328, 1333 (Fed. Cir. 2008). Appellants argue the Specification adequately discloses the corresponding structures of the claimed “means for detecting . . .; means for analyzing . . .; and means for determining . . from the Specification. See App. Br. 6—7; Reply Br. 2—3. Appellants point to various passages and drawings of the Specification. App. Br. 6—7; Reply Br. 2—3. We have reviewed the portions of the Specification cited by Appellants, and we agree with Appellants that the cited Specification portions describe adequate corresponding structures to achieve the claimed functions. See Reply Br. 2—3; Spec. ^flf 30-32, 47; Fig. 2. Accordingly, we reverse the Examiner’s rejection of claim 22 under 35 U.S.C. § 112, second paragraph. Anticipation We have reviewed the Examiner’s rejection in light of Appellants’ contentions and the evidence of record. We concur with Appellants’ contention that the Examiner erred in finding the cited portions of Krishnan disclose “analyzing one or more bits of a target address . . . wherein the one or more bits are alignment bits, and wherein the alignment bits are forcibly misaligned for the target address in one of the first execution mode or the second execution mode,” as recited in independent claim 1 (emphases added). See App. Br. 8—11; Reply Br. 4—5. 4 Appeal 2017-003356 Application 13/655,499 The Examiner cites Krishnan’s paragraph 64 for teaching “wherein the alignment bits are forcibly misaligned for the target address in one of the first execution mode or the second execution mode.” See Final Act. 5—6; Ans. 16—17. The Examiner maps the claimed “alignment bits [that] are forcibly misaligned” to Krishnan’s LSB and LSB+1 bits. See Ans. 16—17. However, as acknowledged by the Examiner, Krishnan’s paragraph 64 states “at least two bits (the LSB and LSB+1) are unused for addressing.” See Ans. 16; Krishnan | 64 (emphasis added). In contrast, claim 1 requires the “alignment bits [that] are forcibly misaligned” be bits of a target address— used for addressing. See claim 1 (reciting “one or more bits of a target address . . . wherein the one or more bits are alignment bits”). As a result, the Examiner has not shown the cited portions of Krishnan disclose “analyzing one or more bits of a target address . . . wherein the one or more bits are alignment bits, and wherein the alignment bits are forcibly misaligned for the target address in one of the first execution mode or the second execution mode,” as recited in independent claim 1 (emphases added). Because the Examiner fails to provide sufficient evidence or explanation to support the anticipation rejection, we are constrained by the record to reverse the Examiner’s rejection of claim 1. Each of independent claims 12 and 22 recites a claim limitation that is substantively similar to the disputed limitation of claim 1. See claims 12 and 22. Therefore, for similar reasons, we reverse the Examiner’s rejection of independent claims 12 and 22. We also reverse the Examiner’s anticipation rejection of corresponding dependent claims 2—6, 9, 10, 13—17, 20, and 23. 5 Appeal 2017-003356 Application 13/655,499 Obviousness The Examiner cites additional references for the obviousness rejection of claims 7, 8, 11, 18, 19, and 21. The Examiner relies on Krishnan in the same manner discussed above in the context of claim 1, and does not rely on the additional references in any manner that remedies the deficiencies of the underlying anticipation rejection. See Final Act. 8—12. Accordingly, we reverse the Examiner’s obviousness rejection of claims 7, 8, 11, 18, 19, and 21. DECISION We reverse the Examiner’s decision rejecting claims 1—23. REVERSED 6