Ex Parte Suvakovic et al

Patent Trial and Appeal Board

Dec 12, 2017

13248869 (P.T.A.B. Dec. 12, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/248,869 09/29/2011 Dusan Suvakovic 808413-US-NP 9995
46304 7590 12/14/2017
RYAN, MASON & LEWIS, LLP
48 South Service Road
Suite 100
Melville, NY 11747
EXAMINER
COLEMAN, ERIC
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
12/14/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ny office @ rml-law. com
jbr@rml-law.com
ipsnarocp @ nokia. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DUSAN SUVAKOVIC,
ADRIAAN J. DE LIND VAN WIJNGAARDEN, and MAN FAI LAU
Appeal 2017-004484
Application 13/248,869
Technology Center 2100
Before ROBERT E. NAPPI, DAVID M. KOHUT, and
LYNNE E. PETTIGREW, Administrative Patent Judges.
KOHUT, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE1
This is an appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1—20 and 22—24. Claim 25 has been allowed. We have jurisdiction
under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.
1 Our Decision makes reference to Appellants’ Reply Brief (“Reply Br.,”
filed January 23, 2017) and Appeal Brief (“App. Br.,” filed September 12,
2016), and the Examiner’s Answer (“Ans.,” mailed December 1, 2016) and
Final Office Action (“Final Act.,” mailed June 3, 2016).
Appeal 2017-004484
Application 13/248,869
INVENTION
Appellants’ invention relates to encoder and decoder selection for
video communications between devices. Abstract; Spec. 3.
Claims 1,17, and 20 are the independent claims on appeal. Claim 1 is
illustrative of the invention and reproduced below (disputed limitations
italicized):
1. An apparatus comprising:
a plurality of processor units arranged to operate
concurrently and in cooperation with one another; and
control logic configured to direct the operation of the
plurality of processor units to perform computations
associated with decoding of a designated forward error
correction code;
wherein at least a given one of the processor units
comprises:
a memory;
an arithmetic engine; and
a switch fabric providing controllable connectivity
between the memory, the arithmetic engine and
input and output ports of the given processor unit;
the switch fabric having control inputs driven by the
control logic;
wherein the control logic is configured to drive the
control inputs of the switch fabric to direct the arithmetic
engine of the given processor unit to perform first and
second different portions of the decoding of said
designated forward error correction code.
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Application 13/248,869
REFERENCES
Dulong US 5,384,722 Jan. 24, 1995
Shin et al. US 2008/0313253 A1 Dec. 18, 2008
(“Shin”)
Kwok et al. US 2011/0239094 Al Sept. 29, 2011
(“Kwok”)
REJECTIONS
Claims 1—4, 6—11, 13—17, 19, 20, 23 and 24 are rejected under 35
U.S.C. § 102(b) as anticipated by Shin.
Claim 5 is rejected under 35 U.S.C. § 103(a) as unpatentable over
Shin and Dulong.
Claims 12 and 18 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Shin.
Claim 22 is rejected under 35 U.S.C. § 103(a) as unpatentable over
Shin and Kwok.
ANALYSIS
Claims 1—4, 6—11, 13—17, 19, 20, 23, and 24 rejected under 35 U.S.C.
§ 102(b) as anticipated by Shin.
Independent claims 1,17, and 20
Independent claim 1 recites, “[a] processor unit to perform first and
second different portions of the decoding of said designated forward error
correction code.” The Examiner finds Shin discloses processor units for
decoding a forward error correction code. Final Act. 2. The Examiner
construes the claimed first and second different portions of the decoding to
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Application 13/248,869
include the different, discrete operations that occur in the processor unit, i.e.,
the adders and multipliers in the basic cell of Shin. Final Act. 3; Ans. 3.
Appellants argue that Shin’s adders and multipliers are not reasonably
considered as the claimed first and second different portions. App. Br. 7.
Rather, Appellants argue Shin discloses the first portion (Euclidean
algorithm including the adders and multipliers), but not the second portion
(Chien search) and therefore does not perform first and second portions of
decoding the designated forward error correction code. App. Br. 7.
Appellants have not persuaded us that the Examiner’s broader claim
interpretation is unreasonable, in light of Appellants’ Specification. We
understand the plain meaning of the term portion to be a part or a component
of a whole. This meaning is supported by the Specification, which uses the
term portion throughout to mean parts of a whole. See, e.g., Spec. 4—9, 19,
and 22. Further, the Specification neither limits the first portion as being
associated with a key equation solver, such as a Euclidean algorithm, nor
limits the second different portion as being associated with an error value
computation module, such as a Chien search. Under the broadest reasonable
interpretation consistent with the Specification, we find the first and second
portions of the decoding can be the adders and multipliers in Shin’s
processor unit. Accordingly, Appellants’ argument is not persuasive as it is
based on an improperly narrow claim interpretation and Appellants have not
persuaded us of error with respect to the Examiner’s finding.
Independent claims 17 and 20 recite similar limitations as claim 1 and
are not argued separately. Claims 3, 4, 6—8, 10, 11, and 14—16 depend from
claim 1 and are not argued separately. Accordingly, we sustain the
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Application 13/248,869
Examiner’s rejection of claims 1,3,4, 6—8, 10, 11, 14—17, and 20 as
anticipated by Shin.
Claims 13, 19, 23, and 24
Claim 13 recites “the second portion of the decoding of said
designated forward error correction code comprises computations of a Chien
search.” App. Br. 19 (emphasis added). Claim 19 recites a similar
limitation. Id. at 20. Claim 23 recites “the second portion of the decoding
of said designated forward error correction code comprises computations of
an error value computation module.'1'’ Id. (emphasis added). Claim 24
recites a similar limitation. Id. at 21.
The Examiner finds the outputs of Shin’s modified Euclidean
algorithm circuit are used as inputs for the Chien search/error value
computation module, and are thus computations of the Chien search/error
value computation module. Final Act. 6—7; Ans. 5.
Appellants argue Shin performs computations of a Euclidean
algorithm, whose output is fed as input to a separate Chien search. App. Br.
9—10; Reply Br. 5. Appellants further argue the basic cell in Shin does not
perform any computations of the Chien search or any other computations to
calculate the locations and values of errors. App. Br. 9-10; Reply Br. 5. We
agree with Appellants.
The claims require the second portion to have computations of a
Chien search (or the error value computation module). While we agree with
the Examiner that Shin discloses the outputs from the computations of the
Euclidean algorithm serve as inputs to the Chien search (Final Act. 6-7;
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Ans. 5), the Examiner has failed to show that the inputs to the Chien search
are the same as the claimed computations of the Chien search. Accordingly,
we do not sustain the Examiner’s rejection of claims 13, 19, 23, and 24 as
anticipated by Shin.
Claim 2
Claim 2 recites the “memory comprises a multi-port memory
configured to permit the arithmetic engine to read at least two different input
variables simultaneously.” App. Br. 17.
The Examiner finds Shin discloses memory in the form of four D-
latches receiving multiple inputs and giving output to the multipliers and
adders. Final Act. 3; Ans. 4.
Appellants argue Shin’s latches are not multi-port memory; rather,
Appellants argue the latches are basic flip-flops that are not multi-port
memory and they cannot collectively store more than one word at a time.
App. Br. 8.
Appellants’ arguments are not persuasive. The Specification states
registers (latches) or banks of registers can be used in addition to or in place
of the memory. Spec. 8. As the Examiner points out, Shin discloses four
latches, each latch simultaneously receiving a different input, not a
collective input. Final Act. 3; Ans. 4. As such, we agree with the Examiner
(Final Act. 3; Ans. 4) that the memory system of Shin has four input ports.
Thus, Appellants have not provided persuasive arguments as to why the
latches of Shin that receive multiple inputs are not multi-port memory as
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claimed. Accordingly, we sustain the Examiner’s rejection of claim 2 as
anticipated by Shin.
Claim 9
Claim 9 recites the “processor unit further comprises an input port
configured to receive an input from an external co-processor.”
The Examiner finds Shin discloses an input from an external co­
processor (input Fi+1 to one basic cell from another basic cell). Final Act. 5;
Ans. 4.
Appellants argue Shin’s basic cell is not an external co-processor.
App. Br. 8. Appellants further argue the input Fi+1 is a polynomial and thus
not an input from an external co-processor. App. Br. 8.
Appellants’ arguments are not persuasive. The Examiner finds that
the basic cells of Shin are processors and make up the Euclidean algorithm
circuit. Ans. 4; see Shin Fig. 6, 48, 51. Shin teaches that each basic cell
feeds polynomial outputs as polynomial inputs to the next basic cell, until
the final error locator polynomial and an error value polynomial output from
the circuit. See Shin | 50. As such, any basic cell in the Euclidean
algorithm circuit can be considered as a co-processor and external to another
basic cell in the circuit; therefore, an input Fi+i would be input from an
external co-processor. Appellants do not provide further argument as to why
the basic cells in Shin are not co-processors or why the polynomial Fi+1
cannot be input from a co-processor. See App. Br. 8. Accordingly, we
sustain the Examiner’s rejection of claim 9 as anticipated by Shin.
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Claim 5 rejected under 35 U.S.C. § 103(a) as unpatentable over Shin
and Dulong.
Claim 5 recites “a multiplexer controlling application of data to a first
data input of the multi-port memory; and a multiplexer controlling
application of data to a second data input of the multi-port memory.”
The Examiner finds Dulong teaches that two multiplexers control data
being input to latches. Final Act. 8; Ans. 6 (citing Dulong Fig. 5
multiplexers 64, 66; latches 68, 69). As a result, the Examiner proposes
combining Dulong’s multiplexers with Shin’s system, including multi-port
memory in the form of latches, in order to read on the disputed limitation.
Final Act. 8; Ans. 6.
Appellants argue Dulong does not teach multi-port memory because
the latches do not have a first data input and a second data input. App. Br.
11; see Dulong Fig. 5 latches 68, 69.
Appellants’ arguments are unpersuasive because they misinterpret the
Examiner’s rejection. The Examiner relies on Shin to teach the multi-port
memory with first and second data inputs; the Examiner only relies on
Dulong to teach multiplexers. See Final Act. 8; Ans. 6. As we already have
addressed the argument regarding the latches of Shin as multi-port memory,
and because Appellants have not provided further argument regarding the
combination of Shin with Dulong, Appellants’ have not persuaded us of
error in the Examiner’s rejection. Accordingly, we sustain the Examiner’s
rejection of claim 5 as unpatentable over Shin and Dulong.
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Claims 12 and 18 rejected under 35 U.S.C. § 103(a) as unpatentable
over Shin.
Claim 12 recites the “total number of multipliers collectively provided
by the processor units is less than a maximum number of errors that are
correctable.” App. Br. 19. Claim 18 recites a similar limitation. Id. at 20.
The Examiner finds the disputed limitation is taught by Shin because
Shin teaches the number of errors that are correctable (t) is given by the
equation t=(n-k)/2. Final Act. 9 (citing Shin | 6). The Examiner further
finds the Euclidean algorithm circuit has 64 multipliers and “any arbitrary
numbers” for (n) and (k) where (t) is greater than 64 would meet this claim
limitation. Final Act. 9; Ans. 6.
Appellants argue the Examiner’s findings are not supported by the
teachings of Shin. App. Br. 12—15. Specifically, Appellants argue Shin
teaches that the basic number of cells needed for processing the maximum
number of correctable errors should be 2t (which would have more
multipliers than errors (t) as the number of multipliers per cell is four) and
thus Shin teaches away from claim 12. App. Br. 14.
Appellants’ argument regarding lack of support in Shin for the
Examiner’s finding is persuasive. The Examiner finds that any arbitrary
numbers (n) and (k) that would have (t) be more than the number of
multipliers would meet the limitation, but the Examiner does not point to
any support in the reference for this statement nor does the Examiner
suggest that these values would have been selected by one of ordinary skill
in the art. For example, the Examiner has not shown that there would be a
circumstance where (n) and (k) could equal values that would result in a
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value (t) greater than 64. Without more, we cannot sustain the Examiner’s
rejection.
Accordingly, we do not sustain the Examiner’s rejection of claims 12
and 18 as unpatentable over Shin.
Claim 22 rejected under 35 U.S.C. § 103(a) as unpatentable over Shin
and Kwok.
Claim 22 recites an “arithmetic engine provides a single finite field
multiplier and a single adder.” App. Br. 20.
The Examiner finds Kwok teaches or suggests either parallel or serial
processing, where a serial architecture may comprise a multiplier block
having one multiplier and one adder. Final Act. 10; Ans. 6—7. The
Examiner points to Figure 3 of Kwok as teaching “a single multiplier and a
single adder.” Final Act. 10. The Examiner further finds Kwok teaches the
number of multipliers ranges “from one to t+1.” Ans. 6. The Examiner
concludes that using a serial architecture, i.e., reducing the number of
multipliers and adders “needed per cell to one,” reduces hardware costs. Id.
at 7.
Appellants argue “[t]he number of multipliers shown in FIG. 3 of
Kwok . . . cannot simply be one.” App. Br. 15. Citing to Kwok, Figure 3
and paragraph 60, Appellants state “the minimum number of multipliers . . .
is ten.” App Br. 16. We disagree with Appellants.
While Kwok Figure 3 illustrates a parallel multiplier architecture
useable as a Chien search, the Examiner finds Kwok also teaches an
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embodiment with a serial multiplier architecture using one Galois field
(finite field) multiplier (with one multiplier and one adder) to perform all the
multiplications. Kwok || 37, 59; Fig. 3. Similarly, while we note Figure 2
is illustrated as a semi-parallel BMA multiplier architecture with a plurality
of Galois field multipliers, the Examiner finds that using a serial architecture
can result in the number of Galois field multipliers being one. See Ans. 7
(citing Kwok Fig. 2 and 143 (“BMA architecture can range from one, for a
serial architecture, to 3t +3”)).
Appellants have not addressed the Examiner’s specific findings
regarding the serial implementation of the architectures of Figures 2 and 3.
As such, Appellants’ arguments have not persuaded us of error in the
Examiner’s rejection. Accordingly, we sustain the Examiner’s rejection of
claim 22 as unpatentable over Shin and Kwok.
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CONCLUSION
The Examiner did not err in rejecting claims 1—4, 6—11, 14—17, and 20
under 35 U.S.C. § 102(b) as anticipated by Shin.
The Examiner erred in rejecting claims 13, 19, 23, and 24 under
35 U.S.C. § 102(b) as anticipated by Shin.
The Examiner did not err in rejecting claim 5 under 35 U.S.C.
§ 103(a) as unpatentable over Shin and Dulong.
The Examiner erred in rejecting claims 12 and 18 under 35 U.S.C.
§ 103(a) as unpatentable over Shin.
The Examiner did not err in rejecting claim 22 under 35 U.S.C.
§ 103(a) as unpatentable over Shin and Kwok.
DECISION
The Examiner’s rejections of claims 1—11, 14—17, 20, and 22 are
affirmed.
The Examiner’s rejections of claims 12, 13, 18, 19, 23, and 24 are
reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED-IN-PART
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