Ex Parte Summerfelt et al

Patent Trial and Appeal Board

Jun 16, 2016

12576340 (P.T.A.B. Jun. 16, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/576,340 10/09/2009
23494 7590 06/20/2016
TEXAS INSTRUMENTS IN CORPORA TED
P 0 BOX 655474, MIS 3999
DALLAS, TX 75265
FIRST NAMED INVENTOR
Scott R. Summerfelt
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TI-67122 1907
EXAMINER
ANYA,IGWEU
ART UNIT PAPER NUMBER
2891
NOTIFICATION DATE DELIVERY MODE
06/20/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SCOTT R. SUMMERFEL T and RAJNI J. AGGARWAL 1
Appeal2015-001729
Application 12/576,340
Technology Center 2800
Before MICHAEL J. STRAUSS, DANIEL N. FISHMAN, and
JAMES W. DEJMEK, Administrative Patent Judges.
DEJMEK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-13. Claims 14--20 have been withdrawn. Final Act. 1. We have
jurisdiction over the remaining pending claims under 35 U.S.C. § 6(b ).
We reverse.
1 Appellants identify Texas Instruments Incorporated as the real party in
interest. Br. 3.
Appeal2015-001729
Application 12/576,340
STATEMENT OF THE CASE
Introduction
Appellants' invention is directed to an "integrated circuit containing
hydrogen permeable dummy vias." Abstract. In a disclosed embodiment,
the hydrogen permeable dummy vias are formed inside an inter-level
dielectric layer, and at least a portion of bottom surfaces of the hydrogen
permeable dummy vias contact another dielectric layer. Spec. i-f 19.
According to the Specification, this allows hydrogen to diffuse from the
inter-level dielectric layer to the other dielectric layer. Spec. i-f 19.
Claim 1 is illustrative of the subject matter on appeal and is
reproduced below with the disputed limitation emphasized in italics:
1. An integrated circuit, comprising:
a substrate;
a component located on said substrate;
a dielectric layer located on said substrate and above said
component;
a plurality of electrically active ferroelectric structures located
over said dielectric layer;
a hydrogen barrier located above said electrically active
ferroelectric structures;
an inter-level dielectric layer located on said hydrogen barrier;
a plurality of electrically active vias located in said inter-level
dielectric layer and said hydrogen barrier; and
a plurality of hydrogen permeable dummy vias configured in
one of a linear array or a rectangular array, said plurality of hydrogen
permeable dummy vias symmetrically positioned over said
component and located in said inter-level dielectric layer and said
hydrogen barrier such that at least a portion of bottom surfaces of said
plurality of hydrogen permeable dummy vias contact said dielectric
layer.
2
Appeal2015-001729
Application 12/576,340
The Examiner ;s Rejections
1. Claims 1, 7, 10, and 12 stand rejected under 35 U.S.C. § 102(b)
as being anticipated by Sashida (US 2008/0224194 Al; Sept. 18, 2008).
Final Act. 2--4.
2. Claims 2-6, 8, 9, 11, and 13 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Sashida. Final Act. 6-11.
Issue on Appeal2
Did the Examiner err in finding Sashida discloses a dielectric layer
and a plurality of hydrogen permeable dummy vias "such that at least a
portion of bottom surfaces of said plurality of hydrogen permeable dummy
vias contact said dielectric layer," as recited in claim 1?
ANALYSIS 3
In rejecting claim 1, the Examiner finds Sashida discloses, inter alia, a
portion of bottom surfaces of a plurality of hydrogen permeable dummy vias
contact a dielectric layer. Final Act. 3. In particular, the Examiner relies on
Figure 9 of Sashida and finds a portion of the bottom surface of via-plug
42C (i.e., a dummy via-plug) is in contact with dielectric layer 32. Id.;
see also Sashida i-f 44, Fig. 9. Figure 9 of Sashida, relied upon by the
Examiner, is illustrative and is reproduced below:
2 We only address this issue, which is dispositive. We do not address
additional issues raised by Appellants' arguments.
3 Throughout this Decision we have considered the Appeal Brief filed
March 27, 2014 ("Br."); the Examiner's Answer mailed on August 26, 2014
("Ans."); and the Final Office Action ("Final Act.") mailed on November 8,
2013, from which this Appeal is taken.
3
Appeal2015-001729
Application 12/576,340
c
' ·--._
1'
40 -----·-39 ____ _,--
38 -----
FIG.9
42A
37--------•11~•-LJ 36- ~
!
'
31 -..____..r·-~
'
\
34 33
428
\
35
42C
\
()
--""/43
, ___ ,--42
Figure 9 of Sashida illustrates the formation of via-plugs ( 42A, 42B,
and 42C) as part of the fabrication of a semiconductor device having a
ferromagnetic capacitor (C). Sashida ,-r,-r 42; 44. "While not illustrated there
is provided a silicon substrate carrying an active element ... underneath the
interlayer insulation film 31." Sashida ,-r 24 (referring to Figure 3, which we
find similarly applies to Figure 9). Sashida further discloses the formation
of the via-plugs is "without etching the SION film 32 at the bottom part of
the opening 41C. Thereby, the via-plug 42C becomes a dummy via-plug."
Sashida ,-r 44.
Appellants contend Figure 9 of Sashida does not disclose "at least a
portion of bottom surfaces of [a] plurality of hydrogen permeable dummy
vias contact [a] dielectric layer," as recited in claim 1. Br. 12-13. In
particular, Appellants assert, contrary to the Examiner's finding, film 32 is
not the dielectric layer because "element 32 is an etch stop layer." Br. 13
4
Appeal2015-001729
Application 12/576,340
(citing Sashida ilil 28, 30, 44). Rather, Appellants assert film 31 of Sashida
corresponds to the claimed dielectric layer. Br. 13. Appellants conclude
because the dummy via-plug 42C illustrated in Figure 9 does not contact the
insulation film 31 (i.e., the dielectric layer), Sashida fails to disclose the
disputed limitation.
We find Appellants' arguments persuasive of Examiner error. As
claimed, the dielectric layer of claim 1 is located on a substrate and above a
component located on the substrate. As the Appellants identify, Sashida
discloses "a silicon substrate carrying an active element such as a MOS
transistor underneath the interlayer insulation film 31." Sashida i-f 24
(emphasis added). Thus, layer 31 of Sashida is located over a component on
a substrate (and thereby over the substrate as well).
A claim is anticipated only if each and every element as set forth in
the claim is found, either expressly or inherently described, in a single prior
art reference. Verdegaal Bros., Inc. v. Union Oil Co. of Cal., 814 F.2d 628,
631 (Fed. Cir. 1987).
The Examiner finds "a dielectric layer may comprise of [sic] multiple
films including [an] etch stop layer [(i.e., such as layer 32)] to avoid over
etching." Ans. 4. Accordingly, the Examiner finds films 31, 32, and 33
form the claimed dielectric layer "by virtue of their compositions." Ans. 4;
see also Final Act. 2. However, the Examiner has not identified a disclosure
in Sashida or elsewhere to support such a finding. Thus, because dummy
via-plug 42C does not penetrate through SION film 32 to contact a dielectric
layer as claimed, the reference fails to disclose the disputed limitation of
claim 1.
5
Appeal2015-001729
Application 12/576,340
Therefore, based on the record before us, and for the reasons
discussed supra, we do not sustain the Examiner's rejection of independent
claim 1 or the rejection of independent claim 7, which contains similar
limitations. For similar reasons, we do not sustain the Examiner's rejections
of dependent claims 2---6 and 8-13.
DECISION
We reverse the Examiner's decision to reject claims 1-13.
REVERSED
6