Ex Parte Speier et al

Patent Trial and Appeal Board

Dec 4, 2012

11040600 (P.T.A.B. Dec. 4, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte THOMAS PHILIP SPEIER, JAMES NORRIS
DIEFFENDERFER, and RAVI RAJAGOPALAN
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Appeal 2010-006609
Application 11/040,600
Technology Center 2100
____________

Before DENISE M. POTHIER, JENNIFER L. McKEOWN,
and DAVID C. McKONE, Administrative Patent Judges.

McKONE, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-24, which constitute all the claims pending in this application. See
App. Br. 3.1 We have jurisdiction under 35 U.S.C. § 6(b). We reverse.

1 Throughout this opinion, we refer to the Appeal Brief filed May 22, 2009,
and supplemented July 17, 2009, the Examiner’s Answer mailed October 27,
2009, and the Reply Brief filed January 27, 2010.
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STATEMENT OF THE CASE
Appellants’ invention relates to techniques for allocating cache
memory banks between cache memory and non-cache memory. See
Spec. ¶ 0001. Claim 1, which is illustrative of the invention, reads as
follows:
1. Apparatus for allocating a total number of
banks of memory in a cache memory having more than
two banks of memory, the apparatus comprising:
a configuration tracker for configuring a first
portion of the total number of banks of memory as cache
memory and a second portion of the total number of
banks of memory as non-cache memory; and
a bank selector for receiving an incoming address,
the bank selector applying a selected one of a plurality of
bank distributing functions based upon the number of
banks configured to the first portion to distribute cache
accesses over the first portion of memory banks in a
balanced manner when the number of memory banks in
the first portion is both greater than two and is not a
power of two.

THE REJECTIONS
The Examiner relies on the following prior art in rejecting the claims:
Patel U.S. 5,854,761 Dec. 29, 1998
Gupta U.S. 6,108,745 Aug. 22, 2000
Agarwala U.S. 6,606,686 B1 Aug. 12, 2003
Lablans U.S. 2005/0185796 A1 Aug. 25, 2005
(filed Sept. 8, 2004)
Claims 1-6, 9, 11-17, and 19-23 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Agarwala, Gupta, and Patel. See Ans.
4-10.
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Claims 7, 8, 10, 18, and 24 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Agarwala, Gupta, and Lablans.2 See Ans. 10-11.

ISSUE
Appellants argue claims 1, 12, and 19 as a group. See App. Br. 6-12.
Appellants do not separately argue dependent claims 2-6, 9, 11, 13-17, and
20-23, and only nominally argue dependent claims 7, 8, 10, 18, and 24
separately. See App. Br. 12.
Regarding claim 1, the Examiner finds that a person of ordinary skill
in the art would have combined the teachings of Agarwala and Gupta with
Patel “for the benefit of grouping multiple ways into banks.” Ans. 5.
Appellants contend that the Examiner has not provided an adequate rationale
for combining Patel with Agarwala and Gupta. See App. Br. 10-11.
Accordingly, the issue raised by Appellants’ contention is whether the
Examiner articulated a reason, with rational underpinning, to combine
Agarwala, Gupta, and Patel.

ANALYSIS
REJECTION OF CLAIMS 1-6, 9, 11-17, AND 19-23 UNDER 35 U.S.C. § 103(a)
The Examiner finds that Agarwala teaches “rearranging cache ways
so that a portion of the ways function as cache memory and the other portion
of the ways function as non-cache memory.” Ans. 12. According to the
Examiner, a memory “bank” can contain one or more cache “ways.” See id.

2 All these claims depend from independent claims 1, 12, or 19, which were
rejected based on Agarwala, Gupta, and Patel. The heading of this rejection
should therefore include Patel.
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For example, in Agarwala, “[i]t is known in the art to provide more than one
cache entry for each set. The number of such cache entries is known as the
ways of the cache.” Agarwala, col. 7, ll. 26-28. See also Patel, col. 3,
ll. 57-58 (“Each bank also provides two ways (or cache lines) 308 and 310
associated with a set.”). This is shown in Agarwala’s Figure 4 reproduced
below:

Figure 4 shows a cache memory divided into eight sets of entries,
with each set divided into four ways.

Because a bank can include more than one way, and Agarwala
organizes memory into cache and non-cache based on ways rather than
banks, Agarwala (in combination with Gupta) does not teach “configuring a
first portion of the total number of banks of memory as cache memory and a
second portion of the total number of banks of memory as non-cache
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memory.” See Ans. 5 (“The combination of Agarwala and Gupta fail [sic] to
teach that cache banks are made up of cache ways.”). The Examiner finds,
however, that Patel discloses that “banks consist of at least one or more
ways.” Id.
In response to Appellants’ arguments, the Examiner clarified his
rejection, explaining that “[w]hen cache ways are grouped as either cache or
non-cache they also end up grouping memory banks.” Ans. 12. The
Examiner explained that Patel proves that “one bank can be made up of one
way or put more simply one way equals one bank” and that “Patel is only
relied upon to show that one way equals one bank.” Ans. 12-13. The
Examiner points to Figure 3 of Patel:

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See Ans. 5, 13-14. Patel’s Figure 3 shows an “even bank” divided into “way
0” and “way 1,” and an “odd bank” divided into two instances of “way 0.” 3
Appellants concede that Patel’s Figure 3 “discloses that a single way could
be allocated to a single bank.” Reply Br. 2.
Appellants, however, contend that “Patel does not disclose any
rationale for why an exclusive one-way per-cache implementation would be
used for all banks,” and that “there is no apparent suggestion to implement
all banks [of Agarwala’s level two cache memory] with a single unique
way.” App. Br. 10-11. “[R]ejections on obviousness grounds cannot be
sustained by mere conclusory statements; instead, there must be some
articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness.” In re Kahn, 441 F.3d 977, 988 (Fed. Cir.
2006); accord KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). The
Examiner’s stated rationale for combining the teachings of Agarwala and
Gupta with Patel is “for the benefit of grouping multiple ways into banks.”
Ans. 5. Appellants correctly point out that a rationale based on grouping
multiple ways into banks is contradictory to the Examiner’s finding that
Patel teaches “one way equals one bank.” See App. Br. 9-10. The Examiner
does not provide any other rationale for why a person of ordinary skill in the
art would combine these teachings.
We conclude that the Examiner’s stated reason for combining
Agarwala and Gupta with Patel lacks rational underpinning. As shown in
Figure 4 of Agarwala (above), when a way is selected as cache or non-cache,

3 But see Patel, col. 4, ll. 5-7 (“As shown in FIG. 3, the way 0 and the way 1
of each of the odd and even banks of the cache 302 respectively output 4
lines of instructions.” (emphasis added)); Patel, Figure 5 (showing that the
“Odd Set” has a “way 0” and a “way 1”).
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that same way in each bank is configured cache or non-cache. See
Agarwala, col. 8, ll. 6-41. Agarwala teaches that there are benefits to
organizing a cache in this manner. For example, “the ways may . . . be
configured as SRAM only in a predetermined order enabling the SRAM
memory addresses to be contiguous whatever number of partitions are
configured as SRAM.” Agarwala, col. 8, ll. 41-44. Agarwala also states
that “[t]he cache/SRAM partitioning within level two unified cache 130 is
across the data banks rather than within the data banks” so that the “level
two unified cache 130 can always supply 256 bits to level one instruction
cache 121 if any part is partitioned as cache.” Agarwala, col. 5, ll. 44-49.
Yet, given these teachings, the Examiner does not explain why
modifying the way Agarwala organizes its cache memory in light of Patel
would provide “the benefit of grouping multiple ways into banks” (Ans. 5),
or what that benefit would be. Thus, assuming that a person of ordinary skill
in the art could configure Agarwala’s cache to have a one-to-one
correspondence between ways and banks, the Examiner has not adequately
explained why one would do so. Also, although claim 1 does not require the
configuration tracker to configure all banks (see App. Br. 10-11) – rather a
first portion of the total number of banks configured as cache memory and a
second portion of the total number of banks as non-cache memory –, the
record still fails to articulate adequately a rational basis for combining
Patel’s teachings with Agarwala to support a conclusion of obviousness.
Accordingly, we do not sustain the rejection of (1) claim 1; (2) claims
12 and 19, which include recitations substantially the same as claim 1; (3)
claims 2-6, 9, and 11, which depend on claim 1; (4) claims 13-17, which
depend on claim 12; and (4) claims 20-23, which depend on claim 19.
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REJECTION OF CLAIMS 7, 8, 10, 18, AND 24 UNDER 35 U.S.C. § 103(a)
Claims 7, 8, and 10 depend on claim 1; claim 18 depends on claim 12;
and claim 24 depends on claim 19. The newly cited reference, Lablans, has
not been cited to cure the above noted deficiency. See Ans. 10-11.
Accordingly, we reverse the rejection of claims 7, 8, 10, 18, and 24 for the
reasons given above for claims 1, 12, and 19.

ORDER
The decision of the Examiner to reject claims 1-24 is reversed.

REVERSED

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