Ex Parte Solomita et al

Patent Trial and Appeal Board

Nov 30, 2012

11497884 (P.T.A.B. Nov. 30, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte ETHAN SOLOMITA, SUNAY TRIPATHI, and
JERRY HSIAO-KENG CHU
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Appeal 2010-006494
Application 11/497,884
Technology Center 2100
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Before JASON V. MORGAN, ERIC B. CHEN, and
TREVOR M. JEFFERSON, Administrative Patent Judges.

MORGAN, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-006494
Application 11/497,884

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STATEMENT OF THE CASE
Introduction
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s Final
Rejection of claims 43 – 60. Claims 1 – 42 are canceled. App. Br. 4. We
have jurisdiction under 35 U.S.C. § 6(b)(1).
We affirm.
Invention
The invention relates to distributing multiple interrupts among
multiple processors. See Abstract.
Exemplary Claim (Emphases Added)
43. A machine-implemented method comprising:
determining that a particular device is capable of using an
N number of interrupt channels to send interrupts generated by
the particular device, where N is an integer greater than one;
generating a first mapping that maps the N interrupt
channels to one or more processors of a plurality of processors;
causing interrupts sent by the particular device to be
distributed according to the first mapping;
generating a second mapping, wherein the second
mapping requires the particular device to use an M number of
interrupt channels instead of an N number of interrupt
channels, where M is a positive integer less than N, and
wherein the second mapping maps the M interrupt channels to
one or more processors of the plurality of processors; and
causing interrupts sent by the particular device to be
distributed according to the second mapping instead of the first
mapping, thereby causing the particular device to change from
using N interrupt channels to using M interrupt channels.
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Rejection
The Examiner rejects claims 43 – 60 under 35 U.S.C. § 102(b) as
being anticipated by Jahnke (US 2003/0120702 A1; June 26, 2003). Ans. 3 –
7.
ISSUES
1. Did the Examiner err in finding that Jahnke discloses “generating a
first mapping that maps the N interrupt channels to one or more processors
of a plurality of processors” and “generating a second mapping, wherein the
second mapping requires the particular device to use an M number of
interrupt channels instead of an N number of interrupt channels,” as recited
in claim 43?
2. Did the Examiner err if finding that Jahnke discloses “causing
interrupts sent by the particular device to be distributed according to the first
mapping” and “causing interrupts sent by the particular device to be
distributed according to the second mapping instead of the first mapping,” as
recited in claim 43?
ANALYSIS
Claim 43 recites “generating a first mapping that maps the N interrupt
channels to one or more processors of a plurality of processors” and
“generating a second mapping, wherein the second mapping requires the
particular device to use an M number of interrupt channels instead of an N
number of interrupt channels.” The Examiner finds that Jahnke, which is
directed to load balanced interrupt handling in an embedded symmetric
multiprocessor system, discloses the claimed generating of mappings of
interrupt channels to processors. See Ans. 4 (citing Jahnke fig. 6 and
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¶ [0045]). Specifically, the Examiner finds that Jahnke illustrates generating
an initial first mapping of interrupts A – D to processors CPU-0 – CPU-3
followed by generating a second mapping to a single processor. See Ans. 4
and 7 – 8.
Appellants contend that the Examiner erred. Specifically, Appellants
argue that Jahnke illustrates a set of interrupts and is not directed to interrupt
channels. See App. Br. 8. However, Jahnke discloses causing “an interrupt
[to be executed by] the selected central processing unit via the corresponding
one of interrupt A line 610, interrupt B line 611. . . or interrupt [D] line 613”
Jahnke ¶ [0045] (emphases added). Thus, Jahnke illustrates more than a set
of interrupts; Jahnke discloses interrupt channels (i.e., lines) for executing
interrupts.
Appellants further argue that “there are no mappings generated for
interrupts A-D to corresponding CPUs” in Jahnke. App. Br. 9. Specifically,
Appellants argue that Jahnke fails to mention either “storing any type of
mapping” or “using a different number of total interrupt channels to
distribute interrupts.” See id.; see also Reply Br. 9. However, the Examiner
correctly notes that the claim recitations do not require storing any
mappings. See Ans. 7. Thus, Appellants’ arguments are not commensurate
with the scope of the claimed invention.
Furthermore, the Examiner correctly finds that Jahnke discloses an
initial mapping using all four interrupt channels and a subsequent mapping
in which a selected interrupt channel is used for interrupt execution. See
Ans. 7 (citing, Jahnke ¶ [0045]). The Examiner’s findings are consistent
with Appellants’ characterization of Jahnke as disclosing that when an
interrupt first occurs, one of the processors at random takes the interrupt and
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provides it to scheduling software. See Reply Br. 4 The scheduling software
then chooses one of a plurality of CPUs to handle the interrupt. See App. Br.
9 – 10. The initial uptake by any one of four CPUs discloses a first generated
mapping while the subsequent assignment to a selected CPU discloses a
second generated mapping, with a different, smaller number of interrupt
channels used for interrupt distribution during the two parts of interrupt
handling. Therefore, we agree with the Examiner that Jahnke discloses
“generating a first mapping that maps the N interrupt channels to one or
more processors of a plurality of processors” and “generating a second
mapping, wherein the second mapping requires the particular device to use
an M number of interrupt channels instead of an N number of interrupt
channels,” as recited in claim 43.
Claim 43 further recites “causing interrupts sent by the particular
device to be distributed according to the first mapping” and “causing
interrupts sent by the particular device to be distributed according to the
second mapping instead of the first mapping.” The Examiner finds that the
processing of interrupts, as discussed above, discloses these distributions.
See Ans. 4 and 8. Appellants contend that the Examiner erred because
“Jahnke is completely silent with respect to causing interrupts sent by the
particular device to be distributed first according to a first mapping and then
according to a second mapping.” App. Br. 10 – 11.
Appellants’ arguments are not persuasive of error in the Examiner’s
rejection. In particular, we agree with the Examiner that the initial uptake by
any one of four CPUs of an interrupt discloses a first interrupt distribution
while a subsequent interrupt assignment to a selected CPU discloses a
second interrupt distribution. See Ans. 8. Therefore, we agree with the
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Examiner that Jahnke discloses “causing interrupts sent by the particular
device to be distributed according to the first mapping” and “causing
interrupts sent by the particular device to be distributed according to the
second mapping instead of the first mapping,” as recited in claim 43.
Accordingly, we affirm the Examiner’s 35 U.S.C. § 102(b) rejection
of claim 43, and claims 44 – 60, which are not argued separately. See App.
Br. 11.
DECISION
The Examiner’s decision to reject claims 43 – 60 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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