Ex Parte so et al

Patent Trial and Appeal BoardNov 27, 2012

11212958 (P.T.A.B. Nov. 27, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/212,958 08/25/2005 Kimming So 3875.0780000 1031 26111 7590 11/28/2012 STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C. 1100 NEW YORK AVENUE, N.W. WASHINGTON, DC 20005 EXAMINER WU, QING YUAN ART UNIT PAPER NUMBER 2199 MAIL DATE DELIVERY MODE 11/28/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ________________ Ex parte KIMMING SO and JASON LEONARD ________________ Appeal 2010-007754 Application 11/212,958 Technology Center 2100 ________________ Before JEAN R. HOMERE, JASON V. MORGAN, and JOHNNY A. KUMAR, Administrative Patent Judges. MORGAN, Administrative Patent Judge. DECISION ON APPEAL Appeal 2010-007754 Application 11/212,958 2 STATEMENT OF THE CASE Introduction This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s Final Rejection of claims 1 – 14. We have jurisdiction under 35 U.S.C. § 6(b)(1). We affirm. Invention The invention relates to a system and method for inter-thread Communication using software interrupts in a multithread processor. Bits in a shared control register and/or a private control register can enable an inter- thread communication path. When the interrupt is triggered, one thread processor raises an interrupt in another thread processor. See Abstract. Exemplary Claim (Emphasis Added) 1. A method for inter-thread communication in a multithread processor, wherein the method comprises: selecting a software interrupt; enabling inter-thread communication with a first thread processor; enabling inter-thread communication with a second thread processor; interrupting the second thread processor with the software interrupt through inter-thread communication, wherein the first thread processor triggers the software interrupt. Rejections The Examiner rejects claims 1, 3 – 6, 8, 9, and 11 – 13 under 35 U.S.C. § 102(e) as being anticipated by Nemirovsky (US 7,020,879 B1; Mar. 28, 2006; filed May 14, 1999). Ans. 3 – 7. Appeal 2010-007754 Application 11/212,958 3 The Examiner rejects claims 2, 7, 10, and 14 under 35 U.S.C. § 103(a) as being unpatentable over Nemirovsky and Poisner (US 7,051,137 B2; May 23, 2006; filed Oct. 31, 2002). Ans. 7 – 8. ISSUES 1. Did the Examiner err in finding that Nemirovsky discloses “interrupting the second thread processor with the software interrupt through inter-thread communication, wherein the first thread processor triggers the software interrupt,” as recited in claim 1? 2. Did the Examiner err in finding that Nemirovsky discloses “wherein setting an inter-thread communication bit enables inter-thread communication between the first thread processor and the second thread processor,” as recited in claim 4? ANALYSIS Claim 1 The Examiner finds that Nemirovsky, which is directed to interrupt and exception handling for multi-streaming digital processors, discloses interrupting a second thread processor as claimed. See Ans. 4 (citing Nemirovsky col. 11, ll. 12 – 23, 29 – 31, and 35 – 37, col. 17, ll. 54 – 67, Abstract, and fig. 1B). Appellants contend the Examiner erred because in Nemirovsky “interrupt logic interrupts individual streams, and individual streams respond (acknowledge) by logic paths 411.” App. Br. 6 (citing Nemirovsky col. 16, ll. 20 – 21). Appellants argue that the arrangement of Nemirovsky “is exactly the type of disadvantageous system noted in the present application.” Id.; see also Reply Br. 4. Specifically, Appellants cite to the Specification’s Appeal 2010-007754 Application 11/212,958 4 disclosure that it is advantageous to provide for communication from one thread processor to another “directly and not through [a] system interconnect, e.g. [a] system bus.” App. Br. 6. However, as the Examiner correctly notes, “the lack of a system interconnect . . . was not recited in the rejected claim(s).” Ans. 10. Appellants’ arguments are therefore not commensurate with the scope of claim 1. Moreover, the Specification discloses the use of inter-thread communication paths. See, e.g., Spec. ¶ [0017] and Abstract. Thus, the broadest reasonable interpretation of interrupting “through inter-thread communication” encompasses the use of an inter-thread communications path. Appellants do not persuasively distinguish between an inter-thread communications path and Nemirovsky’s interrupt logic 407, which Appellants acknowledge “interconnects the streams.” See App. Br. 6. Therefore, we agree with the Examiner that Nemirovsky discloses triggering a software interrupt through inter-thread communication. Appellants further argue that the Examiner appears to be relying on Nemirovsky’s streams, but “the claimed thread processors are not merely ‘streams.’” App. Br. 10. In particular, Appellants submit that “Nemirovsky merely notes that the stream is a capability of the hardware, . . . not a processor itself.” Reply Br. 3. However, as the Examiner correctly points out, the Specification broadly describes “thread processors” as “execution elements.” Ans. 9 (citing Spec. ¶ [0013]). In particular, the Specification states that a concurrent multithread “processor 101 contains a set of execution elements, called the thread processors.” Spec. ¶ [0013]. We agree with the Examiner, Ans. 9, that a broad, but reasonable interpretation of the claimed thread processors (i.e., execution elements) encompasses Appeal 2010-007754 Application 11/212,958 5 Nemirovsky’s streams, which are hardware capabilities of a processor for supporting and processing instruction threads, which run within each stream, see Nemirovsky col. 1, ll. 37 – 41. Moreover, in Nemirovsky, software interrupts issued by active streams are processed by logic 407 to be handled and mapped. See Nemirovsky col. 17, ll. 61 – 63. Once logic 407 determines the mapping, streams are interrupted on logical paths 411. See Nemirvosky col. 17, ll. 16 – 17. The active stream may interrupt a mapped stream if the active stream has been granted the interrupt privilege for the mapped stream. See Nemirvosky fig. 1B and col. 6, ll. 45 – 47. Thus, Nemirovsky discloses a first thread processor (an active stream) triggering a software interrupt (if granted the interrupt privilege) to interrupt a second thread processor (for a mapped stream) through inter-thread communication (where the interrupt is processed by logic 407). Therefore, we agree with the Examiner that Nemirovsky discloses “interrupting the second thread processor with the software interrupt through inter-thread communication, wherein the first thread processor triggers the software interrupt,” as recited in claim 1 Accordingly, we affirm the Examiner’s rejection of claim 1, and of claims 2, 3, 6 – 12, and 14, which are not argued separately with sufficient specificity. See App. Br. 10 – 12. Claim 4 Claim 4 is dependent on claim 1 and further recites “wherein setting an inter-thread communication bit enables inter-thread communication between the first thread processor and the second thread processor.” The Examiner finds that this recitation is disclosed by Nemirovsky’s disclosure of setting a control bit in one stream’s control authorization bitmap to enable Appeal 2010-007754 Application 11/212,958 6 other streams “to interact/communicate with the stream.” Ans. 4 (citing Nemirovsky col. 5, l. 55 – col. 6, l. 47, col. 6, l. 56 – col. 7, l. 23, and fig. 1B). Appellants contend the Examiner erred, arguing that “the portions relied on by the Office Action to reject claim 4 relate to setting control bits, but not communication between first and second thread processors.” App. Br. 11. However, we agree with the Examiner that the cited disclosure in Nemirovsky is directed to enabling inter-thread communication. For example, Nemirovsky discloses a bit column for a stream’s bitmap labeled interrupts which indicates which streams have the interrupt privilege, meaning that they may interrupt that stream. See Nemirovsky col. 6, ll. 45 – 47. Claim 4 does not limit the meaning of enabling inter-thread communication, nor do Appellants direct our attention to any clear definition in the Specification. As such, we find that enabling interrupts falls within a broad, but reasonable meaning of enabling “inter-thread communication.” Moreover, Nemirovsky discloses generating interrupts for purposes “such as communicating between threads.” See Nemirovsky col. 15, ll. 22 – 24. Therefore, we agree with the Examiner that Nemirovsky discloses “wherein setting an inter-thread communication bit enables inter-thread communication between the first thread processor and the second thread processor,” as recited in claim 4. Accordingly, we affirm the Examiner’s rejection of claim 4, and claims 5 and 13, which are not argued separately with sufficient specificity. See App. Br. 12. Appeal 2010-007754 Application 11/212,958 7 DECISION The Examiner’s decision to reject claims 1 – 14 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED tj