Ex Parte Siguenza et al

Patent Trial and Appeal BoardJul 11, 2016

13757617 (P.T.A.B. Jul. 11, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 131757,617 02/01/2013 95671 7590 Synopsys/Fenwick Silicon Valley Center 801 California Street Mountain View, CA 94041 07113/2016 FIRST NAMED INVENTOR Oscar Siguenza UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 22524-22511 3782 EXAMINER LIN,ARIC ART UNIT PAPER NUMBER 2851 NOTIFICATION DATE DELIVERY MODE 07/13/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): ptoc@fenwick.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte OSCAR SIGUENZA, DUANE BREID, GENE SLUSS, DEEP AK SHERLEKAR, and MIKE COL WELL 1 Appeal2015-000893 Application 13/757,617 Technology Center 2800 Before CATHERINE Q. TIMM, CHRISTOPHER C. KENNEDY, and JENNIFER R. GUPTA, Administrative Patent Judges. KENNEDY, Administrative Patent Judge. DECISION ON APPEAL This is an appeal under 35 U.S.C. Â§ 134(a) from the Examiner's decision to reject claims 1-20. We have jurisdiction under 35 U.S.C. Â§ 6(b ). We AFFIRM. BACKGROUND The subject matter on appeal relates to a low power circuit design and selective power down of individual blocks of logic inside an integrated circuit. E.g., Spec. i-f 3; Claim 1. Claim 1 is reproduced below from page 10 (Claims Appendix) of the Appeal Brief: 1 According to the Appellants, the real party in interest is Synopsys, Inc. App. Br. 2. Appeal2015-000893 Application 13/757,617 1. A non-transitory computer-readable storage medium storing a representation of a power distribution structure surrounding a logic block in an integrated circuit (IC), the representation compnsmg: at least one enable cell connected to an enable rail configured to transmit a control signal; a first power gating cell comprising a first gating element configured to switch on or off a path between a power rail and at least one cell in the logic block according to the control signal received via the enable rail; a second gating cell comprising a second gating element configured to switch on or off a path between the power rail and the at least one cell, the second gating element having different voltage threshold characteristics or a different channel length compared to the first power gating element, the second gating cell derived from a same cell library as the first power gating cell; and at least one filler cell comprising a gating element having a gate terminal connected to receive the control signal. REJECTIONS ON APPEAL 1. Claims 1-20 stand rejected on the ground of nonstatutory double patenting over claims 1-7, 11, and 16 of U.S. Patent No. 8,392,862. 2. Claims 1, 4--10, and 13-17 stand rejected under 35 U.S.C. Â§ 103(a) as unpatentable over Eisenstadt et al. (US 2005/0091629 Al, published Apr. 28, 2005) in view of Burr (US 6,552,601 B 1, issued Apr. 22, 2003). 3. Claims 19 and 20 stand rejected under 35 U.S.C. Â§ 103(a) as unpatentable over Eisenstadt in view of Burr, further in view of Hazucha et al. (US 2005/0068015 Al, published Mar. 31, 2005) and Law (US 2003/0140322 Al, published July 24, 2003). 2 Appeal2015-000893 Application 13/757,617 ANALYSIS After review of the cited evidence in the appeal record and the opposing positions of the Appellants and the Examiner, we determine that the Appellants have not identified reversible error in the Examiner's rejections. Accordingly, we affirm the rejections for reasons set forth below, in the Final Action, and in the Examiner's Answer. See generally Final Act. 2-10; Ans. 2-9. Rejection 1 The Appellants do not address the double patenting rejection. Because the Appellants have not asserted any error in that rejection, we summarily affirm it. Rejections 2 and 3 All of the Appellants' arguments concern limitations that appear in claim 1. We select claim 1 as representative of the rejected claims, and the remaining claims on appeal will stand or fall with claim 1. The Appellants focus on the limitation "a second gating cell ... derived from a same cell library as the first power gating cell." According to the Examiner, that limitation is taught by Figures 7 and 20, and paragraphs 71, 72, and 80, of Eisenstadt. Final Act. 5. Eisenstadt, like the Appellants' disclosure, is directed to power management in integrated circuits, including the reduction of leakage current. E.g., Eisenstadt at Abstract, i-f 4; see also Fig. 2. Paragraph 71 teaches that Eisenstadt's "power-gating transistors can be implemented as standardized library macros." Paragraph 72 teaches that "[ t ]he optimum size or net channel width of I/O based power-gating transistors generally depends upon one or 3 Appeal2015-000893 Application 13/757,617 more of [several factors]." Paragraph 80 teaches that, in designing a power distribution structure, "[ d]ifferent applications will require different net power gating transistor sizes to meet their targeted drive strength and leakage current limitations." The Examiner finds that "Burr also discloses a second gating cell" as recited by claim 1. Final Act. 5. Burr, like Eisenstadt, is concerned with reduction of leakage current in integrated circuits. Burr at Abstract, 4:30- 34. The Examiner relies on Burr's teaching of an embodiment with two gating cells in which "threshold gating transistors 703 and 705 ... are each separately back biased by different voltage sources," Burr at 18:5-7, i.e., "hav[ e] different voltage threshold characteristics," as recited by claim 1. Final Act. 5. The Examiner concludes that "[i]t would have been obvious ... to combine the teachings of Eisenstadt and Burr[] in order to reduce leakage current in low power devices." Id. In the Appeal Brief, the Appellants argue that Eisenstadt does not teach the claimed "second gating cell." App. Br. 6-7. However, as the Examiner points out, the Appellants "present a cursory description of Eisenstadt that ignores several cited teachings." See Ans. 8. For example, the Appellants state, with no explanation, that "Eisenstadt at best discloses implementing power-gating transistors 'as standardized library macros that can about [sic] or be close to one side or both sides of the VDD core power macros."' App. Br. 6-7. The Examiner interprets that statement as an argument that Eisenstadt does not disclose the limitation "the second gating cell derived from a same cell library as the first power gating cell." See Ans. 4--5. Assuming that interpretation to be correct, the Appellants' mere assertion that the prior art does not teach a particular element, with no 4 Appeal2015-000893 Application 13/757,617 meaningful explanation, is unpersuasive. Cf 37 C.F.R. Â§ 41.37(c)(l)(iv) ("A statement which merely points out what a claim recites will not be considered an argument for separate patentability of the claim."); see also In re Lovin, 652 F.3d 1349, 1357 (Fed. Cir. 2011) (holding that "the Board reasonably interpreted Rule 41.3 7 to require more substantive arguments in an appeal brief than a mere recitation of the claim elements and a naked assertion that the corresponding elements were not found in the prior art"). The Examiner makes specific findings concerning Eisenstadt and the "same cell library" limitation, see Final Act. 8-9; Ans. 4--5, and the Appellants fail to address or show reversible error in those findings. See App. Br. 6-7; Reply Br. 2-3. On this record, a preponderance of the evidence supports the Examiner's finding that Eisenstadt teaches or suggests a second gating cell derived from the same library as the first gating cell. See In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) (even ifthe examiner failed to make a prima facie case, the Board would not have erred in framing the issue as one of reversible error because "it has long been the Board's practice to require an applicant to identify the alleged error in the examiner's rejections"). The Appellants also appear to contest the Examiner's reliance on i-fi-1 72 and 80 of Eisenstadt. See App. Br. 7. As above, however, their limited arguments consist of brief statements as to what Eisenstadt teaches, followed by a conclusory assertion that Eisenstadt does not teach the "second gating cell" limitation. Id. Those arguments are not persuasive because they ignore key portions of the paragraphs cited by the Examiner and fail to identify reversible error in the Examiner's findings and 5 Appeal2015-000893 Application 13/757,617 conclusions. See, e.g., Eisenstadt ilil 71, 72, 80; cf Lovin, 652 F.3d at 1357; Jung, 637 F.3d at 1365. The Appellants' argument concerning the Examiner's reliance on Burr is similarly limited, see App. Br. 8, and fails to provide any explanation concerning Burr's teaching that "threshold gating transistors 703 and 705 ... are each separately back biased by different voltage sources," Burr at 18:5- 7, which the Examiner relies on for the disclosure of gating elements "having different voltage threshold characteristics," see Final Act. 5. To the extent that the Appellants raise new arguments in the Reply Brief, see, e.g., Reply Br. 3, 5 (addressing the "same cell library" limitation), we decline to consider those arguments because the Appellants have not established good cause for failing to present those arguments in the opening Appeal Brief. See 37 C.F.R. Â§ 41.41(b)(2). We note that the relevant portions of the Final Action are substantively the same as the Examiner's Answer. Compare Final Act. 8-10 with Ans. 4--5. The Appellants have not identified reversible error in the Examiner's rejection of claim 1. CONCLUSION We AFFIRM the Examiner's rejection of claims 1-20. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. Â§ 1.136(a). AFFIRMED 6